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Electricity/FWLIB/include/ENS1_SPI.h

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第一次上传 矫正timer 实现GPIO19灯珠闪烁 尚未移植电刺激
2025-08-13 16:43:29 +08:00
/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_SPI.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
1 uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx)
2 uint8_t CLR_TX_FIFO(CMSDK_SPI_TypeDef* SPIx)
3 uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx)
4 uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
5 uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
6 SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx)
7 uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
8 uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
9 uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
10 uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
11 uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx)
12 uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx )
13 uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx )
14 uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET)
15 uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS)
16 uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , struct SPI_ModeConfig_Struct SPI_Config ,struct SPI_FIFO_Struct FIFO_Struct)
17 uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx)
18 uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx)
19 uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx )
20 void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data)
21 uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET)
History:
1.V1.0
Date:
Author:
Modification: <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
#ifndef ENS1_SPI_H
#define ENS1_SPI_H
#include "my_header.h"
/*
һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ź<EFBFBD>ϵ<EFBFBD><EFBFBD>
ALT Function2
SPI1_SCK --- GPIO16
SPI1_MOSI --- GPIO17
SPI1_MISO --- GPIO18
SPI1_NSS0 --- GPIO19
SPI1_NSS1 --- GPIO2
SPI1_NSS2 --- GPIO3
SPI1_NSS3 --- GPIO4
ALT Function2
SPI0_SCK --- GPIO8
SPI0_MOSI --- GPIO9
SPI0_MISO --- GPIO10
SPI0_NSS0 --- GPIO11
SPI0_NSS1 --- GPIO13
SPI0_NSS2 --- GPIO14
SPI0_NSS3 --- GPIO15
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>б<EFBFBD>˵<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD>ϵ<EFBFBD>ȫ˫<EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
˫<EFBFBD>߰<EFBFBD>˫<EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD><EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>䣨<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߣ<EFBFBD>
16*16bits FIFO <EFBFBD>շ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
4-16λ<EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>Сѡ<EFBFBD><EFBFBD>
<EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD>Fpclk/2
<EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD>Fpclk/4
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> NSS
<EFBFBD>ɱ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>Ӽ<EFBFBD><EFBFBD>Ժ<EFBFBD><EFBFBD><EFBFBD>λ
<EFBFBD>ɱ<EFBFBD><EFBFBD>̵<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˳<EFBFBD><EFBFBD><EFBFBD><EFBFBD>MSB<EFBFBD><EFBFBD>LSB<EFBFBD><EFBFBD>λ
DMA<EFBFBD>¼<EFBFBD>֧<EFBFBD><EFBFBD>
<EFBFBD>ж<EFBFBD>֧<EFBFBD><EFBFBD>
*/
typedef enum {MASTER = 1 ,SLAVE= 0}MASTER_SLAVE_SEL;
typedef enum {NSS0= 8 ,NSS1 ,NSS2 ,NSS3}NSS_CHANNEL_SEL ;
typedef enum {NOTBUSY = 0, BUSY}SPI_BUSY_STATE ;
typedef enum {EMPTY=0,FULL}FIFO_FULL_EMPTY_STATE;
struct SPI_ModeConfig_Struct
{
uint8_t BAUD_FPCLKdivx ; //<2F><><EFBFBD><EFBFBD><EFBFBD>ʷ<EFBFBD>Ƶϵ<C6B5><CFB5>
uint8_t SPI_MODE ; //SPI<50><49><EFBFBD><EFBFBD>ģʽ
uint8_t SPI_TRANS_MODE; //<2F><><EFBFBD><EFBFBD>ģʽѡ<CABD><D1A1>
MASTER_SLAVE_SEL MS_SEL; //<2F><><EFBFBD><EFBFBD>ģʽѡ<CABD><D1A1>
uint16_t CHAR_LEN ; //<2F><><EFBFBD>ô<EFBFBD><C3B4>䳤<EFBFBD><E4B3A4> <20><>4 - 16 bit<69><74>
NSS_CHANNEL_SEL NSSx ;
uint8_t SAMP_PHASE ;
};
struct SPI_FIFO_Struct //<2F><><EFBFBD><EFBFBD>FIFO<46><4F>DMA<4D><41><EFBFBD><EFBFBD>
{
uint8_t TX_FIFO_TH; // 0 - 16 char
uint8_t RX_FIFO_TH; // 0 - 16 char
bool FIFO_ENABLE_SET;
bool TXDMA_SET; //ѡ<><D1A1><EFBFBD>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>DMA(fifo<66><6F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>)
bool RXDMA_SET;
};
/* <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ܽṹ<DCBD><E1B9B9>
1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ղ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
3<EFBFBD><EFBFBD><EFBFBD>շ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD>
4<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ж<EFBFBD>
5<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ջ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿ<EFBFBD> <EFBFBD>ж<EFBFBD>
*/
//<2F>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define UNDERRUN_INT_EN (uint8_t)0x10
#define OVERRUN_INT_EN (uint8_t)0x8
#define CMPL_INT_EN (uint8_t)0x4
#define TXE_INT_EN (uint8_t)0x2
#define RXNE_INT_EN (uint8_t)0x1
//<2F>ж<EFBFBD><D0B6>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD>⵽<EFBFBD><E2B5BD>Ӧ<EFBFBD><D3A6><EFBFBD>ж<EFBFBD>
#define UNDERRUN_INT (uint8_t)0x10
#define OVERRUN_INT (uint8_t)0x8
#define CMPL_INT (uint8_t)0x4
#define TXE_INT (uint8_t)0x2
#define RXNE_INT (uint8_t)0x1
/*ģʽ<C4A3><CABD> | <20><><EFBFBD>߷<EFBFBD>ʽ<EFBFBD><CABD> <20><><EFBFBD><EFBFBD> <20>ӻ<EFBFBD>
ȫ˫<EFBFBD><EFBFBD> | MISO/MOSI MISO/MOSI
<EFBFBD><EFBFBD>˫<EFBFBD><EFBFBD> | MOSI MISO
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><EFBFBD>ӻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ | MOSI MOSI
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>գ<EFBFBD><EFBFBD>ӻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ | MISO MISO
SPI_TRANS_MODE <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2<EFBFBD>ߵ<EFBFBD><EFBFBD><EFBFBD> / 1<EFBFBD><EFBFBD>˫<EFBFBD><EFBFBD>
<EFBFBD><EFBFBD>+<EFBFBD><EFBFBD> / <EFBFBD><EFBFBD><EFBFBD><EFBFBD> /<EFBFBD><EFBFBD><EFBFBD><EFBFBD>/ <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> / <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
#define L2_UniDirect_TandR (uint8_t)0x0 //BIT[15:12] 0 0 00
#define L2_UniDirect_T (uint8_t)0x1 //BIT[15:12] 0 0 01
#define L2_UniDirect_R (uint8_t)0x2 //BIT[15:12] 0 0 10
#define L1_BiDirect_T (uint8_t)0x8 //BIT[15:12] 1 0 00
#define L1_BiDirect_R (uint8_t)0xc//BIT[15:12] 1 1 00
/*NSS<53><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
#define NSS_PULSE 1 //<2F><>nss
#define NO_NSS_PULSE 0 //û<><C3BB>nss
#define NSS_ASSERTED 0 //
#define NSS_DEASSERYED 1 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>nss<73>ź<EFBFBD>
#define NSS_CTRL_HW 0 //<2F><><EFBFBD><EFBFBD>ΪӲ<CEAA><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NSS
#define NSS_CTRL_SW 1 //<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NSS
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
#define BAUD_FPCLKdiv2 (uint8_t)0x0
#define BAUD_FPCLKdiv4 (uint8_t)0x1
#define BAUD_FPCLKdiv8 (uint8_t)0x2
#define BAUD_FPCLKdiv16 (uint8_t)0x3
#define BAUD_FPCLKdiv32 (uint8_t)0x4
#define BAUD_FPCLKdiv64 (uint8_t)0x5
#define BAUD_FPCLKdiv128 (uint8_t)0x6
#define BAUD_FPCLKdiv256 (uint8_t)0x7
/*SPI_MODE <20><><EFBFBD><EFBFBD>ģʽѡ<CABD><D1A1>*/
#define SPI_MODE0 (uint8_t)0x0 //bit[3:2] 00
#define SPI_MODE1 (uint8_t)0x1 // 01
#define SPI_MODE2 (uint8_t)0x2 // 10
#define SPI_MODE3 (uint8_t)0x3 // 11
/*SAMP_PHASE ѡ<><D1A1>*/
#define PRE_1_PCLK_PERIOD (uint8_t)0X0
#define SAMP_PHASE_NORMAL (uint8_t)0X1
#define DELAY_1_PCLK_PERIOD (uint8_t)0X2
#define DELAY_2_PCLK_PERIOD (uint8_t)0X3
/*****************************<2A><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD>***************************/
#define SPI0_CS_SET GPIO_SetOutput(GPIO_11)
#define SPI0_CS_RESET GPIO_ResetOutput(GPIO_11)
#define SPI1_CS_SET GPIO_SetOutput(GPIO_19)
#define SPI1_CS_RESET GPIO_ResetOutput(GPIO_19)
//<2F><>SPI<50><49>ǰ<EFBFBD><C7B0><EFBFBD>õ<EFBFBD>ģʽ
extern uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx);
/*<2A><><EFBFBD><EFBFBD>FIFO<46>ͼ<EFBFBD><CDBC><EFBFBD><EFBFBD><EFBFBD>0*/
extern uint8_t CLR_TX_FIFO(CMSDK_SPI_TypeDef* SPIx);
extern uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx) ;
/*FIFO ״̬<D7B4><CCAC>ȡ*/
extern uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx); //<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
extern uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx) ; //<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
extern SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx) ; //<2F><>ȡ<EFBFBD><C8A1>ǰSPI<50>Ƿ<EFBFBD><C7B7><EFBFBD>æ
extern uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) ; //<2F><>ǰ<EFBFBD><C7B0>ȡFIFO<46>Ƿ<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
extern uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) ; //<2F><>ǰ<EFBFBD><C7B0>ȡFIFO<46>Ƿ<EFBFBD>Ϊ<EFBFBD>գ<EFBFBD>
extern uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) ;//<2F><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>FIFO<46>Ƿ<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
extern uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) ; //<2F><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>FIFO<46>Ƿ<EFBFBD>Ϊ<EFBFBD>գ<EFBFBD>
extern uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx);
extern uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx ); //FIFO<46><4F><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
extern uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx ); //FIFO<46><4F><EFBFBD><EFBFBD>ʧ<EFBFBD><CAA7>
extern uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET); //DMA<4D><41><EFBFBD><EFBFBD>
extern uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS); //nssͨ<73><CDA8>ѡ<EFBFBD><D1A1>
extern uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , struct SPI_ModeConfig_Struct SPI_Config ,struct SPI_FIFO_Struct FIFO_Struct); //spi<70>ij<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
extern uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx);
extern uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx);
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>16bits
extern uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx );
//д<><D0B4><EFBFBD><EFBFBD>
extern void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data);
extern uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET);
#endif