381 lines
9.2 KiB
C
381 lines
9.2 KiB
C
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/*
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*Copyright ,2023 , NANOCHAP
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*File name: ENS1_SPI.C
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*Author:
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*Version: V1.0
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*Date: 2023-11-
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*Description:
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*Function List:
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History:
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1.V1.0
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Date:
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Author:
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Modification: <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*/
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#include "ENS1_SPI.h"
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#include "ENS1_GPIO.h"
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/*---------------------------------------------------fifo<66><6F><EFBFBD>صĺ<D8B5><C4BA><EFBFBD>ͷ--------------------------------------------------*/
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/*<2A><><EFBFBD><EFBFBD>FIFO<46>ͼ<EFBFBD><CDBC><EFBFBD><EFBFBD><EFBFBD>0*/
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uint8_t CLR_TX_FIFO( CMSDK_SPI_TypeDef* SPIx)
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{
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return (uint8_t)(SPIx->FCR>>8 & 0x1);
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}
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uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx)
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{
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return (uint8_t)(SPIx->FCR>>1 & 0x1);
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}
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/*FIFO ״̬<D7B4><CCAC>ȡ*/
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uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
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{
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return (uint8_t)(((SPIx->FCR & 0x1) == 0x1) ? ((uint8_t)((SPIx->FSR & 0x001f0000)>>16)):0); //<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
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}
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uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
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{
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return (uint8_t)(((SPIx->FCR & 0x1) == 0x1) ? ((uint8_t)((SPIx->FSR & 0x00001f00)>>8)):0); //<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD>ݳ<EFBFBD><DDB3><EFBFBD>
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}
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SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx)
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{
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return (SPI_BUSY_STATE)((((SPIx->FSR & 0x10) >> 4)==1) ? ( BUSY ) : ( NOTBUSY )); //<2F><>ȡ<EFBFBD><C8A1>ǰSPI<50>Ƿ<EFBFBD><C7B7><EFBFBD>æ
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}
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uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
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{
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return (uint8_t)((((SPIx->FSR & 0x8)>> 3 )==1) ? (1) : (0)) ; //<2F><>ǰ<EFBFBD><C7B0>ȡFIFO<46>Ƿ<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
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}
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uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
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{
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return (uint8_t)((((SPIx->FSR & 0x4) >> 2)==1) ? (1) : (0) ) ; //<2F><>ǰ<EFBFBD><C7B0>ȡFIFO<46>Ƿ<EFBFBD>Ϊ<EFBFBD>գ<EFBFBD>
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}
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uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
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{
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return (uint8_t)((((SPIx->FSR & 0x2) >> 1)==1) ? (1) : (0)) ; //<2F><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>FIFO<46>Ƿ<EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
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}
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uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
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{
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return (uint8_t)(((SPIx->FSR & 0x1)==1) ? (1) : (0)) ; //<2F><>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>FIFO<46>Ƿ<EFBFBD>Ϊ<EFBFBD>գ<EFBFBD>
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}
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/*FIFOʹ<4F><CAB9>/DMAʹ<41><CAB9>*/
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uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx) //<2F><>FIFO<46><4F><EFBFBD><EFBFBD>
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{
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return (uint8_t)(SPIx->FCR & 0x1) ;
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}
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uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx )
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{
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SPIx->FCR |= 0x1;
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return 0;//(uint8_t)(SPIx->FCR & 0x1) ;
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}
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uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx )
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{
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SPIx->FCR &=~ 0x1;
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return (uint8_t)(SPIx->FCR & 0x1) ;
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}
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uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET)
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{
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if(TXDMA_SET == true)
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SPIx->CTRL2 |= (1<<5);
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else if(TXDMA_SET == false)
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SPIx->CTRL2 &=~ (1<<5);
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if(TXDMA_SET == true)
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SPIx->CTRL2 |= (1<<4);
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else if(TXDMA_SET == false)
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SPIx->CTRL2 &=~ (1<<4);
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return (uint8_t)((SPIx->CTRL2>>4)&0x3);
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}
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/*------------------------------------------------------fifo<66><6F><EFBFBD>صĺ<D8B5><C4BA><EFBFBD>β--------------------------------------------------*/
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/*----------------------------------------------------------SPI<50><49><EFBFBD><EFBFBD>-------------------------------------------------------*/
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//<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0>SPIģʽ
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uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx)
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{
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return ((SPIx->CTRL1 & 0x7000) >> 12);
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}
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//NSSͨ<53><CDA8>ѡ<EFBFBD><D1A1>
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uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS)
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{
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if(ENorDIS == ENABLE)
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SPIx->CTRL2 |= ( 1 << NSSx );
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else
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SPIx->CTRL2 &=~ ( 1 << NSSx);
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return (uint8_t)((SPIx->CTRL2 & 0x0f00) >> 8);
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}
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//spi<70>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx ,
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struct SPI_ModeConfig_Struct SPI_Config,
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struct SPI_FIFO_Struct FIFO_Struct)
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{
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/*1<><31>GPIO ALTER*/
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if(SPIx == CMSDK_SPI1)
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{
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GPIO_AltFunction(GPIO_16 , ALT_FUNC2);
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GPIO_AltFunction(GPIO_17 , ALT_FUNC2);
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GPIO_AltFunction(GPIO_18 , ALT_FUNC2);
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GPIO_AltFunction(GPIO_19 , ALT_FUNC2);
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}
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else if(SPIx == CMSDK_SPI0)
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{
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GPIO_AltFunction(GPIO_8, ALT_FUNC1);
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GPIO_AltFunction(GPIO_9, ALT_FUNC1);
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GPIO_AltFunction(GPIO_10,ALT_FUNC1);
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GPIO_AltFunction(GPIO_11,ALT_FUNC1);
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}
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/*
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2<EFBFBD><EFBFBD>дSPI_CTRL1<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>Ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>BAUD_RATE[2:0]
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<EFBFBD><EFBFBD>2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>Ӽ<EFBFBD><EFBFBD>Ժ<EFBFBD><EFBFBD><EFBFBD>λ CPOL and CPHA bits
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<EFBFBD><EFBFBD>3<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ BIDI_EN, BIDI_MODE, UNIDI_MODE bits
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<EFBFBD><EFBFBD>4<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>LSB_SELλ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡<EFBFBD><EFBFBD>ʽ
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<EFBFBD><EFBFBD>5<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NSS_TOGGLE<EFBFBD><EFBFBD>NSS_MST_CTRL<EFBFBD><EFBFBD>NSS_MST_SW bits<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>NSS<EFBFBD><EFBFBD><EFBFBD>Ʒ<EFBFBD>ʽ bit11 9 8
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<EFBFBD><EFBFBD>6<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MST_SLV_SELλѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
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*/
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SPIx->CTRL1 = (SPIx->CTRL1&~ 0xffff) | ( SPI_Config.BAUD_FPCLKdivx << 4);
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SPIx->CTRL1 |= (SPI_Config.SPI_MODE << 2);
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SPIx->CTRL1 |= (SPI_Config.SPI_TRANS_MODE << 12 );
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SPIx->CTRL1 &=~ (0x1 << 7); //֡<><D6A1>ʽĬ<CABD>ϴ<EFBFBD><CFB4><EFBFBD>ģʽ
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SPIx->CTRL1 &=~ (0x1 << 8); //֡<><D6A1>ʽĬ<CABD>ϴ<EFBFBD><CFB4><EFBFBD>ģʽ
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SPIx->CTRL1 &=~ (1 << 11);
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SPIx->CTRL1 |= (1 << 11) ; // Ĭ<><C4AC>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NSS
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if(SPI_Config.MS_SEL == MASTER)
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{
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SPIx->CTRL1 |= (1<<1);
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}
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else
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{
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SPIx->CTRL1 &=~ (1<<1);
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}
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/*
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3<EFBFBD><EFBFBD>дSPI_CTRL2<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CHAR_LEN[3:0]λ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD>2<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>NSS<EFBFBD>˿ڡ<EFBFBD> NSS0_EN, NSS1_EN, NSS2_EN
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<EFBFBD><EFBFBD>3<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD>RX<EFBFBD><EFBFBD><EFBFBD>ݲɼ<EFBFBD><EFBFBD><EFBFBD> SAMP_PHASE(1:0)λ
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<EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>C2T_DELAY<EFBFBD><EFBFBD>T2C_DELAYλ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ը<EFBFBD><EFBFBD>ݴ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD>C2T/T2C<EFBFBD>ӳ<EFBFBD>
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<EFBFBD><EFBFBD>5<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>TXDMA_EN<EFBFBD><EFBFBD>RXDMA_ENλʹ<EFBFBD>ܻ<EFBFBD>ʹ<EFBFBD><EFBFBD>FIFOģʽ<EFBFBD><EFBFBD>TX/RX DMA<EFBFBD><EFBFBD>
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*/
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SPIx->CTRL2 = (SPIx->CTRL2&~ 0xffff);
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if(SPI_Config.CHAR_LEN < 4)
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{
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}
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else if((SPI_Config.CHAR_LEN >= 4) && (SPI_Config.CHAR_LEN < 17))
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{
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SPIx->CTRL2 |= (SPI_Config.CHAR_LEN -1);
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}
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else
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{
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}
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SPI_NSS_CHANNEL(SPIx ,SPI_Config.NSSx ,ENABLE);
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//rx<72><78><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD>λ<EFBFBD><CEBB> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>Ĭ<EFBFBD><C4AC>ѡnormal
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//C2T_DELAY ,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>Ч
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//T2C_DELAY, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>Ч
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if(SPI_Config.MS_SEL == MASTER)
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{
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SPIx->CTRL2 |= (SPI_Config.SAMP_PHASE << 6);
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//T2C <20><>Transmit-end-to-chip-inactive <20><><EFBFBD>ӳ<EFBFBD>ʱ<EFBFBD>䣬Ĭ<E4A3AC><C4AC>Ϊ1T SCK
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//C2T <20><>Chip-select-active-to-transmit-start <20><>ʱ<EFBFBD><CAB1> Ĭ<><C4AC>1T SCK ,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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}
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/*
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4<EFBFBD><EFBFBD>дFIFO <EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>TX_FIFO_TH<EFBFBD><EFBFBD>RX_FIFO_TH<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>崥<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
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<EFBFBD><EFBFBD>2<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>TX_FIFO_CLR<EFBFBD><EFBFBD>RX_FIFO_CLRλ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>TX/RX FIFO
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<EFBFBD><EFBFBD>3<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>fif_enλʹ<EFBFBD>ܻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FIFOģʽ
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*/
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SPIx->FCR |= (FIFO_Struct.TX_FIFO_TH << 9 );
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SPIx->FCR |= (FIFO_Struct.RX_FIFO_TH << 2 );
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CLR_TX_FIFO(SPIx) ;
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CLR_RX_FIFO(SPIx) ;
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if(FIFO_Struct.FIFO_ENABLE_SET == true)
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SPI_FIFO_ENABLE(SPIx);
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//SPI_FIFODMA_SET(SPIx ,FIFO_Struct.TXDMA_SET ,FIFO_Struct.RXDMA_SET);
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return 0;
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}
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/*---------------------------------------------SPI<50><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹͣ-------------------------------------------------*/
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uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx )
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{
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SPIx->CTRL1 |= (1);
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return (uint8_t)(SPIx->CTRL1 & 0x1);
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}
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uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx)
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{
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if((READ_SPI_MODE(SPIx)==(L2_UniDirect_R & 0x7)) || (READ_SPI_MODE(SPIx)==(L1_BiDirect_R & 0x7)))
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{
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if(SPI_FIFO_STATE(SPIx) == 1)
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{
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//<2F><> RX<52><58>FIFO ֱ<><D6B1> FIFO<46><4F><EFBFBD><EFBFBD>Ϊ 0
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while((RX_FIFO_LEN(SPIx) != 0) || (BUSY_STATE(SPIx) == BUSY))
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{
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//save_data = READ_SPI_RCVBuff(SPIx);
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}
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SPIx->CTRL1 &=~ (1);
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|
|
}
|
|||
|
|
else if(SPI_FIFO_STATE(SPIx) == 0)
|
|||
|
|
{
|
|||
|
|
while(BUSY_STATE(SPIx) == BUSY);
|
|||
|
|
SPIx->CTRL1 &=~ (1);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
if(SPI_FIFO_STATE(SPIx) == 1)
|
|||
|
|
{
|
|||
|
|
while((TX_FIFO_LEN(SPIx)!= 0) || (BUSY_STATE(SPIx) == BUSY));
|
|||
|
|
SPIx->CTRL1 &=~ (1);
|
|||
|
|
//<2F><> RX<52><58>FIFO ֱ<><D6B1> FIFO<46><4F><EFBFBD><EFBFBD>Ϊ 0
|
|||
|
|
while(RX_FIFO_LEN(SPIx) != 0)
|
|||
|
|
{
|
|||
|
|
uint16_t save_data = READ_SPI_RCVBuff(SPIx);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else if(SPI_FIFO_STATE(SPIx) == 0)
|
|||
|
|
{
|
|||
|
|
while(BUSY_STATE(SPIx) == BUSY);
|
|||
|
|
SPIx->CTRL1 &=~ (1);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
return (uint8_t)(SPIx->CTRL1*0x1);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*-----------------------------------------<2D><> / д SPI BUFFER<45><52><EFBFBD><EFBFBD><EFBFBD><EFBFBD>-------------------------------------------------*/
|
|||
|
|
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>16bits
|
|||
|
|
uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx)
|
|||
|
|
{
|
|||
|
|
return (uint16_t)(SPIx->RBR & 0xffff);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
//д<><D0B4><EFBFBD><EFBFBD>
|
|||
|
|
void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data)
|
|||
|
|
{
|
|||
|
|
SPIx->THR = data;
|
|||
|
|
while(BUSY_STATE(SPIx) == BUSY);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*------------------------------------------------------SPI<50>ж<EFBFBD>------------------------------------------------------*/
|
|||
|
|
uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET)
|
|||
|
|
{
|
|||
|
|
NVIC_DisableIRQ(IRQn);
|
|||
|
|
NVIC_ClearPendingIRQ(IRQn);
|
|||
|
|
if(IRQn == SPI0_IRQn)
|
|||
|
|
{
|
|||
|
|
CMSDK_SPI0->IER = ((CMSDK_SPI0->IER &~ (0xff)) | SPI_INT_BIT_SET);
|
|||
|
|
}
|
|||
|
|
else if(IRQn == SPI1_IRQn)
|
|||
|
|
{
|
|||
|
|
CMSDK_SPI1->IER = ((CMSDK_SPI0->IER &~ (0xff)) | SPI_INT_BIT_SET);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if(SPI_INT_ENABLE == true)
|
|||
|
|
{
|
|||
|
|
NVIC_EnableIRQ(IRQn);
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
NVIC_DisableIRQ(IRQn);
|
|||
|
|
}
|
|||
|
|
return 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
//<2F>жϴ<D0B6><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
/*
|
|||
|
|
<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD>
|
|||
|
|
1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ղ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
3<EFBFBD><EFBFBD><EFBFBD>շ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD>
|
|||
|
|
4<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD>ж<EFBFBD>
|
|||
|
|
5<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ջ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿ<EFBFBD> <EFBFBD>ж<EFBFBD>
|
|||
|
|
*/
|
|||
|
|
void SPI1_Handler(void)
|
|||
|
|
{
|
|||
|
|
NVIC_ClearPendingIRQ(SPI1_IRQn);
|
|||
|
|
uint8_t read_fifo=0;
|
|||
|
|
if((CMSDK_SPI1->INTSTATUS & 0x10 )== UNDERRUN_INT) //<2F><><EFBFBD><EFBFBD>-<2D><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
|||
|
|
{
|
|||
|
|
CMSDK_SPI1->INTCLEAR |= (1<<4); //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|||
|
|
}
|
|||
|
|
if((CMSDK_SPI1->INTSTATUS & 0x8) ==OVERRUN_INT)
|
|||
|
|
{
|
|||
|
|
CMSDK_SPI1->INTCLEAR |= (1<<3);
|
|||
|
|
}
|
|||
|
|
if((CMSDK_SPI1->INTSTATUS& 0x4) ==CMPL_INT)
|
|||
|
|
{
|
|||
|
|
CMSDK_SPI1->INTCLEAR |= (1<<2);
|
|||
|
|
}
|
|||
|
|
if((CMSDK_SPI1->INTSTATUS &0x2) ==TXE_INT)
|
|||
|
|
{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
if((CMSDK_SPI1->INTSTATUS & 1)== RXNE_INT)
|
|||
|
|
{
|
|||
|
|
|
|||
|
|
while(!RX_FIFO_EMPTY(CMSDK_SPI1))
|
|||
|
|
{
|
|||
|
|
read_fifo = READ_SPI_RCVBuff(CMSDK_SPI1);
|
|||
|
|
printf("masterrcv:%d\n",read_fifo);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void SPI0_Handler(void)
|
|||
|
|
{
|
|||
|
|
NVIC_ClearPendingIRQ(SPI0_IRQn);
|
|||
|
|
uint8_t read_fifo=0;
|
|||
|
|
if((CMSDK_SPI0->INTSTATUS & 0x10 )== UNDERRUN_INT) //<2F><><EFBFBD><EFBFBD>-<2D><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
|||
|
|
{
|
|||
|
|
CMSDK_SPI0->INTCLEAR |= (1<<4); //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|||
|
|
}
|
|||
|
|
if((CMSDK_SPI0->INTSTATUS & 0x8) ==OVERRUN_INT)
|
|||
|
|
{
|
|||
|
|
CMSDK_SPI0->INTCLEAR |= (1<<3);
|
|||
|
|
}
|
|||
|
|
if((CMSDK_SPI0->INTSTATUS& 0x4) ==CMPL_INT)
|
|||
|
|
{
|
|||
|
|
CMSDK_SPI0->INTCLEAR |= (1<<2);
|
|||
|
|
}
|
|||
|
|
if((CMSDK_SPI0->INTSTATUS &0x2) ==TXE_INT)
|
|||
|
|
{
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
if((CMSDK_SPI0->INTSTATUS & 1)== RXNE_INT)
|
|||
|
|
{
|
|||
|
|
|
|||
|
|
while(!RX_FIFO_EMPTY(CMSDK_SPI0))
|
|||
|
|
{
|
|||
|
|
read_fifo = READ_SPI_RCVBuff(CMSDK_SPI0);
|
|||
|
|
printf("masterrcv:%d\n",read_fifo);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|