93 lines
2.9 KiB
C
93 lines
2.9 KiB
C
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/*
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*Copyright (C),2023 , NANOCHAP
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*File name: ENS1_CLOCK.H
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*Author:
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*Version: V1.0
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*Date: 2023-11-
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*Description:
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*Function List:
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1 uint32_t ClockInitSet(Clock_ConfigStructure* CLOCKCONFIG);
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2 void ClockInit(void);
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3 uint8_t PCLK_Enable(uint8_t APB_CLKEN_POS);
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4 uint8_t PCLK_Disable(uint8_t APB_CLKEN_POS);
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History:
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1.V1.0
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Date:
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Author:
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Modification: <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*/
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#ifndef ENS1_CLOCK_H
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#define ENS1_CLOCK_H
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#include "my_header.h"
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#include "CMSDK_CM0.h"
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/*
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ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ṹ
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<EFBFBD><EFBFBD><EFBFBD>٣<EFBFBD>LSI RC / LSE OSC<EFBFBD><EFBFBD> --> LFCLK --> RTC / LCD
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD> (HSI RC / HSE ) --> SYSCLK --> <EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>AHB Prescaler<EFBFBD><EFBFBD>-----> SYSC / PMU / HCLK /SCLK /DCLK
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----><EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>APB Prescaler<EFBFBD><EFBFBD> --> PCLK
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*/
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extern uint32_t APB_Clock_Freq;
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//<2F><>Ƶѡ<C6B5><D1A1>
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//APB
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#define ENS1_APB_PCLK_DIV_1 0x0
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#define ENS1_APB_PCLK_DIV_2 0x4
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#define ENS1_APB_PCLK_DIV_4 0x5
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#define ENS1_APB_PCLK_DIV_8 0x6
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#define ENS1_APB_PCLK_DIV_16 0x7
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//AHB
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#define ENS1_AHB_HCLK_DIV_1 0X0
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#define ENS1_AHB_HCLK_DIV_2 0X4
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#define ENS1_AHB_HCLK_DIV_4 0X5
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#define ENS1_AHB_HCLK_DIV_8 0X6
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#define ENS1_AHB_HCLK_DIV_16 0X7
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typedef enum{HSI_4MHZ =0 , HSI_8MHZ=1 , HS_16MHZ=2 , HSI_32MHZ=3}HSI_FREQ_SEL;
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typedef enum{MCO_HSI=0, MCO_HSE ,MCO_LSI,MCO_LSE}MCU_CLOCK_OUTPUT_SEL; //mcuʱ<75><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
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typedef enum{LSI_AS_LFCLK =0, LSE_AS_LFCLK }LFCLK_SWITCH_SEL; //LFCLK<4C><4B><EFBFBD><EFBFBD>Դѡ<D4B4><D1A1>
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typedef enum{HSI_SYSCLK = 0 ,HSE_SYSCLK , LFCLK_SYSCLK}SYSTEM_CLOCK_SEL; //ѡ<><D1A1>ϵͳʱ<CDB3><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD>뿪stopģʽʱ<CABD><CAB1>ϵͳ<CFB5><CDB3>ǿ<EFBFBD><C7BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ00
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/*--------ʱ<>ӳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ýṹ<C3BD><E1B9B9>----------*/
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typedef struct ClockConfig
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{
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MCU_CLOCK_OUTPUT_SEL MCO_SEL; //<2F><><EFBFBD><EFBFBD>
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HSI_FREQ_SEL HSI_FREQ; //<2F>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>RCƵ<43><C6B5>ѡ<EFBFBD><D1A1>
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uint8_t HSE_OSC_FREQ; //<2F>ⲿ<EFBFBD><E2B2BF><EFBFBD>پ<EFBFBD><D9BE><EFBFBD>ʵ<EFBFBD><CAB5>Ƶ<EFBFBD>ʣ<EFBFBD><CAA3><EFBFBD>λMHZ<48><5A>
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uint16_t LSE_OSC_FREQ; //<2F>ⲿ<EFBFBD><E2B2BF><EFBFBD>پ<EFBFBD><D9BE><EFBFBD>ʵ<EFBFBD><CAB5>Ƶ<EFBFBD>ʣ<EFBFBD><CAA3><EFBFBD>λ1<CEBB><31>
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SYSTEM_CLOCK_SEL SYSCLK_SEL; //ϵͳʱ<CDB3><CAB1>Դ<EFBFBD><D4B4>ѡ<EFBFBD><D1A1>
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uint8_t ENS1_APB_PCLK_DIV_x; //PCLK<4C><4B>Ƶѡ<C6B5><D1A1>
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uint8_t ENS1_AHB_PCLK_DIV_x; //HCLK<4C><4B>Ƶѡ<C6B5><D1A1>
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LFCLK_SWITCH_SEL LFCLK_SW_SEL; //ѡ<><D1A1>lfclk<6C><6B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ,ΪRTC<54><43>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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}Clock_ConfigStructure;
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extern uint32_t ClockInitSet(Clock_ConfigStructure* CLOCKCONFIG);
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extern void ClockInit(void);
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//PCLK <20><>ʱ<EFBFBD><CAB1>λ
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#define UART0_PCLK_EN 0
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#define UART1_PCLK_EN 1
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#define SPI0_PCLK_EN 2
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#define SPI1_PCLK_EN 3
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#define I2C0_PCLK_EN 4
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#define I2C1_PCLK_EN 5
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#define WDT_PCLK_EN 6
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#define PWM_PCLK_EN 7
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#define TIMER0_PCLK_EN 8
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#define TIMER1_PCLK_EN 9
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#define DUAL_TIMER_PCLK_EN 10
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#define LCD_PCLK_EN 11
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#define WAVE_GEN_PCLK_EN 12
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#define ADC_PCLK_EN 13
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#define ANALOG_PCLK_EN 14
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#define RTC_PCLK_EN 15
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extern uint8_t PCLK_Enable(uint8_t APB_CLKEN_POS);
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extern uint8_t PCLK_Disable(uint8_t APB_CLKEN_POS);
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void HSE_ClockInit(uint32_t Clock_Freq);
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#endif
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