Electricity/FWLIB/source/ENS1_PWM.c

/*
*Copyright ,2023 , NANOCHAP
*File name:   ENS1_PWM.C         
*Author:      
*Version:     V1.0 
*Date:        2023-11-                  
*Description:  
*Function List: 
    
History: 
	1.V1.0
	Date:          
	Author: 
	Modification: <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/ 

#include "ens1_pwm.h"
//PWMx        ѡ<><D1A1>PWM<57><4D><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
//edge_mode   pwm<77><6D><EFBFBD><EFBFBD>ģʽ  Ĭ<>ϵ<EFBFBD><CFB5><EFBFBD>
//pulse_duty  ռ<>ձ<EFBFBD>  0-100 <20><><EFBFBD><EFBFBD>Щƫ<D0A9>
//freq_HZ     Ƶ<><C6B5>   <20><>λ HZ 
//pwmEnable   ʹ<><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void PWM_init(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue* PWM_Para ,  bool pwmEnable)  
{	
	if(PWMx > 6 || PWMx < 1)
		PWMx = IO16_PWM1;
	int pwmsel = PWMx-2;
	if(pwmsel<0)
		pwmsel = 0;
	if(PWM_Para->pwm_Duty_cycle>100)
		PWM_Para->pwm_Duty_cycle=100;
    //IO<49><4F><EFBFBD><EFBFBD>
	CMSDK_GPIO->ALTFH |= (0x01 << ((PWMx-1)*2));
	uint32_t pulse_width = (uint32_t)((uint8_t)APB_Clock_Freq / ((PRESCALE_PWM+1) * (PWM_Para->pwm_freq)));
	CMSDK_PWM->MR0 = pulse_width;   	
	/*ģʽ<C4A3><CABD> 1 <20><><EFBFBD><EFBFBD>ģʽ 2 ˫<><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 3 ˫<>߸<EFBFBD><DFB8><EFBFBD><EFBFBD><EFBFBD>*/
	if(PWM_Para->mode == pwm_single_mode)
	{
		//pwmͨ<6D><CDA8>1-6<><36>ijһ<C4B3><D2BB>ͨ<EFBFBD><CDA8><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
		*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(PWM_Para->pwm_Duty_cycle*CMSDK_PWM->MR0/100);
	}	
	else if(PWM_Para->mode == pwm_double_positive_mode)
	{	
		//pwmͨ<6D><CDA8>1-6<><36>ijһ<C4B3><D2BB>ͨ<EFBFBD><CDA8><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
		CMSDK_PWM->PCR |= (1<<pwmsel) ;
		if(PWMx < 6 || PWMx > 1)  //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>2-6
		{
			*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx-1))=(uint32_t)(0);
			*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(PWM_Para->pwm_Duty_cycle*pulse_width/100);
		}
	}
	else
	{
		CMSDK_PWM->PCR |= (1<<pwmsel) ;
		if(PWMx < 6 || PWMx >1)  //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>2-6
		{
			*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx-1))=(uint32_t)(pulse_width);
			*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)((100-PWM_Para->pwm_Duty_cycle)*pulse_width/100);
		}
	}
	
	CMSDK_PWM->PR = PRESCALE_PWM;//Prescale  
	CMSDK_PWM->LER |= (1)|(1<<PWMx);      //<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
	CMSDK_PWM->TCR |= (1<<1);             //<2F><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>
	CMSDK_PWM->MCR |= (1<<1)  ;           //<2F>жϲ<D0B6>ʹ<EFBFBD>ܺ͸<DCBA>λʹ<CEBB><CAB9>| ((PWMx*3+1)<<1)
	if(pwmEnable == true)
		CMSDK_PWM->PCR |= (0x01 << (PWMx+4));
	else
		CMSDK_PWM->PCR &=~ (0x01 << (PWMx+4));
}

void PWM_SetFreq(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue * PWM_Para )
{
	CMSDK_PWM->MR0 = (uint32_t)((uint8_t)APB_Clock_Freq/ ((PRESCALE_PWM+1) * (PWM_Para->pwm_freq))); 
}	
	
void PWM_SetDutyCycle_SingleMode(ENS1_PWM_CHANNEL PWMx  ,uint8_t DutyCycle)  //<2F><><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>
{
	PWM_OutputDisable(PWMx);
	CMSDK_PWM->LER &=~ (1<<PWMx);
	*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(DutyCycle* CMSDK_PWM->MR0/100);
	CMSDK_PWM->LER |= (1<<PWMx);
	PWM_OutputEnable(PWMx);
}

void PWM_SetDutyCycle_DoublePositiveMode(ENS1_PWM_CHANNEL PWMx  ,uint8_t DutyCycle)
{	
	if(PWMx < 2)
	{
		return ;
	}
	else 
	{
		PWM_OutputDisable(PWMx);
		CMSDK_PWM->LER &=~ (1<<PWMx);
		*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(DutyCycle*CMSDK_PWM->MR0/100);
	CMSDK_PWM->LER |= (1<<PWMx);
	PWM_OutputEnable(PWMx);
	}
}

void PWM_SetDutyCycle_DoubleNegtiveMode(ENS1_PWM_CHANNEL PWMx  ,uint8_t DutyCycle)
{
	if(PWMx < 2)
	{
		return ;
	}
	else 
	{
		PWM_OutputDisable(PWMx);
		CMSDK_PWM->LER &=~ (1<<PWMx);
		*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)((100-DutyCycle)*CMSDK_PWM->MR0/100);
	CMSDK_PWM->LER |= (1<<PWMx);
	PWM_OutputEnable(PWMx);
	}
}

void PWM_OutputDisable(ENS1_PWM_CHANNEL PWMx)
{
	CMSDK_PWM->PCR &=~ (0x01 << (PWMx+4));
}

void PWM_OutputEnable(ENS1_PWM_CHANNEL PWMx)
{
	CMSDK_PWM->PCR |= (0x01 << (PWMx+4));	
}

uint32_t pwm_irq_occurred_mr[7];
void PWM_Handler(void) {
//MR0 status interrupt
    if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR0_INT_STS_Msk)==CMSDK_PWM_MR0_INT_STS_Msk) {
    	CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR0_INT_STS_Msk;//Clear Interrupt
	pwm_irq_occurred_mr[0]++;
    }
//MR1 status interrupt
    if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR1_INT_STS_Msk)==CMSDK_PWM_MR1_INT_STS_Msk) {
    	CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR1_INT_STS_Msk;//Clear Interrupt
	pwm_irq_occurred_mr[1]++;
    }
//MR2 status interrupt
    if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR2_INT_STS_Msk)==CMSDK_PWM_MR2_INT_STS_Msk) {
    	CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR2_INT_STS_Msk;//Clear Interrupt
	pwm_irq_occurred_mr[2]++;
    }
//MR3 status interrupt
    if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR3_INT_STS_Msk)==CMSDK_PWM_MR3_INT_STS_Msk) {
    	CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR3_INT_STS_Msk;//Clear Interrupt
	pwm_irq_occurred_mr[3]++;
    }
//MR4 status interrupt
    if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR4_INT_STS_Msk)==CMSDK_PWM_MR4_INT_STS_Msk) {
    	CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR4_INT_STS_Msk;//Clear Interrupt
	pwm_irq_occurred_mr[4]++;
    }
//MR5 status interrupt
    if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR5_INT_STS_Msk)==CMSDK_PWM_MR5_INT_STS_Msk) {
    	CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR5_INT_STS_Msk;//Clear Interrupt
	pwm_irq_occurred_mr[5]++;
    }
//MR6 status interrupt
    if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR6_INT_STS_Msk)==CMSDK_PWM_MR6_INT_STS_Msk) {
    	CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR6_INT_STS_Msk;//Clear Interrupt	
	pwm_irq_occurred_mr[6]++;
    }    
}