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矫正timer 实现GPIO19灯珠闪烁 尚未移植电刺激
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Shocky 2025-08-13 16:43:29 +08:00
parent bc74efde35
commit e2e6670399
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Bin/ENS001_BASIC_PRJ.bin Normal file
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CORE/ARM/startup_CMSDK_CM0.s Normal file
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;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Cortex-M0 Core Device Startup File for
; * Device CMSDK_CM0
; * @version V3.01
; * @date 06. March 2012
; *
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD LVD_Handler ;
DCD RTC_Handler ;
DCD COMP0_Handler ;
DCD COMP1_Handler ;
DCD GPIO0_7_Handler ;
DCD GPIO8_15_Handler ;
DCD GPIO16_23_Handler ;
DCD MTP_Handler ;
DCD CHARGER_OK_Handler ;
DCD CHARGER_END_Handler ;
DCD ADC_Handler ;
DCD LCD_Handler ;
DCD UART0_Handler ;
DCD UART1_Handler ;
DCD SPI0_Handler ;
DCD SPI1_Handler ;
DCD I2C0_Event_Handler ;
DCD I2C0_Error_Handler ;
DCD I2C1_Event_Handler ;
DCD I2C1_Error_Handler ;
DCD PWM_Handler ;
DCD TIMER0_Handler ;
DCD TIMER1_Handler ;
DCD DUALTIMER_Handler ;
DCD OVER_TEMP_Handler ;
DCD WG_DRV_Handler ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT LVD_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT COMP0_Handler [WEAK]
EXPORT COMP1_Handler [WEAK]
EXPORT GPIO0_7_Handler [WEAK]
EXPORT GPIO8_15_Handler [WEAK]
EXPORT GPIO16_23_Handler [WEAK]
EXPORT MTP_Handler [WEAK]
EXPORT CHARGER_OK_Handler [WEAK]
EXPORT CHARGER_END_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT LCD_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT SPI0_Handler [WEAK]
EXPORT SPI1_Handler [WEAK]
EXPORT I2C0_Event_Handler [WEAK]
EXPORT I2C0_Error_Handler [WEAK]
EXPORT I2C1_Event_Handler [WEAK]
EXPORT I2C1_Error_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_Handler [WEAK]
EXPORT OVER_TEMP_Handler [WEAK]
EXPORT WG_DRV_Handler [WEAK]
LVD_Handler
RTC_Handler
COMP0_Handler
COMP1_Handler
GPIO0_7_Handler
GPIO8_15_Handler
GPIO16_23_Handler
MTP_Handler
CHARGER_OK_Handler
CHARGER_END_Handler
ADC_Handler
LCD_Handler
UART0_Handler
UART1_Handler
SPI0_Handler
SPI1_Handler
I2C0_Event_Handler
I2C0_Error_Handler
I2C1_Event_Handler
I2C1_Error_Handler
PWM_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_Handler
OVER_TEMP_Handler
WG_DRV_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

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/**************************************************************************//**
* @file startup_CMSDK_CM0.s
* @brief CMSIS Cortex-M0 Core Device Startup File for
* Device CMSDK_CM0
* @version V3.01
* @date 06. March 2012
*
* @note Should use with GCC for ARM Embedded Processors
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/*****************************************************************************/
/* startup_CMSDK_CM3.s: Startup file for CMSDK device series */
/*****************************************************************************/
/* Version: GNU Tools for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv6-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x200
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
/* Vector Table */
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long LVD_Handler /* 16+ 0: LVD Handler */
.long RTC_Handler /* 16+ 1: RTC Handler */
.long COMP0_Handler /* 16+ 2: Comp0 Handle */
.long COMP1_Handler /* 16+ 3: Comp1 Handler */
.long GPIO0_7_Handler /* 16+ 4: GPIO0_7 Handler */
.long GPIO8_15_Handler /* 16+ 5: GPIO8_15 Handler */
.long GPIO16_23_Handler /* 16+ 6: GPIO16_23 Handler */
.long MTP_Handler /* 16+ 7: MTP Handler */
.long CHARGER_OK_Handler /* 16+ 8: Charge ok Handler */
.long CHARGER_END_Handler /* 16+ 9: Charge end Handler */
.long ADC_Handler /* 16+10: ADC Handler */
.long LCD_Handler /* 16+11: LCD Handler */
.long UART0_Handler /* 16+12: UART0 Handler */
.long UART1_Handler /* 16+13: UART1 Handler */
.long SPI0_Handler /* 16+14: SPI0 Handler */
.long SPI1_Handler /* 16+15: SPI1 Handler */
.long I2C0_Event_Handler /* 16+16: I2C0 Event Handler */
.long I2C0_Error_Handler /* 16+17: I2C0 Error Handler */
.long I2C1_Event_Handler /* 16+18: I2C1 Event Handler */
.long I2C1_Error_Handler /* 16+19: I2C1 Error Handler */
.long PWM_Handler /* 16+20: PWM Handler */
.long TIMER0_Handler /* 16+21: Timer 0 Handler */
.long TIMER1_Handler /* 16+22: Timer 1 Handler */
.long DUALTIMER_Handler /* 16+23: Dual-Timer Handler */
.long OVER_TEMP_Handler /* 16+24: over temp Handler */
.long WG_DRV_Handler /* 16+25: Reserved Handler */
.long 0 /* 16+26: Reserved Handler */
.long 0 /* 16+27: Reserved Handler */
.long 0 /* 16+28: Reserved Handler */
.long 0 /* 16+29: Reserved Handler */
.long 0 /* 16+30: Reserved Handler */
.long 0 /* 16+31: Reserved Handler */
.size __isr_vector, . - __isr_vector
/* Reset Handler */
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
subs r2, r1
ble .LC3
movs r0, 0
.LC2:
str r0, [r1, r2]
subs r2, 4
bge .LC2
.LC3:
#endif /* __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
/* bl SystemInit */
ldr r0,=SystemInit
blx r0
#endif
bl _start
.pool
.size Reset_Handler, . - Reset_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
/* System Exception Handlers */
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
/* IRQ Handlers */
def_default_handler LVD_Handler
def_default_handler RTC_Handler
def_default_handler COMP0_Handler
def_default_handler COMP1_Handler
def_default_handler GPIO0_7_Handler
def_default_handler GPIO8_15_Handler
def_default_handler GPIO16_23_Handler
def_default_handler MTP_Handler
def_default_handler CHARGER_OK_Handler
def_default_handler CHARGER_END_Handler
def_default_handler ADC_Handler
def_default_handler LCD_Handler
def_default_handler UART0_Handler
def_default_handler UART1_Handler
def_default_handler SPI0_Handler
def_default_handler SPI1_Handler
def_default_handler I2C0_Event_Handler
def_default_handler I2C0_Error_Handler
def_default_handler I2C1_Event_Handler
def_default_handler I2C1_Error_Handler
def_default_handler PWM_Handler
def_default_handler TIMER0_Handler
def_default_handler TIMER1_Handler
def_default_handler DUALTIMER_Handler
def_default_handler OVER_TEMP_Handler
def_default_handler WG_DRV_Handler
/*
def_default_handler Default_Handler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
*/
.end

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

793
CORE/INCLUDE/core_cm0plus.h Normal file
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@ -0,0 +1,793 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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@ -0,0 +1,636 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

688
CORE/INCLUDE/core_cmInstr.h Normal file
View File

@ -0,0 +1,688 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file system_CMSDK_CM0.h
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for
* Device <Device>
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef SYSTEM_CMSDK_CM0_H
#define SYSTEM_CMSDK_CM0_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_CM0_H */

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/**************************************************************************//**
* @file system_CMSDK_CM0.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
* Device CMSDK
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "CMSDK_CM0.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (100000000UL) /* Oscillator frequency */
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemFrequency = XTAL; /*!< System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock = XTAL; /*!< Processor Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
SystemCoreClock = XTAL;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
SystemCoreClock = XTAL;
}

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>ENS001_BASIC_PRJ</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>/</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U941000024 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC2000 -FN1 -FF0NNC_ENS1_0x000_0x5F00 -FS010000000 -FL05F00</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>-U-O14 -O14 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC2000 -FN1 -FF0NNC_ENS1 -FS010000000 -FL06F00</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>39</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\USER\mian.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>283</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>268441304</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>C:\Users\admin\Desktop\---宸ヤ綔涓?--\0銆侀噸瑕佸唴瀹癸細ENS椹卞姩寮€鍙?缁堢増20231124\1銆丒NS_GPIO_DEMO\FWLIB\source\ENS1_UART.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\ENS001_BASIC_PRJ\FWLIB/source/ENS1_UART.c\283</Expression>
</Bp>
<Bp>
<Number>2</Number>
<Type>0</Type>
<LineNumber>36</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>268444878</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>C:\Users\admin\Desktop\---宸ヤ綔涓?--\0銆侀噸瑕佸唴瀹癸細ENS椹卞姩寮€鍙?缁堢増20231124\1銆丒NS_GPIO_DEMO\USER\mian.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\ENS001_BASIC_PRJ\USER/mian.c\36</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>unit_t</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>isel_t,0x0A</ItemText>
</Ww>
<Ww>
<count>2</count>
<WinNumber>1</WinNumber>
<ItemText>wavePara_type</ItemText>
</Ww>
</WatchWindow1>
<WatchWindow2>
<Ww>
<count>0</count>
<WinNumber>2</WinNumber>
<ItemText>FT_CURRENT_SAVE[4]</ItemText>
</Ww>
</WatchWindow2>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>0</SubType>
<ItemText>0X10006F00</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>USER</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\USER\mian.c</PathWithFileName>
<FilenameWithoutPath>mian.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>FWLIB</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FWLIB\source\ENS1_UART.c</PathWithFileName>
<FilenameWithoutPath>ENS1_UART.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FWLIB\source\ENS1_GPIO.c</PathWithFileName>
<FilenameWithoutPath>ENS1_GPIO.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FWLIB\source\ENS1_MTP.c</PathWithFileName>
<FilenameWithoutPath>ENS1_MTP.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FWLIB\source\ENS1_CLOCK.c</PathWithFileName>
<FilenameWithoutPath>ENS1_CLOCK.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FWLIB\source\retarget.c</PathWithFileName>
<FilenameWithoutPath>retarget.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\FWLIB\source\ENS1_TIMER.c</PathWithFileName>
<FilenameWithoutPath>ENS1_TIMER.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>HARDWARE</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
<Group>
<GroupName>SYSTEM</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
<Group>
<GroupName>CORE</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\CORE\system_CMSDK_CM0.c</PathWithFileName>
<FilenameWithoutPath>system_CMSDK_CM0.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>5</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\CORE\ARM\startup_CMSDK_CM0.s</PathWithFileName>
<FilenameWithoutPath>startup_CMSDK_CM0.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
</ProjectOpt>

470
ENS001_BASIC_PRJ.uvprojx Normal file
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@ -0,0 +1,470 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>ENS001_BASIC_PRJ</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pArmCC>5060750::V5.06 update 6 (build 750)::.\ARM_Compiler_5.06u7</pArmCC>
<pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARM_Compiler_5.06u7</pCCUsed>
<uAC6>8</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM0</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.Cortex_DFP.1.1.0</PackID>
<PackURL>https://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>ENS001_BASIC_PRJ</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name>$K\ARM\ARMCC\bin\fromelf.exe --bin --output=Bin\@L.bin !L</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<nBranchProt>0</nBranchProt>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>.\CORE\INCLUDE;.\USER;.\FWLIB\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>USER</GroupName>
<Files>
<File>
<FileName>mian.c</FileName>
<FileType>1</FileType>
<FilePath>.\USER\mian.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>FWLIB</GroupName>
<Files>
<File>
<FileName>ENS1_UART.c</FileName>
<FileType>1</FileType>
<FilePath>.\FWLIB\source\ENS1_UART.c</FilePath>
</File>
<File>
<FileName>ENS1_GPIO.c</FileName>
<FileType>1</FileType>
<FilePath>.\FWLIB\source\ENS1_GPIO.c</FilePath>
</File>
<File>
<FileName>ENS1_MTP.c</FileName>
<FileType>1</FileType>
<FilePath>.\FWLIB\source\ENS1_MTP.c</FilePath>
</File>
<File>
<FileName>ENS1_CLOCK.c</FileName>
<FileType>1</FileType>
<FilePath>.\FWLIB\source\ENS1_CLOCK.c</FilePath>
</File>
<File>
<FileName>retarget.c</FileName>
<FileType>1</FileType>
<FilePath>.\FWLIB\source\retarget.c</FilePath>
</File>
<File>
<FileName>ENS1_TIMER.c</FileName>
<FileType>1</FileType>
<FilePath>.\FWLIB\source\ENS1_TIMER.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>HARDWARE</GroupName>
</Group>
<Group>
<GroupName>SYSTEM</GroupName>
</Group>
<Group>
<GroupName>CORE</GroupName>
<Files>
<File>
<FileName>system_CMSDK_CM0.c</FileName>
<FileType>1</FileType>
<FilePath>.\CORE\system_CMSDK_CM0.c</FilePath>
</File>
<File>
<FileName>startup_CMSDK_CM0.s</FileName>
<FileType>2</FileType>
<FilePath>.\CORE\ARM\startup_CMSDK_CM0.s</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>ENS001_BASIC_PRJ</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

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EventRecorderStub.scvd Normal file
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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

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FWLIB/include/ENS1_ADC.h Normal file
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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_ADC.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS1_ADC_H
#define ENS1_ADC_H
#include "my_header.h"
/*
GPIO21 --- ADC 1
GPIO22 --- ADC 2
GPIO23 --- ADC 3
*/
extern uint16_t save_data;
extern uint8_t ADC_UART_BYTE_LOW ;
extern uint8_t ADC_UART_BYTE_HIGH ;
typedef enum { ENS1_PGA_TO_ADC = 0 ,ENS1_ADC_CHANNEL1 = 1,ENS1_ADC_CHANNEL2 = 2,ENS1_ADC_CHANNEL3 = 3}ENS_ADC_SEL;
//typedef enum { SINGLE_ADC_MODE = 0, CONTINUOUS_ADC_MODE = 1}ENS_ADC_COV_MODE;
//typedef enum { NOOVERRUN_ADC_MODE = 0, OVERRUN_ADC_MODE = 1}ENS_ADC_OVERRUN_MODE;
//typedef enum { NOWAIT_ADC_MODE = 0, WAIT_ADC_MODE = 1}WAIT_MODE;
typedef enum { NCOV_WITHOUT_RCV_EOC = 0 , COV_RCV_EOC = 1}ENS_ADC_COV_INC_EOC;
/*模式分类： MODE_SEL
单次采集
连续采集
OVERRUN
关闭OVERRUN
等待模式开启
等待模式关闭
*/
#define SINGLE_ADC_MODE 0
#define CONTINUOUS_ADC_MODE (1)
#define OVERRUN_ADC_MODE (1<<1)
#define WAIT_ADC_MODE (1<<2)
/*中断模式选择 INT_MODE_SEL */
#define DISABLE_INT (0)
#define ENABLE_EOC_INT (1)
#define ENABLE_OVERRUN_INT (1<<1)
/*
ADC读取状态
*/
#define ADC_READ_DATA_IS_WAITING 0x00
#define ADC_READ_DATA_IS_READY 0x01
/*
SIMLING_TIME
*/
#define ADC_SampleTime_2ADC_Clk ((uint8_t)0x00)
#define ADC_SampleTime_3ADC_Clk ((uint8_t)0x01)
#define ADC_SampleTime_4ADC_Clk ((uint8_t)0x02)
#define ADC_SampleTime_5ADC_Clk ((uint8_t)0x03)
/*
*/
#define ADC_CLK_base2div ((uint8_t)0x00)
#define ADC_CLK_base4div ((uint8_t)0x01)
#define ADC_CLK_base6div ((uint8_t)0x02)
#define ADC_CLK_base8div ((uint8_t)0x03)
#define ADC_CLK_base10div ((uint8_t)0x04)
#define ADC_CLK_base12div ((uint8_t)0x05)
#define ADC_CLK_base16div ((uint8_t)0x06)
#define ADC_CLK_base32div ((uint8_t)0x07)
/*
*/
#define single_mode_without_overrun_without_wait 0
#define single_mode_without_overrun_with_wait 4
#define single_mode_with_overrun_without_wait 2
#define single_mode_with_overrun_with_wait 6
#define continious_mode_without_overrun_without_wait 1
#define continious_mode_with_overrun_without_wait 3
#define Continious_mode_without_overun_with_wait 5
#define continious_mode_with_overrun_with_wait 7
/*
声明 ADC相关函数
*/
extern uint8_t ENS1_ADCCLKConfig(uint8_t ADC_CLK_div);
extern uint8_t ENS1_ADC_CONFIG(ENS_ADC_SEL channelx ,
uint8_t MODE_SEL,
ENS_ADC_COV_INC_EOC EOC_CONFIG ,
uint8_t SIMLING_TIME,
uint8_t INT_MODE_SEL);
extern uint8_t ENS1_ADC_START(ENS_ADC_SEL channelx);
extern uint8_t ENS1_ADC_STOP(ENS_ADC_SEL channelx);
extern uint16_t ADC_READ_DATA(void);
#endif

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FWLIB/include/ENS1_ANAC.h Normal file
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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_ANAC.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS1_ANAC_H
#define ENS1_ANAC_H
#include <stdio.h>
#include "CMSDK_CM0.h"
#include "my_header.h"
#include "ENS1_GPIO.h"
/*-------------------boost------------------------*/
extern uint8_t Boost_Voltage_Sel(uint8_t VOLTAGE_XV);
#define VOLTAGE_11V 0x0
#define VOLTAGE_15V 0x1
#define VOLTAGE_26V 0x2
#define VOLTAGE_45V 0x3
#define VOLTAGE_55V 0x4
/*-------------------比较器------------------------*/
/*
比较器IO复用说明
GPIO12 -- COMP1_VIP0
GPIO13 -- COMP1_VIP1
GPIO14 -- COMP1_VIN0
GPIO15 -- COMP1_VIN1
GPIO21 -- COMP1_OUT
GPIO8 -- COMP0_VIP0
GPIO9 -- COMP0_VIP1
GPIO10 -- COMP0_VIN0
GPIO11 -- COMP0_VIN1
GPIO20 -- COMP0_OUT
*/
#define COMP_VREF_VOLTAGE_0_3v (uint8_t)(0x0)
#define COMP_VREF_VOLTAGE_0_6v (uint8_t)(0x1)
#define COMP_VREF_VOLTAGE_0_9v (uint8_t)(0x2)
#define COMP_VREF_VOLTAGE_1_2v (uint8_t)(0x3)
#define COMP_VREF_VOLTAGE_1_5v (uint8_t)(0x4)
#define COMP_VREF_VOLTAGE_1_8v (uint8_t)(0x5)
#define COMP_VREF_VOLTAGE_2_1v (uint8_t)(0x6)
#define COMP_VREF_VOLTAGE_2_4v (uint8_t)(0x7)
#define COMP_NEG_INPUT_VIN0 (uint8_t)(0x0)
#define COMP_NEG_INPUT_VIN1 (uint8_t)(0x1)
#define COMP_NEG_INPUT_VREF (uint8_t)(0x2)
#define COMP_POS_INPUT_VIP0 (uint8_t)(0x1)
#define COMP_POS_INPUT_VIP1 (uint8_t)(0x2)
typedef enum{COMP0=0, COMP1}COMP_NUM;
typedef struct COMPConfig
{
COMP_NUM COMPARATOR_NUM;
uint8_t COMP_VREF_SEL;
uint8_t COMP_SIGSEL_NEGATIVE_INPUT_SEL;
uint8_t COMP_SIGSEL_POSITIVE_INPUT_SEL;
}COMP_ConfigStructure;
/*比较器的输出设置*/
extern void CompInitSet(COMP_ConfigStructure* COMPCONFIG);
/*读比较结果*/
extern uint8_t Read_Comp_Output(COMP_NUM NUM);
/*开启/关闭比较器*/
extern void CompControl(COMP_NUM NUM ,FunctionalState Newstate);
/*-----------------------------PGA------------------------------*/
/*
PGA IO复用说明
GPIO16 -- PGA_VIP0 //输入信号直连
GPIO18 -- PGA_VIN0 //需要接入电阻
GPIO17 -- PGA_VIP1 //输入信号直连
GPIO19 -- PGA_VIN1 //需要接入电阻
GPIO20 -- PGA_EXVCM
GPIO4 -- PGA_OUT
*/
//#define PGA_POSITIVE_INPUT_VBAT (uint8_t)(0x3)
//#define PGA_POSITIVE_INPUT_AVDD1P8 (uint8_t)(0x4)
//#define PGA_POSITIVE_INPUT_VLCD0 (uint8_t)(0x5)
//#define PGA_POSITIVE_INPUT_V_TEMP (uint8_t)(0x7)
//PGA放大倍数选择 ，对于反相模式： 1-8 倍， 同相模式2-9倍
#define PGA_GAIN_1X_2X (uint8_t)(0x0)
#define PGA_GAIN_2X_3X (uint8_t)(0x1)
#define PGA_GAIN_3X_4X (uint8_t)(0x2)
#define PGA_GAIN_4X_5X (uint8_t)(0x3)
#define PGA_GAIN_5X_6X (uint8_t)(0x4)
#define PGA_GAIN_6X_7X (uint8_t)(0x5)
#define PGA_GAIN_7X_8X (uint8_t)(0x6)
#define PGA_GAIN_8X_9X (uint8_t)(0x7)
typedef enum{PGA_NEGATIVE_INPUT_PGA_VIN0 = 0,PGA_NEGATIVE_INPUT_PGA_VIN1, PGA_NEGATIVE_INPUT_INTERNAL_VCM,PGA_NEGATIVE_INPUT_EXTERNAL_VCM}PGA_NEG_SEL;
typedef enum{PGA_POSITIVE_INPUT_PGA_VIP0 = 0,PGA_POSITIVE_INPUT_PGA_VIP1=1,PGA_POSITIVE_INPUT_INTERNAL_VCM=2,PGA_POSITIVE_INPUT_VREF1_2V=6}PGA_POS_SEL;
typedef enum{PGA_TO_GPIO4=0 , PGA_TO_ADC=1}PGA_OUTPUT_SEL;
typedef struct PGAConfig
{
PGA_NEG_SEL PGA_NEG_SELx ;
PGA_POS_SEL PGA_POS_SELx ;
uint8_t PGA_GAIN_SEL ;
PGA_OUTPUT_SEL PGA_OUT ;
}PGA_ConfigStructure;
//初始化
extern void PGAInitSet(PGA_ConfigStructure* PGACONFIG );
//PGA开关控制
extern void PGAControl(FunctionalState Newstate);
/*--------------------------低电压与芯片过温检测-------------------------*/
void PMU_TEMP150C_TRIGControl(FunctionalState Newstate); //过温检测功能开启与关闭
//返回温度是否超过150度的状态值
int8_t TEMP_150C_TRIG_SIGNAL(void);
#define LVD_4P2V (uint8_t)(0x0)
#define LVD_3P9V (uint8_t)(0x1)
#define LVD_3P6V (uint8_t)(0x2)
#define LVD_3P3V (uint8_t)(0x3)
#define LVD_3P0V (uint8_t)(0x4)
#define LVD_2P7V (uint8_t)(0x5)
#define LVD_2P4V (uint8_t)(0x6)
#define LVD_2P1V (uint8_t)(0x7)
//低电压告警
//设置阈值电压
void LVD_InitSet(uint8_t Threshold_voltage);
//打开或关闭此功能
void PMU_LVD_Control(FunctionalState Newstate);
//读取低电压状态
uint8_t Read_LVD_Signal(void);
/*-------------------------带隙BUFFER启用或关闭-------------------------*/
void PMU_BANDGAP_CONTROL(FunctionalState Newstate);
#endif

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#ifndef ENS1_BOOST_H
#define ENS1_BOOST_H
#include "my_header.h"
extern uint8_t Boost_Voltage_Sel(uint8_t VOLTAGE_XV);
#define VOLTAGE_11V 0x0
#define VOLTAGE_15V 0x1
#define VOLTAGE_26V 0x2
#define VOLTAGE_45V 0x3
#define VOLTAGE_55V 0x4
#endif

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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_CLOCK.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
1 uint32_t ClockInitSet(Clock_ConfigStructure* CLOCKCONFIG);
2 void ClockInit(void);
3 uint8_t PCLK_Enable(uint8_t APB_CLKEN_POS);
4 uint8_t PCLK_Disable(uint8_t APB_CLKEN_POS);
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS1_CLOCK_H
#define ENS1_CLOCK_H
#include "my_header.h"
#include "CMSDK_CM0.h"
/*
时钟树结构
低速（LSI RC / LSE OSC） --> LFCLK --> RTC / LCD
高速 (HSI RC / HSE ) --> SYSCLK --> 分频（AHB Prescaler）-----> SYSC / PMU / HCLK /SCLK /DCLK
|
|
|
---->分频（APB Prescaler） --> PCLK
*/
extern uint32_t APB_Clock_Freq;
//分频选择
//APB
#define ENS1_APB_PCLK_DIV_1 0x0
#define ENS1_APB_PCLK_DIV_2 0x4
#define ENS1_APB_PCLK_DIV_4 0x5
#define ENS1_APB_PCLK_DIV_8 0x6
#define ENS1_APB_PCLK_DIV_16 0x7
//AHB
#define ENS1_AHB_HCLK_DIV_1 0X0
#define ENS1_AHB_HCLK_DIV_2 0X4
#define ENS1_AHB_HCLK_DIV_4 0X5
#define ENS1_AHB_HCLK_DIV_8 0X6
#define ENS1_AHB_HCLK_DIV_16 0X7
typedef enum{HSI_4MHZ =0 , HSI_8MHZ=1 , HS_16MHZ=2 , HSI_32MHZ=3}HSI_FREQ_SEL;
typedef enum{MCO_HSI=0, MCO_HSE ,MCO_LSI,MCO_LSE}MCU_CLOCK_OUTPUT_SEL; //mcu时钟输出选择
typedef enum{LSI_AS_LFCLK =0, LSE_AS_LFCLK }LFCLK_SWITCH_SEL; //LFCLK输入源选择
typedef enum{HSI_SYSCLK = 0 ,HSE_SYSCLK , LFCLK_SYSCLK}SYSTEM_CLOCK_SEL; //选择系统时钟源，在离开stop模式时，系统会强制设置为00
/*--------时钟初始化配置结构体----------*/
typedef struct ClockConfig
{
MCU_CLOCK_OUTPUT_SEL MCO_SEL; //输入
HSI_FREQ_SEL HSI_FREQ; //内部高速RC频率选择
uint8_t HSE_OSC_FREQ; //外部高速晶振实际频率（单位MHZ）
uint16_t LSE_OSC_FREQ; //外部低速晶振实际频率（单位1）
SYSTEM_CLOCK_SEL SYSCLK_SEL; //系统时钟源的选择
uint8_t ENS1_APB_PCLK_DIV_x; //PCLK分频选择
uint8_t ENS1_AHB_PCLK_DIV_x; //HCLK分频选择
LFCLK_SWITCH_SEL LFCLK_SW_SEL; //选择lfclk的输入源,为RTC的时钟输入
}Clock_ConfigStructure;
extern uint32_t ClockInitSet(Clock_ConfigStructure* CLOCKCONFIG);
extern void ClockInit(void);
//PCLK 的时钟位
#define UART0_PCLK_EN 0
#define UART1_PCLK_EN 1
#define SPI0_PCLK_EN 2
#define SPI1_PCLK_EN 3
#define I2C0_PCLK_EN 4
#define I2C1_PCLK_EN 5
#define WDT_PCLK_EN 6
#define PWM_PCLK_EN 7
#define TIMER0_PCLK_EN 8
#define TIMER1_PCLK_EN 9
#define DUAL_TIMER_PCLK_EN 10
#define LCD_PCLK_EN 11
#define WAVE_GEN_PCLK_EN 12
#define ADC_PCLK_EN 13
#define ANALOG_PCLK_EN 14
#define RTC_PCLK_EN 15
extern uint8_t PCLK_Enable(uint8_t APB_CLKEN_POS);
extern uint8_t PCLK_Disable(uint8_t APB_CLKEN_POS);
void HSE_ClockInit(uint32_t Clock_Freq);
#endif

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_EXTI.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS1_EXTI_H
#define ENS1_EXTI_H
#include "my_header.h"
/*
0-23 : GPIO
24 : LVD output
25 : COMP0 output
26 : COMP1 output
27 : charge_ok
28 : charge_end
29 : over temperature
30 : rtc_alarm
31 : rtc_wut
*/
typedef enum {
EXTI_GPIO0=0,
EXTI_GPIO1=1,
EXTI_GPIO2=2,
EXTI_GPIO3=3,
EXTI_GPIO4=4,
EXTI_GPIO5=5,
EXTI_GPIO6=6,
EXTI_GPIO7=7,
EXTI_GPIO8=8,
EXTI_GPIO9=9,
EXTI_GPIO10=10,
EXTI_GPIO11=11,
EXTI_GPIO12=12,
EXTI_GPIO13=13,
EXTI_GPIO14=14,
EXTI_GPIO15=15,
EXTI_GPIO16=16,
EXTI_GPIO17=17,
EXTI_GPIO18=18,
EXTI_GPIO19=19,
EXTI_GPIO20=20,
EXTI_GPIO21=21,
EXTI_GPIO22=22,
EXTI_GPIO23=23,
EXTI_LVDOUTPUT=24,
EXTI_COMP0=25,
EXTI_COMP1=26,
EXTI_CHARGE_OK=27,
EXTI_CHARGE_END=28,
EXTI_OVER_TEMP=29,
}EXTI_NUM;
/*
寄存器：
EXTI_RTSR: 上升沿触发选择寄存器
EXTI_FTSR: 下降沿触发选择寄存器
EXTI_SWIER: 软件中断事件
EXTI_RPR: 上升沿挂起寄存器
EXTI_FPR: 下降沿挂起寄存器
EXTI_IMR: 带中断掩码的CPU唤醒寄存器
EXTI_EMR: 带有事件掩码的CPU唤醒寄存器
*/
/*每一位在相应的线路上使能/失能事件或中断的上升沿触发 0-29*/
void EXTI_RisingTriggerSelect(EXTI_NUM NUM , FunctionalState newstate);
/*每一位在相应的线路上使能/失能事件或中断的下降沿触发 0-29*/
void EXTI_FallingTriggerSelect(EXTI_NUM NUM ,FunctionalState newstate);
/*软件中断设置：通过软件设置某一位的上升沿发生从而导致上升沿中断（软件中断）发生，仅仅可写 0-29*/
void EXTI_SoftwareInterruptEventSet(EXTI_NUM NUM);
/*读取上升沿触发请求数据（用于判断上升沿事件发生）*/
bool Read_EXTI_RisingEdgePending(EXTI_NUM NUM);
/*读取下降沿触发请求数据（用于判断下降沿事件发生）*/
bool Read_EXTI_FallingEdgePending(EXTI_NUM NUM);
/*清除/屏蔽 唤醒CPU的中断线（0：用被屏蔽的中断唤醒 1：用未被屏蔽的中断唤醒）0-31*/
void EXTI_INT_MASK(uint8_t NUM);
/*设置/清除 事件生成唤醒CPU */
void EXTI_EVENT_MASK(uint8_t NUM);
#endif

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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_GPIO.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
1 uint8_t GPIO_AltFunction(GPIO_NUM GPIO_X , GPIO_AltFuncSel GPIO_AltFuncSelx);
2 int8_t GPIO_IO_Select(GPIO_NUM GPIO_X, I_O_SELECT INorOUT ,FunctionalState ENABLEorNOT);
3 uint8_t GPIO_GetInputValue(GPIO_NUM GPIO_X);
4 uint8_t GPIO_GetOutputValue(GPIO_NUM GPIO_X);
5 void GPIO_Output(GPIO_NUM GPIO_X,LEVELStatus HIGHorLOW);
6 void GPIO_SetOutput(GPIO_NUM GPIO_X);
7 void GPIO_ResetOutput(GPIO_NUM GPIO_X);
8 void GPIO_Overturn(GPIO_NUM GPIO_X);
9 void GPIO_AnalogChannel_Control(GPIO_NUM GPIO_X ,FunctionalState ENABLEorNOT );
History:
1.V1.0
Date:
Author:
Modification: ³õ°æ
*/
#ifndef ENS1_GPIO_H
#define ENS1_GPIO_H
#include "my_header.h"
#include "CMSDK_CM0.h"
extern uint8_t GPIO_AltFunction(GPIO_NUM GPIO_X , GPIO_AltFuncSel GPIO_AltFuncSelx);
extern int8_t GPIO_IO_Select(GPIO_NUM GPIO_X, I_O_SELECT INorOUT ,FunctionalState ENABLEorNOT);
extern uint8_t GPIO_GetInputValue(GPIO_NUM GPIO_X);
extern uint8_t GPIO_GetOutputValue(GPIO_NUM GPIO_X);
extern void GPIO_Output(GPIO_NUM GPIO_X,LEVELStatus HIGHorLOW);
extern void GPIO_SetOutput(GPIO_NUM GPIO_X);
extern void GPIO_ResetOutput(GPIO_NUM GPIO_X);
extern void GPIO_Overturn(GPIO_NUM GPIO_X);
extern void GPIO_AnalogChannel_Control(GPIO_NUM GPIO_X ,FunctionalState ENABLEorNOT );
#endif

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_I2C.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS1_IIC_H
#define ENS1_IIC_H
#include "my_header.h"
#include "ens1_uart.h"
#include "ENS1_GPIO.h"
/*
一、引脚关系：
ALT Function1
IIC0 SCL --- GPIO6
IIC0 SDA --- GPIO7
ALT Function2
IIC1 SCL --- GPIO8
IIC1 SDA --- GPIO9
ENS1 IIC ：
1、标准模式100khz 快速模式 400khz
2、DMA
3、主机模式下通过软件发出启停信号
4、从机模式下，接口可以识别自己的地址和一般呼叫地址，一般呼叫地址监测可以通过软件使能或失能
5、数据和地址的传输以8位，大端模式，开始后的字节包含地址信息，（7bit地址模式是一字节，10bit地址模式是2字节）
地址总时在主机模式下传输。
6、在一个字节传输的8个时钟周期后的第九个时钟，接收端必须发送一个应答位给传输端
应答可以被软件使能或者失能，可以通过软件选择地址是7位还是10位的。
特性说明：
1、可做主、从端
2、半双工通讯（仅发送或接收）
3、7位 / 10位的寻址或检测
4、支持不同传输速率： 100k 400k
5、模拟噪声滤波器
6、状态标志：
（1）传输/接收模式标志
（2）字节结束传输标志
（3）IIC 繁忙标志
7、数据总是大端模式
8、错误标志：
（1）主模式下:仲裁丢失状态
（2）地址 / 数据传输后应答失败
（3）错位启动或停止 状态的检测
9、1字节缓冲带有DMA功能
*/
/*
错误状态（会造成通讯失败）
1 总线错误 BUS ERROR
2 应答错误 AD
3 仲裁
4 溢出/下溢 错误
*/
/*IIC 速度选择*/
#define IIC_STARDARD_MODE_10K 0x0
#define IIC_STARDARD_MODE_20K 0x1
#define IIC_STARDARD_MODE_100K 0x9
#define IIC_FAST_MODE_110K 0xA
#define IIC_FAST_MODE_120K 0xB
#define IIC_FAST_MODE_400K 0x27
#define IIC_HIGH_MODE_500K 0x28
#define IIC_HIGH_MODE_600K 0x29
#define IIC_HIGH_MODE_1500K 0x2E
/*中断使能*/
#define IIC_ITERREN (1<<6) //error 使能
#define IIC_ITEVTEN (1<<7) //事件中断使能
#define IIC_ITBUFEN (1<<8) //缓冲区中断使能
#define IIC_DMAEN (1<<9) //DMA使能
typedef enum{IIC_MASTER=0, IIC_SLAVE=1}IIC_MODE ;
typedef struct IIC_Config_Struct
{
IIC_MODE MODE;
uint32_t OWN_ADDRESS;
bool ACK_EN;
uint8_t IIC_SPEED;
}IIC_ConfigStructure;
extern IIC_ConfigStructure IIC0_Config;
extern IIC_ConfigStructure IIC1_Config;
//bus error 判断（ITERREN使能）
extern bool IIC_BUS_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//应答错误判断
extern bool IIC_ACK_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//仲裁
extern bool IIC_ARBITRAT_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//溢出/下溢错误
extern bool IIC_OVERRUN_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//ITEVFEN使能后有如下事件
//起始状态，起始位发送（主机模式）
extern bool IIC_SB_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//地址发送（主机模式） / 地址匹配（从机事件）
extern bool IIC_ADDR_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//主机模式下，主机已发送10bit地址数据的第一个字节！！！
extern bool IIC_ADD10_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//从机模式下，停止条件被接收到
extern bool IIC_STOPF_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//数据字节传输成功
extern bool IIC_BTF_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//ITEVFEN 且 ITBUFEN 使能后，有如下事件
//数据寄存器非空（接受器读到数据）
extern bool IIC_RxNE_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//数据寄存器空（传输完数据）
extern bool IIC_TxE_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//总线状态：繁忙与否
extern uint8_t IIC_Bus_BUSY(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//模式确认
extern bool IIC_MASTER_MODE(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//IIC配置初始化
extern uint8_t IIC_Config_init(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,IIC_ConfigStructure* IIC_Para );
//使能与失能IIC
extern void IIC_Cmd(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,FunctionalState NewState) ;
//应答选择
extern void IIC_Ackconfig(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,FunctionalState NewState );
//生成START 信号
extern void IIC_GenerateSTART(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//生成STOP信号
extern void IIC_GenerateSTOP(CMSDK_I2C_TypeDef* CMSDK_I2Cx);
//IIC发送数据
extern void IIC_SendData(CMSDK_I2C_TypeDef* CMSDK_I2Cx , uint8_t data);
extern void IIC_ITConfig(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,uint16_t IIC_IT_SEL ,FunctionalState NewState);
#endif

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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_MTP.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
1 uint8_t MTP_init(void);
2 void MTP_TRIM(STRUCT_MTP_TRIM TRIM);
3 void flash_read(uint32_t start_addr,uint16_t *test_i);
4 int8_t flash_buff_write(uint32_t start_addr, uint16_t *buff);
5 int8_t flash_write_ctrl(uint16_t *buff , uint32_t start_addr);
6 int8_t write_data(void);
History:
1.V1.0
Date:
Author:
Modification: ³õ°æ
*/
#ifndef ENS1_MTP_H
#define ENS1_MTP_H
#include "CMSDK_CM0.h"
#include <stdlib.h>
#include <string.h>
#include "my_header.h"
#define MTP_BASE_ADDR CMSDK_MTP_BASE //0x10000000
#define MTP_SIZE 0x8000 //32KBytes
#define HW32_REG(ADDRESS) (*((volatile unsigned int *)(ADDRESS)))
#define HW16_REG(ADDRESS) (*((volatile uint16_t *)(ADDRESS)))
#define DATA_SAVE_ADDR (MTP_BASE_ADDR + 0x6F00) //µÚ0x1BC0¿é
typedef struct STRUCT_MTP_TRIM
{
__I uint32_t DEV_ID1:32;
__I uint32_t DEV_ID2:32;
__I uint32_t DEV_ID3:32;
__IO uint8_t OSCA_FT:5;
__IO uint8_t OSC32K_RTRIM:5;
__IO uint8_t BG_TRIM:8;
}STRUCT_MTP_TRIM;
extern uint8_t MTP_init(void);
extern void MTP_TRIM(STRUCT_MTP_TRIM TRIM);
extern void flash_read(uint32_t start_addr,uint16_t *test_i);
extern int8_t flash_buff_write(uint32_t start_addr, uint16_t *buff);
extern int8_t flash_write_ctrl(uint16_t *buff , uint32_t start_addr);
extern int8_t write_data(void);
#endif

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_PWM.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS1_PWM_H
#define ENS1_PWM_H
#include "my_header.h"
#include "ENS1_CLOCK.h"
#define PRESCALE_PWM 1
/*
复用引脚
GPIO16 PWM1
GPIO17 PWM2
GPIO18 PWM3
GPIO19 PWM4
GPIO20 PWM5
GPIO21 PWM6
*/
typedef enum
{
IO16_PWM1 = 1 ,
IO17_PWM2 = 2 ,
IO18_PWM3 = 3 ,
IO19_PWM4 = 4 ,
IO20_PWM5 = 5 ,
IO21_PWM6 = 6
}ENS1_PWM_CHANNEL;
/*
ENS1 PWM 功能特性
1、6个单边沿 和 3个双边沿控制输出 或 1个两种类型的混合
2、脉冲周期和宽度可以是任意定时器计数值
3、双边沿控制PWM输出可以被编程为正极或负极输出
4、匹配寄存器更新与脉冲输出同步以避免产生错误脉冲
5、如不启用PWM功能可作为标准定时器
6、一个有着32位预分频器的32位计时器
*/
/*
PWM使用说明：
1、2个匹配寄存器用于单边沿PWM输出控制，其中PWMMR0控制PWM周期速率，另一个匹配寄存器控制边沿位置（即控制脉宽）
2、3个匹配寄存器可用于双边沿PWM输出控制，其中PWMMR0控制PWM周期速率，另两个匹配控制寄存器控制双边位置
3、使用双边沿PWM的控制可以生成正向和负向脉冲
*/
/*------------------------------------------------函数声明---------------------------------------------*/
/*PWM初始化*/
typedef enum {pwm_single_mode = 0,pwm_double_positive_mode , pwm_double_negtive_mode } PWM_EDGE_MODE;
typedef struct ENS1_PWM_Para
{
PWM_EDGE_MODE mode;
uint32_t pwm_freq;
uint8_t pwm_Duty_cycle ;
}PWM_ParaStructrue;
void PWM_init(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue* PWM_Para , bool pwmEnable) ;
void PWM_SetFreq(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue * PWM_Para );
void PWM_SetDutyCycle_SingleMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle);
void PWM_SetDutyCycle_DoublePositiveMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle);
void PWM_SetDutyCycle_DoubleNegtiveMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle);
void PWM_OutputDisable(ENS1_PWM_CHANNEL PWMx);
void PWM_OutputEnable(ENS1_PWM_CHANNEL PWMx);
#endif

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_SPI.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
1 uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx)
2 uint8_t CLR_TX_FIFO(CMSDK_SPI_TypeDef* SPIx)
3 uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx)
4 uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
5 uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
6 SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx)
7 uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
8 uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
9 uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
10 uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
11 uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx)
12 uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx )
13 uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx )
14 uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET)
15 uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS)
16 uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , struct SPI_ModeConfig_Struct SPI_Config ,struct SPI_FIFO_Struct FIFO_Struct)
17 uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx)
18 uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx)
19 uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx )
20 void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data)
21 uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET)
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS1_SPI_H
#define ENS1_SPI_H
#include "my_header.h"
/*
一、引脚关系：
ALT Function2
SPI1_SCK --- GPIO16
SPI1_MOSI --- GPIO17
SPI1_MISO --- GPIO18
SPI1_NSS0 --- GPIO19
SPI1_NSS1 --- GPIO2
SPI1_NSS2 --- GPIO3
SPI1_NSS3 --- GPIO4
ALT Function2
SPI0_SCK --- GPIO8
SPI0_MOSI --- GPIO9
SPI0_MISO --- GPIO10
SPI0_NSS0 --- GPIO11
SPI0_NSS1 --- GPIO13
SPI0_NSS2 --- GPIO14
SPI0_NSS3 --- GPIO15
二、SPI功能列表说明：
三条线路上的全双工同步传输
双线半双工同步传输
两线单工同步传输（带单向数据线）
16*16bits FIFO 收发缓冲区
4-16位数据大小选择
主模式波特率发生器高达Fpclk/2
从模式波特率发生器高达Fpclk/4
软件或硬件管理 NSS
可编程时钟极性和相位
可编程的数据顺序与MSB或LSB移位
DMA事件支持
中断支持
*/
typedef enum {MASTER = 1 ,SLAVE= 0}MASTER_SLAVE_SEL;
typedef enum {NSS0= 8 ,NSS1 ,NSS2 ,NSS3}NSS_CHANNEL_SEL ;
typedef enum {NOTBUSY = 0, BUSY}SPI_BUSY_STATE ;
typedef enum {EMPTY=0,FULL}FIFO_FULL_EMPTY_STATE;
struct SPI_ModeConfig_Struct
{
uint8_t BAUD_FPCLKdivx ; //波特率分频系数
uint8_t SPI_MODE ; //SPI工作模式
uint8_t SPI_TRANS_MODE; //传输模式选择
MASTER_SLAVE_SEL MS_SEL; //主从模式选择
uint16_t CHAR_LEN ; //设置传输长度 （4 - 16 bit）
NSS_CHANNEL_SEL NSSx ;
uint8_t SAMP_PHASE ;
};
struct SPI_FIFO_Struct //设置FIFO及DMA传输
{
uint8_t TX_FIFO_TH; // 0 - 16 char
uint8_t RX_FIFO_TH; // 0 - 16 char
bool FIFO_ENABLE_SET;
bool TXDMA_SET; //选择是否启动DMA(fifo开启的前提下)
bool RXDMA_SET;
};
/* 中断类型使能结构体
1、发送部分有 下溢 中断（发送数据没有啦）
2、接收部分有 溢出 中断（接满啦）
3、收发完成中断？
4、发送缓冲区空 中断
5、接收缓冲区非空 中断
*/
//中断使能
#define UNDERRUN_INT_EN (uint8_t)0x10
#define OVERRUN_INT_EN (uint8_t)0x8
#define CMPL_INT_EN (uint8_t)0x4
#define TXE_INT_EN (uint8_t)0x2
#define RXNE_INT_EN (uint8_t)0x1
//判断是否检测到对应的中断
#define UNDERRUN_INT (uint8_t)0x10
#define OVERRUN_INT (uint8_t)0x8
#define CMPL_INT (uint8_t)0x4
#define TXE_INT (uint8_t)0x2
#define RXNE_INT (uint8_t)0x1
/*模式： | 接线方式： 主机 从机
全双工 | MISO/MOSI MISO/MOSI
半双工 | MOSI MISO
主机仅发送，从机仅接收模式 | MOSI MOSI
主机仅接收，从机仅发送模式 | MISO MISO
SPI_TRANS_MODE 传输模式选择：
2线单向 / 1线双向
收+发 / 仅发 /仅收/ 单向仅发送 / 仅接收
*/
#define L2_UniDirect_TandR (uint8_t)0x0 //BIT[15:12] 0 0 00
#define L2_UniDirect_T (uint8_t)0x1 //BIT[15:12] 0 0 01
#define L2_UniDirect_R (uint8_t)0x2 //BIT[15:12] 0 0 10
#define L1_BiDirect_T (uint8_t)0x8 //BIT[15:12] 1 0 00
#define L1_BiDirect_R (uint8_t)0xc//BIT[15:12] 1 1 00
/*NSS相关设置*/
#define NSS_PULSE 1 //有nss
#define NO_NSS_PULSE 0 //没有nss
#define NSS_ASSERTED 0 //
#define NSS_DEASSERYED 1 //软件发出nss信号
#define NSS_CTRL_HW 0 //设置为硬件生成NSS
#define NSS_CTRL_SW 1 //设置为软件生成NSS
/*波特率设置*/
#define BAUD_FPCLKdiv2 (uint8_t)0x0
#define BAUD_FPCLKdiv4 (uint8_t)0x1
#define BAUD_FPCLKdiv8 (uint8_t)0x2
#define BAUD_FPCLKdiv16 (uint8_t)0x3
#define BAUD_FPCLKdiv32 (uint8_t)0x4
#define BAUD_FPCLKdiv64 (uint8_t)0x5
#define BAUD_FPCLKdiv128 (uint8_t)0x6
#define BAUD_FPCLKdiv256 (uint8_t)0x7
/*SPI_MODE 工作模式选择*/
#define SPI_MODE0 (uint8_t)0x0 //bit[3:2] 00
#define SPI_MODE1 (uint8_t)0x1 // 01
#define SPI_MODE2 (uint8_t)0x2 // 10
#define SPI_MODE3 (uint8_t)0x3 // 11
/*SAMP_PHASE 选项*/
#define PRE_1_PCLK_PERIOD (uint8_t)0X0
#define SAMP_PHASE_NORMAL (uint8_t)0X1
#define DELAY_1_PCLK_PERIOD (uint8_t)0X2
#define DELAY_2_PCLK_PERIOD (uint8_t)0X3
/*****************************声明 和 定义***************************/
#define SPI0_CS_SET GPIO_SetOutput(GPIO_11)
#define SPI0_CS_RESET GPIO_ResetOutput(GPIO_11)
#define SPI1_CS_SET GPIO_SetOutput(GPIO_19)
#define SPI1_CS_RESET GPIO_ResetOutput(GPIO_19)
//读SPI当前设置的模式
extern uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx);
/*清除FIFO和计数清0*/
extern uint8_t CLR_TX_FIFO(CMSDK_SPI_TypeDef* SPIx);
extern uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx) ;
/*FIFO 状态读取*/
extern uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx); //读取当前接收FIFO数据长度
extern uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx) ; //读取当前发送FIFO数据长度
extern SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx) ; //读取当前SPI是否繁忙
extern uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) ; //当前读取FIFO是否为满？
extern uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) ; //当前读取FIFO是否为空？
extern uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) ;//当前发送FIFO是否为满？
extern uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) ; //当前发送FIFO是否为空？
extern uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx);
extern uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx ); //FIFO功能使能
extern uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx ); //FIFO功能失能
extern uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET); //DMA设置
extern uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS); //nss通道选择
extern uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , struct SPI_ModeConfig_Struct SPI_Config ,struct SPI_FIFO_Struct FIFO_Struct); //spi的初始配置
extern uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx);
extern uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx);
//读被接收的数据 最多16bits
extern uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx );
//写数据
extern void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data);
extern uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET);
#endif

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#ifndef ENS1_TIMER_H
#define ENS1_TIMER_H
#include "CMSDK_CM0.h"
#include "my_header.h"
typedef enum {TOTAL_TIME_MODE = 0 , TRIGGER_TIME_MODE=1}TIME_COUNT_MODE; //选择为总时间或有效运行时间
extern void TIMER0_Init(uint32_t Int_Period);
extern void TIMER1_Init(uint32_t Int_Period);
extern volatile uint32_t CHANNEL_TIME_COUNT[4];
extern volatile uint32_t TRIGGER_TIME_COUNT[4];
extern volatile uint32_t TOTAL_TIME_THRESHOLD_VALUE[4];
extern volatile uint32_t TRIGGER_TIME_THRESHOLD_VALUE[4];
extern volatile uint8_t TRIGGER_TIME_COUNT_FLAG;
extern void CMSDK_timer_EnableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
extern void CMSDK_timer_DisableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
extern void CMSDK_timer_StartTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
extern void CMSDK_timer_StopTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
extern uint32_t CMSDK_timer_GetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
extern void CMSDK_timer_SetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value);
extern uint32_t CMSDK_timer_GetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
extern void CMSDK_timer_SetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value);
extern void CMSDK_timer_ClearIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
extern uint32_t CMSDK_timer_StatusIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER);
extern void CMSDK_timer_Init(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload, uint8_t irq_en);
extern void CMSDK_timer_Init_ExtClock(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,uint32_t irq_en);
extern void CMSDK_timer_Init_ExtEnable(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,uint32_t irq_en);
extern void CMSDK_dualtimer_start(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx);
extern void CMSDK_dualtimer_stop(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx);
extern void CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx);
extern void CMSDK_dualtimer_setup_freerunning(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx,
unsigned int cycle, unsigned int prescale,
unsigned int interrupt, unsigned int size);
extern void CMSDK_dualtimer_setup_periodic(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx,
unsigned int cycle, unsigned int prescale,
unsigned int interrupt, unsigned int size);
extern void CMSDK_dualtimer_setup_oneshot(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx,
unsigned int cycle, unsigned int prescale,
unsigned int interrupt, unsigned int size);
extern void CMSDK_RTC_Init_Calender(uint16_t prescaler, uint8_t data_mode, uint8_t hour_mode, uint32_t init_time, uint32_t init_date);
extern void CMSDK_RTC_Config_Alarm(uint16_t prescaler, uint8_t data_mode, uint8_t hour_mode, uint32_t init_time, uint32_t init_date, uint32_t alarm_time, uint32_t alarm_date) ;
extern void CMSDK_RTC_Config_PeriodWake(uint8_t clock_sel, uint16_t prescaler, uint16_t period_time);
#endif

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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_UART.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
1 void UART_Init(CMSDK_UART_TypeDef *CMSDK_UART, UART_InitStructure* uart_paraX);
2 void UART_ITConfig(CMSDK_UART_TypeDef *CMSDK_UART, UART_ITStructure* uart_paraX);
3 unsigned char UartPutc(CMSDK_UART_TypeDef *CMSDK_UART ,unsigned char my_ch);
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef _ENS1_UART_H_
#define _ENS1_UART_H_
#include "MY_HEADER.h"
#include "CMSDK_CM0.h"
#include "ENS1_CLOCK.h"
#include "math.h"
#define UART0_RX GPIO_2
#define UART0_TX GPIO_3
#define UART0_RTS GPIO_4
#define UART0_CTS GPIO_5
#define UART1_RX GPIO_12
#define UART1_TX GPIO_13
#define UART1_RTS GPIO_14
#define UART1_CTS GPIO_15
#define InterruptDisable __disable_irq
#define InterruptEnable __enable_irq
typedef enum uartRcvfifoTrigger{byte_1=0 , bytes_4=1,bytes_8=2,bytes_14=3}uartRcvTrigger;
typedef enum {OverSamp_16 = 0,OverSamp_13}UART_OverSamp;
/*uart参数设置结构体*/
typedef struct uart_fifo{
uartRcvTrigger level;
uint8_t DMA_Enable ;
uint8_t FIFO_Enable ;
}UART_FifoStructrue;
typedef struct uart_para{
uint8_t UART_OverSampMode;
uint32_t UART_BaudRate;
uint8_t UART_HardwareFlowControl; //硬件流控是否开启
UART_FifoStructrue* FifoSetting ;
}UART_InitStructure;
extern UART_FifoStructrue UART0_Fifo;
extern UART_InitStructure UART0_Init;
extern UART_FifoStructrue UART1_Fifo;
extern UART_InitStructure UART1_Init;
/*
中断资源说明：
1、THREINT THR发送寄存器或发送FIFO空
2、RDAINT 接收寄存器数据可用 ，FIFO模式下触发接收阈值
3、RTOINT FIFO模式下接收超时：在最后四个字节时间内没有字节移除或者输入，在这个时间内至少有一个字节在接收FIFO中
4、RLSINT 接收线路状态：发生了溢出错误，校验错误，帧错误或者中断
5、MSIINT 调制解调器状态：CTS更改状态（禁用autoflow），DSR/RI/DCD更改状态
*/
/*中断使能*/
#define MSI_EN (uint8_t)0X8
#define RLSI_EN (uint8_t)0X4
#define THRE_EN (uint8_t)0X2
#define RDAI_EN (uint8_t)0X1
/*中断信息*/
#define INT_MODEM_STATUS (uint8_t)0X0
#define INT_THR_EMPTY (uint8_t)0X1
#define INT_RCV_DATA_AVAILABLE (uint8_t)0X2
#define INT_RCV_LINE_STATUS (uint8_t)0X3
#define INT_CHAR_TIMEOUT_INDICATION (uint8_t)0X6
typedef struct uart_it_para{
uint8_t UartIntModel ; //选择中断的模式
uint8_t UartDMAEnable; //选择是否开启DMA
}UART_ITStructure;
extern UART_ITStructure UART0_ITSet;
extern UART_ITStructure UART1_ITSet;
#define UART_WordLength_5b ((uint8_t)0x00)
#define UART_WordLength_6b ((uint8_t)0x01)
#define UART_WordLength_7b ((uint8_t)0x02)
#define UART_WordLength_8b ((uint8_t)0x03)
#define UART_NO_PARITY ((uint8_t)0x00 & 0xff)
#define UART_LOGIC_1_ODD_NUM ((uint8_t)0x08 & 0xff) //逻辑1奇数个
#define UART_LOGIC_1_EVEN_NUM ((uint8_t)0x18 & 0xff) //逻辑1偶数个
#define UART_STICK_PARITY_AS1 ((uint8_t)0x28 & 0xff) //固定奇偶校验为1
#define UART_STICK_PARITY_AS0 ((uint8_t)0x38 & 0xff)
/*中断信息读取*/
/*中断挂起*/
uint8_t UART_INT_PEND(CMSDK_UART_TypeDef* UARTx); //为0时有UART的中断挂起
/*中断状态判断*/
uint8_t UART_INT_TYPE(CMSDK_UART_TypeDef* UARTx);
/*fifo 使用指示器*/
uint8_t UART_FIFO_USE(CMSDK_UART_TypeDef* UARTx); //0:非fifo模式 1：fifo 使能
/*清除传输FIFO*/
void UART_TXCLR(CMSDK_UART_TypeDef* UARTx);
/*清除接收FIFO*/
void UART_RXCLR(CMSDK_UART_TypeDef* UARTx);
/*FIFO使能*/
void UART_FIFOEnable(CMSDK_UART_TypeDef* UARTx);
/*FIFO关闭*/
void UART_FIFODisable(CMSDK_UART_TypeDef* UARTx);
/*接收数据*/
uint8_t READ_UART_RCVBuff(CMSDK_UART_TypeDef* UARTx );
/*发送数据*/
void WRITE_UART_THRBuff(CMSDK_UART_TypeDef* UARTx ,uint8_t data);
/*FIFO状态获取*/
uint8_t UART_RX_FIFO_LEN(CMSDK_UART_TypeDef* UARTx) ;
uint8_t UART_TX_FIFO_LEN(CMSDK_UART_TypeDef* UARTx) ;
uint8_t UART_RX_FIFO_FULL(CMSDK_UART_TypeDef* UARTx) ;
uint8_t UART_RX_FIFO_EMPTY(CMSDK_UART_TypeDef* UARTx) ;
uint8_t UART_TX_FIFO_FULL(CMSDK_UART_TypeDef* UARTx) ;
uint8_t UART_TX_FIFO_EMPTY(CMSDK_UART_TypeDef* UARTx) ;
/*收发线状态获取*/
uint8_t UARTLine_RCVError(CMSDK_UART_TypeDef* UARTx);
/*判断发送缓存是否为空*/
uint8_t UARTLine_TRANSEmpty(CMSDK_UART_TypeDef* UARTx);
/*判断THR是否为空*/
uint8_t UARTLine_THREmpty(CMSDK_UART_TypeDef* UARTx);
/*UART初始化*/
void UART_Init(CMSDK_UART_TypeDef *CMSDK_UART, UART_InitStructure* uart_paraX);
void UART_ITConfig(CMSDK_UART_TypeDef *CMSDK_UART, UART_ITStructure* uart_paraX);
unsigned char UartPutc(CMSDK_UART_TypeDef *CMSDK_UART ,unsigned char my_ch);
#endif

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_WATCHDOG.h
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS1_WATCHDOG_H
#define ENS1_WATCHDOG_H
#include "CMSDK_CM0.h"
#include "ENS1_CLOCK.h"
#include "my_header.h"
/*
1、watchdog寄存器有写锁，在写入watchdog的寄存器前需要对 WDOGLOCK 寄存器写入 0x1ACCE551
2、watchdog的技术加载值： WDOGLOAD = interval(us) * pclk(MHZ)
3、计数重加载位置： WDOGVALUE
4、写1到 WDOGCONTROL 的 INTEN 位 ，使能看门狗和预警中断，当WDT计数到0，则触发一次中断
中断状态被知识通过设置 WDOGMIS位，如果 WDOGINTCLR 寄存器写入任意值（比如按照惯例，写1）
此时WDOGMIS 位被清0 ，如果RESEN位是 0 ，watchdog定时器将重载。
5、以上步骤设置完成后，写一个任意数据（除了0x1ACCE551）到WDOGLOCK寄存器
6、如果WDT当前计数值没有重载， 计数到达0时 WDT 将触发一个早期预警中断
因此，在中断触发前需要重载 WDOGLOAD寄存器
*/
typedef enum{UNLOCK = 0,LOCK=1}WdogLockState;
extern void WatchDogLoad(uint32_t loadvalue_us);
extern uint32_t Read_WDOGVALUE(void);
extern void WatchDog_Control(FunctionalState newstate);
extern void WatchDog_IntClear(void);
extern uint8_t WatchDog_LOCK_RegSet(WdogLockState newstate);
#endif

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_CURRENT_CALIBRATION.H
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#ifndef ENS_CURRENT_CALIBRATION_H
#define ENS_CURRENT_CALIBRATION_H
#include "my_header.h"
#include "ENS1_TIMER.h"
#define PI 3.1415
extern volatile uint8_t statics_config; //通道状态标志，[3:0] 每一位对应一个通道的状态 0：关闭中 1：开启状态
extern uint8_t unit_current[4];
extern volatile uint32_t NUM_OF_PULSES_THRESHOLD[4];
extern volatile uint32_t wave_gen_irq_occurred[4];
/* --------------------------电刺激有关的参数以及通道状态--------------------------- */
/*
1、基本参数：
·基础波形类型
·正向脉宽：
·负向脉宽：
·波形频率：
·电流大小：
·延迟输出时间
2、复杂波形参数
·中断点设置（每次可以设置两个点，且第1点需要小于第2点）
·交替波形频率：
·总输出时间设置
·脉冲群中的脉冲个数
·脉冲群与脉冲群的间隔发生时间
*/
typedef enum {SQUARE_WAVE = 0 ,SINE_WAVE = 1, TRIANGULAR_WAVE = 2 }BasicWaveformType;
typedef struct COMPLEX_WAVEFORM_PARA
{
uint16_t AlternatingFreq_HZ;
uint32_t TotalOutputTime_S;
uint32_t NumOfPulseGroups;
uint32_t TimeOfPulseGroups_MS;
}STRUCT_COMPLEX_WAVEFORM_PARA;
typedef struct WAVEFORM_PARA
{
BasicWaveformType Type;
uint32_t PositivePulseWidth;
uint32_t NegativePulseWidth;
//uint32_t WaveformFreq;
uint32_t ClientTime;
uint8_t DeadTime;
uint32_t DelayOutputTime_US;
STRUCT_COMPLEX_WAVEFORM_PARA OtherWaveformPara;
}STRUCT_WAVEFORM_PARA;
extern STRUCT_WAVEFORM_PARA ParaSet_waveform[4];
/* ------------------------------------------------------------------------- */
/*--------------------------------波形设置的函数-----------------------------*/
typedef enum ENS_DRV_CONFIG
{
DISABLE_ALL_BIT = -1,
REST_BIT = 1,
NEGATIVE_BIT =2,
SILENT_BIT =4,
SOURCE_B_BIT = 8,
ALTERNATING_POSITIVE_BIT =16,
CONTINUE_REPEATING_BIT = 32,
MULTI_ELECTRODE_BIT = 64 ,
ENABLE_ALL_BIT = 0X7F
}DRV_CONFIG;
/*获取到FT测试后的实际测量单元电流值 */
extern uint8_t GET_FT_CURRENT(void);
/*波形参数的设置*/
extern uint32_t StimulatorInit(CHANNEL_NUM CHANNEL_X);
/*输出电流 / 频率*/
extern uint8_t CURRENT_AMPLITUDE_MODIFY(CHANNEL_NUM CHANNEL_X , float mA);
extern uint32_t CURRENT_FREQ_MODIFY(CHANNEL_NUM CHANNEL_X , uint32_t freq);
/*电刺激时间*/
extern uint32_t StimuTimeCount_S(CHANNEL_NUM CHANNEL_X , TIME_COUNT_MODE MODE);
/*启动停止*/
void StartStimulatorOut(CHANNEL_NUM CHANNEL_X);
void StopStimulatorOut(CHANNEL_NUM CHANNEL_X);
#endif

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_ANAC.c
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ens1_anac.h"
#include "ENS1_CLOCK.h"
#include "ENS1_ADC.h"
/*----------------------------------------------------COMP----------------------------------------------------------------*/
/*比较器的输出设置*/
void CompInitSet(COMP_ConfigStructure* COMPCONFIG)
{
if(COMPCONFIG->COMPARATOR_NUM == COMP0)
{
//IO复用
GPIO_AltFunction(GPIO_8 , ALT_FUNC3);
GPIO_AltFunction(GPIO_9 , ALT_FUNC3);
GPIO_AltFunction(GPIO_10 , ALT_FUNC3);
GPIO_AltFunction(GPIO_11 , ALT_FUNC3);
GPIO_AltFunction(GPIO_20 , ALT_FUNC2);
CMSDK_ANAC->COMP0_CTRL |= ( COMPCONFIG->COMP_VREF_SEL << 4 );
CMSDK_ANAC->COMP0_CTRL |= ( COMPCONFIG->COMP_SIGSEL_NEGATIVE_INPUT_SEL << 2 );
CMSDK_ANAC->COMP0_CTRL |= ( COMPCONFIG->COMP_SIGSEL_POSITIVE_INPUT_SEL << 1 );
}
else if(COMPCONFIG->COMPARATOR_NUM == COMP1)
{
GPIO_AltFunction(GPIO_12 , ALT_FUNC3);
GPIO_AltFunction(GPIO_13 , ALT_FUNC3);
GPIO_AltFunction(GPIO_14 , ALT_FUNC3);
GPIO_AltFunction(GPIO_15 , ALT_FUNC3);
GPIO_AltFunction(GPIO_21 , ALT_FUNC2);
CMSDK_ANAC->COMP1_CTRL |= ( COMPCONFIG->COMP_VREF_SEL << 4 );
CMSDK_ANAC->COMP1_CTRL |= ( COMPCONFIG->COMP_SIGSEL_NEGATIVE_INPUT_SEL << 2 );
CMSDK_ANAC->COMP1_CTRL |= ( COMPCONFIG->COMP_SIGSEL_POSITIVE_INPUT_SEL << 1 );
}
else
return ;
}
uint8_t Read_Comp_Output(COMP_NUM NUM)
{
if(NUM == COMP0)
return (uint8_t)((CMSDK_ANAC->COMP0_CTRL >> 8)&0X1);
else
return (uint8_t)((CMSDK_ANAC->COMP1_CTRL >> 8)&0X1);
}
void CompControl(COMP_NUM NUM ,FunctionalState Newstate)
{
if(NUM == COMP0)
(Newstate == ENABLE)? (CMSDK_ANAC->COMP0_CTRL |= (1) ): ( CMSDK_ANAC->COMP0_CTRL &=~ (1));
else
(Newstate == ENABLE)? (CMSDK_ANAC->COMP1_CTRL |= (1) ): ( CMSDK_ANAC->COMP1_CTRL &=~ (1));
}
/*--------------------------------------------------------PGA---------------------------------------------------------------*/
//初始化
void PGAInitSet(PGA_ConfigStructure* PGACONFIG)
{
if(PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN0) //PGA0
{
GPIO_AltFunction(GPIO_16 , ALT_FUNC3);
GPIO_AltFunction(GPIO_18 , ALT_FUNC3);
GPIO_AnalogChannel_Control(GPIO_16 ,ENABLE );
GPIO_AnalogChannel_Control(GPIO_18 ,ENABLE );
}
else if(PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN1) //PGA1
{
GPIO_AltFunction(GPIO_17 , ALT_FUNC3);
GPIO_AltFunction(GPIO_19 , ALT_FUNC3);
GPIO_AnalogChannel_Control(GPIO_17 ,ENABLE );
GPIO_AnalogChannel_Control(GPIO_19 ,ENABLE );
}
else if((PGACONFIG->PGA_NEG_SELx ==PGA_NEGATIVE_INPUT_INTERNAL_VCM) && ((PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_PGA_VIP0 )||(PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_PGA_VIP1))) //内部参考电压+0/1
{
GPIO_AltFunction((GPIO_NUM)(GPIO_16+PGACONFIG->PGA_POS_SELx), ALT_FUNC3);
GPIO_AnalogChannel_Control((GPIO_NUM)(GPIO_16+PGACONFIG->PGA_POS_SELx) ,ENABLE );
}
else if((PGACONFIG->PGA_NEG_SELx ==PGA_NEGATIVE_INPUT_EXTERNAL_VCM) && ((PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_PGA_VIP0 )||(PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_PGA_VIP1))) //内部参考电压+0/1
{
GPIO_AltFunction((GPIO_NUM)(GPIO_16+PGACONFIG->PGA_POS_SELx), ALT_FUNC3);
GPIO_AltFunction(GPIO_20, ALT_FUNC3);
GPIO_AnalogChannel_Control((GPIO_NUM)(GPIO_16+PGACONFIG->PGA_POS_SELx) ,ENABLE );
GPIO_AnalogChannel_Control(GPIO_20 ,ENABLE );
}
else if((PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_INTERNAL_VCM) && ((PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN0)||(PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN1)))
{
GPIO_AltFunction((GPIO_NUM)(GPIO_18+PGACONFIG->PGA_POS_SELx), ALT_FUNC3);
GPIO_AnalogChannel_Control((GPIO_NUM)(GPIO_18+PGACONFIG->PGA_POS_SELx) ,ENABLE );
}
else if((PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_VREF1_2V) && ((PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN0)||(PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN1)))
{
GPIO_AltFunction((GPIO_NUM)(GPIO_18+PGACONFIG->PGA_POS_SELx), ALT_FUNC3);
GPIO_AnalogChannel_Control((GPIO_NUM)(GPIO_18+PGACONFIG->PGA_POS_SELx) ,ENABLE );
}
else
{
return ;
}
if(PGACONFIG->PGA_OUT == PGA_TO_GPIO4)
{
CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
CMSDK_ADC->ADC_CH_SEL = 4;
GPIO_AltFunction(GPIO_4, ALT_FUNC3);
GPIO_AnalogChannel_Control(GPIO_4 ,ENABLE );
ENS1_ADC_STOP(ENS1_PGA_TO_ADC);
}
else if(PGACONFIG->PGA_OUT == PGA_TO_ADC)
{
ENS1_ADCCLKConfig(ADC_CLK_base32div);
CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
CMSDK_ADC->ADC_CH_SEL = 0;
ENS1_ADC_CONFIG(ENS1_PGA_TO_ADC ,
CONTINUOUS_ADC_MODE,
COV_RCV_EOC ,
ADC_SampleTime_5ADC_Clk,
ENABLE_EOC_INT);
ENS1_ADC_START(ENS1_PGA_TO_ADC);
}
else
{
return ;
}
CMSDK_ANAC->PGA_CTRL |= ( PGACONFIG->PGA_GAIN_SEL << 4 );
}
//PGA开关控制
void PGAControl(FunctionalState Newstate)
{
(Newstate == ENABLE) ? (CMSDK_ANAC->PGA_CTRL |= (0X3) ) : (CMSDK_ANAC->PGA_CTRL &=~ (0X3)) ;
}
/*----------------------------低电压与芯片过温检测--------------------------*/
void PMU_TEMP150C_TRIGControl(FunctionalState Newstate) //过温检测功能开启与关闭
{
(Newstate==ENABLE) ? (CMSDK_ANAC->PMU_CTRL |= (1<<5) ) : (CMSDK_ANAC->PMU_CTRL &=~ (1<<5));
}
//返回温度是否超过150度的状态值
int8_t TEMP_150C_TRIG_SIGNAL(void)
{
if((CMSDK_ANAC->PMU_CTRL >> 5) & 0x1)
return ((CMSDK_ANAC->PMU_CTRL >> 7) & 0x1);
else
{
PMU_TEMP150C_TRIGControl(ENABLE);
return ((CMSDK_ANAC->PMU_CTRL >> 7) & 0x1);
}
}
//低电压告警
//设置阈值电压
void LVD_InitSet(uint8_t Threshold_voltage)
{
CMSDK_ANAC->PMU_CTRL |= (Threshold_voltage << 1);
}
//打开或关闭此功能
void PMU_LVD_Control(FunctionalState Newstate)
{
(Newstate == ENABLE) ? (CMSDK_ANAC->PMU_CTRL|= (1) ) : (CMSDK_ANAC->PMU_CTRL &=~ (1)) ;
}
//读取低电压状态
uint8_t Read_LVD_Signal(void)
{
return ((CMSDK_ANAC->PMU_CTRL >> 6) & 0x1);
}
/*------------------------带隙BUFFER启用或关闭-----------------------------------*/
void PMU_BANDGAP_CONTROL(FunctionalState Newstate)
{
(Newstate == ENABLE) ? (CMSDK_ANAC->PMU_CTRL |= (1<<4)) : (CMSDK_ANAC->PMU_CTRL &=~ (1<<4)) ;
}

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#include "ENS1_BOOST.h"
#include "ENS1_CLOCK.h"
/*--------------------ÄÚ˛żBOOST_SET-----------------------*/
uint8_t Boost_Voltage_Sel(uint8_t VOLTAGE_XV)
{
PCLK_Enable(ANALOG_PCLK_EN);
switch (VOLTAGE_XV){
case VOLTAGE_11V :
CMSDK_ANAC->BOOST_CTRL =0x71013;//ÄÚ˛żboost
CMSDK_ANAC->PMU_CTRL = 0x10;
break;
case VOLTAGE_15V :
CMSDK_ANAC->BOOST_CTRL =0x71113;//ÄÚ˛żboost
CMSDK_ANAC->PMU_CTRL = 0x10;
break;
case VOLTAGE_26V :
CMSDK_ANAC->BOOST_CTRL =0x71213;//ÄÚ˛żboost
CMSDK_ANAC->PMU_CTRL = 0x10;
break;
case VOLTAGE_45V :
CMSDK_ANAC->BOOST_CTRL =0xc1413;//
CMSDK_ANAC->PMU_CTRL = 0x10;
break;
case VOLTAGE_55V :
CMSDK_ANAC->BOOST_CTRL =0xc1713;//ÄÚ˛żboost
CMSDK_ANAC->PMU_CTRL = 0x10;
break;
default:
CMSDK_ANAC->BOOST_CTRL =0x71013;//ÄÚ˛żboost
CMSDK_ANAC->PMU_CTRL = 0x10;
break;
}
return 0;
}

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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_CLOCK.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ENS1_CLOCK.h"
uint32_t APB_Clock_Freq =0;
//设置后的时钟频率请查看时钟树计算
Clock_ConfigStructure CLOCKCFG=
{
.MCO_SEL = MCO_HSI ,
.HSI_FREQ = HSI_32MHZ ,
.HSE_OSC_FREQ = 0,
.LSE_OSC_FREQ = 0,
.SYSCLK_SEL = HSI_SYSCLK ,
.ENS1_APB_PCLK_DIV_x = ENS1_APB_PCLK_DIV_1,
.ENS1_AHB_PCLK_DIV_x = ENS1_AHB_HCLK_DIV_1,
.LFCLK_SW_SEL = LSI_AS_LFCLK ,
};
uint32_t ClockInitSet(Clock_ConfigStructure* CLOCKCONFIG)
{
uint32_t clockfreq = 0;
//配置系统各时钟初始化
//1 确定输入频率
CMSDK_SYSCON->CLK_CFG |= (CLOCKCONFIG->MCO_SEL<<16);
if(CLOCKCONFIG->MCO_SEL == MCO_HSI)
{
CMSDK_SYSCON->HSI_CTRL |= (CLOCKCONFIG->HSI_FREQ << 4);
clockfreq = (uint8_t)pow(2,CLOCKCONFIG->HSI_FREQ+2)*1000000;
}
else if(CLOCKCONFIG->MCO_SEL == MCO_HSE)
{
clockfreq = CLOCKCONFIG->HSE_OSC_FREQ * 1000000;
}
else if(CLOCKCONFIG->MCO_SEL == MCO_LSI)
{
clockfreq = 32768 ;
}
else if(CLOCKCONFIG->MCO_SEL == MCO_LSE)
{
clockfreq = CLOCKCONFIG->LSE_OSC_FREQ ;
}
else
{
CMSDK_SYSCON->HSI_CTRL |= (CLOCKCONFIG->HSI_FREQ << 4);
clockfreq = (uint8_t)pow(2,CLOCKCONFIG->HSI_FREQ+2);
}
//2 选择系统的时钟源
CMSDK_SYSCON->CLK_CFG |= (CLOCKCONFIG->SYSCLK_SEL);
while((CMSDK_SYSCON->CLK_CFG >> 2 ) & 0x1);
//3 基于系统时钟源的频率设置分频系数
CMSDK_SYSCON->CLK_CFG |= (CLOCKCONFIG->ENS1_AHB_PCLK_DIV_x << 8);
CMSDK_SYSCON->CLK_CFG |= (CLOCKCONFIG->ENS1_APB_PCLK_DIV_x << 12);
if(CLOCKCONFIG->ENS1_AHB_PCLK_DIV_x > 0)
clockfreq = (uint32_t)(clockfreq / pow(2,CLOCKCONFIG->ENS1_AHB_PCLK_DIV_x-3));
if(CLOCKCONFIG->ENS1_APB_PCLK_DIV_x > 0)
clockfreq = (uint32_t)(clockfreq / pow(2,CLOCKCONFIG->ENS1_APB_PCLK_DIV_x-3));
return clockfreq; //返回时钟频率（分频后的APB上的时钟频率）
}
void ClockInit(void)
{
APB_Clock_Freq = ClockInitSet(&CLOCKCFG);
CMSDK_SYSCON->APB_CLKEN = 0;
}
//PCLK时钟使能
uint8_t PCLK_Enable(uint8_t APB_CLKEN_POS)
{
CMSDK_SYSCON->APB_CLKEN |= (0x1 << APB_CLKEN_POS);
return 0;
}
//PCLK时钟关闭
uint8_t PCLK_Disable(uint8_t APB_CLKEN_POS)
{
CMSDK_SYSCON->APB_CLKEN &=~ (0x1 << APB_CLKEN_POS);
return 0;
}
//配置外部晶振，配置前请保留足够延时，否则无法二次烧录程序
void HSE_ClockInit(uint32_t Clock_Freq)
{
CMSDK_GPIO->IE = (CMSDK_GPIO->IE & ~(0x01ul << 0)) | (0x01 << 0);
CMSDK_GPIO->ALTFL = (CMSDK_GPIO->ALTFL & ~(0x03ul << 0)) | (0x02 << 0);
CMSDK_SYSCON->CLK_CFG = (CMSDK_SYSCON->CLK_CFG & ~CMSDK_SYSCON_SYSCLK_SEL_Msk) | (0x1 << CMSDK_SYSCON_SYSCLK_SEL_Pos);
while (((CMSDK_SYSCON->CLK_CFG & CMSDK_SYSCON_SYSCLK_SWSTS_Msk) >> CMSDK_SYSCON_SYSCLK_SWSTS_Pos) != 0x01) { }
CMSDK_SYSCON->HSI_CTRL = (CMSDK_SYSCON->HSI_CTRL & ~CMSDK_SYSCON_HSI_EN_Msk);
APB_Clock_Freq = Clock_Freq;//外部时钟频率
}

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_EXTI.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ENS1_EXTI.h"
/*每一位在相应的线路上使能/失能事件或中断的上升沿触发 0-29*/
void EXTI_RisingTriggerSelect(EXTI_NUM NUM , FunctionalState newstate)
{
if(newstate == ENABLE)
CMSDK_EXTI->RTSR |= (1<<NUM);
else
CMSDK_EXTI->RTSR &=~ (1<<NUM);
}
/*每一位在相应的线路上使能/失能事件或中断的下降沿触发 0-29*/
void EXTI_FallingTriggerSelect(EXTI_NUM NUM , FunctionalState newstate)
{
if(newstate == ENABLE)
CMSDK_EXTI->FTSR |= (1<<NUM);
else
CMSDK_EXTI->FTSR &=~ (1<<NUM);
}
/*软件中断设置：通过软件设置某一位的上升沿发生从而导致上升沿中断（软件中断）发生，仅仅可写 0-29*/
void EXTI_SoftwareInterruptEventSet(EXTI_NUM NUM)
{
CMSDK_EXTI->SWIER |= (1<<NUM);
}
/*读取上升沿触发请求数据（用于判断上升沿事件发生）*/
bool Read_EXTI_RisingEdgePending(EXTI_NUM NUM)
{
return (bool)((CMSDK_EXTI->RISE_PEND_STS >> NUM ) & 0x1);
}
//清除上升沿触发状态
void Clear_EXTI_RisingEdgePending(EXTI_NUM NUM)
{
CMSDK_EXTI->RISE_PEND_CLR |= (1<<NUM);
}
/*读取下降沿触发请求数据（用于判断下降沿事件发生）*/
bool Read_EXTI_FallingEdgePending(EXTI_NUM NUM)
{
return (bool)((CMSDK_EXTI->FALL_PEND_STS >> NUM) & 0x1);
}
//清除下降沿触发状态
void Clear_EXTI_FallingEdgePending(EXTI_NUM NUM)
{
CMSDK_EXTI->FALL_PEND_CLR |= (1<<NUM);
}
/*清除/屏蔽 唤醒CPU的中断线（0：用被屏蔽的中断唤醒 1：用未被屏蔽的中断唤醒）0-31*/
void EXTI_INT_MASK(uint8_t NUM)
{
if(NUM >31)
return ;
CMSDK_EXTI->IMR |= (1<<NUM);
}
/*设置/清除 事件生成唤醒CPU 0-31 */
void EXTI_EVENT_MASK(uint8_t NUM)
{
if(NUM >31)
return ;
CMSDK_EXTI->EMR |= (1<<NUM);
}

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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_GPIO.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "my_header.h"
#include "ENS1_GPIO.h"
//IO复用
uint8_t GPIO_AltFunction(GPIO_NUM GPIO_X , GPIO_AltFuncSel GPIO_AltFuncSelx){
if(GPIO_X >15)
{
CMSDK_GPIO->ALTFH &=~ (0x3 << ((GPIO_X-16)*2));
CMSDK_GPIO->ALTFH |= (GPIO_AltFuncSelx << ((GPIO_X-16)*2));
}
else
{
CMSDK_GPIO->ALTFL &=~ (0x3 << (GPIO_X*2) );
CMSDK_GPIO->ALTFL |= (GPIO_AltFuncSelx << (GPIO_X*2));
}
return 0;
}
int8_t GPIO_IO_Init(GPIO_NUM GPIO_X, I_O_SELECT INorOUT ,GPIOOType_TypeDef GPIO_OType,GPIO_PUPD_TypeDef GPIO_PUPD,OUTPUT_SPEED_TypeDef OUTPUT_SPEED,OUTPUT_PDRV_TypeDef OUTPUT_PDRV,FunctionalState ENABLEorNOT){
//??GPIO??????
GPIO_AltFunction(GPIO_X,ALT_FUNC0);
//????????
if(INorOUT == INPUT && ENABLEorNOT ==ENABLE)
{
CMSDK_GPIO->OE &=~ (1<<GPIO_X);
CMSDK_GPIO->IE |= (1<<GPIO_X);
}
else if(INorOUT == INPUT && ENABLEorNOT ==DISABLE)
{
CMSDK_GPIO->OE &=~ (1<<GPIO_X);
CMSDK_GPIO->IE &=~ (1<<GPIO_X);
}
else if(INorOUT == OUTPUT && ENABLEorNOT ==ENABLE)
{
CMSDK_GPIO->IE &=~ (1<<GPIO_X);
CMSDK_GPIO->OE |= (1<<GPIO_X);
//??????,??
CMSDK_GPIO->SL = OUTPUT_SPEED;
//?????????
CMSDK_GPIO->ODEN = GPIO_OType;
}
else if(INorOUT == OUTPUT && ENABLEorNOT == DISABLE)
{
CMSDK_GPIO->OE &=~ (1<<GPIO_X);
CMSDK_GPIO->IE &=~ (1<<GPIO_X);
}
//???????
if(GPIO_PUPD==GPIO_NOPULL)
{
CMSDK_GPIO->PU &= ~(0x01 << GPIO_X); //????
CMSDK_GPIO->PD &= ~(0x01 << GPIO_X); //????
}
else if(GPIO_PUPD==GPIO_PU)
{
CMSDK_GPIO->PU |= (0x01 << GPIO_X); //??
CMSDK_GPIO->PD &= ~(0x01 << GPIO_X); //????
}
else if(GPIO_PUPD==GPIO_PD)
{
CMSDK_GPIO->PU &= ~(0x01 << GPIO_X); //????
CMSDK_GPIO->PD |= (0x01 << GPIO_X); //??
}
//??????
CMSDK_GPIO->OPDRV0 &=~( 0x01 << (GPIO_X));
CMSDK_GPIO->OPDRV0 |= (OUTPUT_PDRV & 0x01) << (GPIO_X);
CMSDK_GPIO->OPDRV1 &=~( 0x01 << (GPIO_X));
CMSDK_GPIO->OPDRV1 |= ((OUTPUT_PDRV >>1)&0x01) << (GPIO_X);
//
return 0;
}
//IO口输入输出设置,形参1：gpio号，形参2：输入输出选择 ，形参3：使能与否
int8_t GPIO_IO_Select(GPIO_NUM GPIO_X, I_O_SELECT INorOUT ,FunctionalState ENABLEorNOT){
if(INorOUT == INPUT && ENABLEorNOT ==ENABLE)
{
CMSDK_GPIO->OE &=~ (1<<GPIO_X);
CMSDK_GPIO->IE |= (1<<GPIO_X);
}
else if(INorOUT == INPUT && ENABLEorNOT ==DISABLE)
{
CMSDK_GPIO->OE &=~ (1<<GPIO_X);
CMSDK_GPIO->IE &=~ (1<<GPIO_X);
}
else if(INorOUT == OUTPUT && ENABLEorNOT ==ENABLE)
{
CMSDK_GPIO->IE &=~ (1<<GPIO_X);
CMSDK_GPIO->OE |= (1<<GPIO_X);
}
else if(INorOUT == OUTPUT && ENABLEorNOT == DISABLE)
{
CMSDK_GPIO->OE &=~ (1<<GPIO_X);
CMSDK_GPIO->IE &=~ (1<<GPIO_X);
}
else
return -1;
return 0;
}
//读取IO口输入状态
uint8_t GPIO_GetInputValue(GPIO_NUM GPIO_X){
return (uint8_t)((CMSDK_GPIO->DATAIN & (1<<GPIO_X))>>GPIO_X);
}
//读取IO口输出状态
uint8_t GPIO_GetOutputValue(GPIO_NUM GPIO_X){
return (uint8_t)((CMSDK_GPIO->DATAOUT & (1<<GPIO_X))>>GPIO_X);
}
//设置输出电平为高或低
void GPIO_Output(GPIO_NUM GPIO_X,LEVELStatus HIGHorLOW){
if(HIGHorLOW == HIGH_LEVEL)
{
CMSDK_GPIO->DATAOUT |= (1<<GPIO_X);
}
else
{
CMSDK_GPIO->DATAOUT &=~ (1<<GPIO_X);
}
}
//设置输出电平为高
void GPIO_SetOutput(GPIO_NUM GPIO_X){
CMSDK_GPIO->DATAOUT |= (1<<GPIO_X);
}
//设置输出电平为低
void GPIO_ResetOutput(GPIO_NUM GPIO_X){
CMSDK_GPIO->DATAOUT &=~ (1<<GPIO_X);
}
//IO反转
void GPIO_Overturn(GPIO_NUM GPIO_X){
if(GPIO_GetOutputValue(GPIO_X) == HIGH_LEVEL)
{
GPIO_ResetOutput(GPIO_X);
}
else if(GPIO_GetOutputValue(GPIO_X) == LOW_LEVEL)
{
GPIO_SetOutput(GPIO_X);
}
}
//模拟功能使能失能
void GPIO_AnalogChannel_Control(GPIO_NUM GPIO_X ,FunctionalState ENABLEorNOT )
{
if(ENABLEorNOT == ENABLE)
CMSDK_GPIO->ANAEN |= (1 << GPIO_X);
else if(ENABLEorNOT == DISABLE)
CMSDK_GPIO->ANAEN &=~ (1 << GPIO_X);
else
return ;
}

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_I2C.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ENS1_IIC.h"
IIC_ConfigStructure IIC0_Config =
{
.MODE = IIC_SLAVE ,
.OWN_ADDRESS = 0x78 ,
.ACK_EN = true ,
.IIC_SPEED = IIC_STARDARD_MODE_10K ,
};
IIC_ConfigStructure IIC1_Config =
{
.MODE = IIC_SLAVE ,
.OWN_ADDRESS = 0x78 ,
.ACK_EN = true ,
.IIC_SPEED = IIC_STARDARD_MODE_10K ,
};
//bus error 判断（ITERREN使能）
bool IIC_BUS_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 8)&0x1) ? true :false);}
//应答错误判断
bool IIC_ACK_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 10)&0x1) ? true :false);}
//仲裁
bool IIC_ARBITRAT_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 9)&0x1) ? true :false);}
//溢出/下溢错误
bool IIC_OVERRUN_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 11)&0x1) ? true :false);}
//ITEVFEN使能后有如下事件
//起始状态，起始位发送（主机模式）
bool IIC_SB_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS)&0x1) ? true :false);}
//地址发送（主机模式） / 地址匹配（从机事件）
bool IIC_ADDR_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 1)&0x1) ? true :false);}
//主机模式下，主机已发送10bit地址数据的第一个字节！！！
bool IIC_ADD10_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 3)&0x1) ? true :false);}
//从机模式下，停止条件被接收到
bool IIC_STOPF_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 4)&0x1) ? true :false);}
//数据字节传输成功
bool IIC_BTF_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 2)&0x1) ? true :false);}
//ITEVFEN 且 ITBUFEN 使能后，有如下事件
//数据寄存器非空（接受器读到数据）
bool IIC_RxNE_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 5)&0x1) ? true :false);}
//数据寄存器空（传输完数据）
bool IIC_TxE_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 6)&0x1) ? true :false);}
//总线状态：繁忙与否
uint8_t IIC_Bus_BUSY(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (uint8_t)(((CMSDK_I2Cx->I2C_STS >> 13)&0x1) ? 1 :0);};
//模式确认
bool IIC_MASTER_MODE(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 12)&0x1) ? true :false);}
uint8_t IIC_Config_init(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,IIC_ConfigStructure* IIC_Para )
{
if(CMSDK_I2Cx == CMSDK_I2C0)
{
GPIO_AltFunction(GPIO_6 , ALT_FUNC1);
GPIO_AltFunction(GPIO_7 , ALT_FUNC1);
}
else if(CMSDK_I2Cx == CMSDK_I2C1)
{
GPIO_AltFunction(GPIO_8 , ALT_FUNC2);
GPIO_AltFunction(GPIO_9 , ALT_FUNC2);
}
if(IIC_Para->MODE == IIC_SLAVE)
{
// CMSDK_I2Cx->I2C_CR2|=(1<<7);//|(1<<8);//中断使能--bit8：buffer中断 / bit7：事件中断 / bit6：错误中断
CMSDK_I2Cx->I2C_CR1|=(1);
CMSDK_I2Cx->I2C_OAR = IIC_Para->OWN_ADDRESS ;
if(IIC_Para->ACK_EN == true)
CMSDK_I2Cx->I2C_CR1 |= (1<<5);
}
else
{
/*
IIC master transmitter:
IIC_CR2:配置中断时钟频率
IIC_CR1:使能IIC接口
IIC_CR1:配置START 位 IIC主机
*/
CMSDK_I2Cx->I2C_CR2 |= IIC_Para->IIC_SPEED ;
CMSDK_I2Cx->I2C_CR1 |= (1) ;
CMSDK_I2Cx->I2C_OAR = IIC_Para->OWN_ADDRESS ;
if(IIC_Para->ACK_EN == true)
CMSDK_I2Cx->I2C_CR1 |= (1<<5);
}
return 0;
}
void IIC_ITConfig(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,uint16_t IIC_IT_SEL ,FunctionalState NewState)
{
if(CMSDK_I2Cx == CMSDK_I2C1){
CMSDK_I2C1->I2C_CR2 |= IIC_IT_SEL;
NVIC_DisableIRQ(I2C1_Event_IRQn);
NVIC_ClearPendingIRQ(I2C1_Event_IRQn);
NVIC_DisableIRQ(I2C1_Error_IRQn);
NVIC_ClearPendingIRQ(I2C1_Error_IRQn);
if(NewState == ENABLE)
NVIC_EnableIRQ(I2C1_Event_IRQn);
}
else if(CMSDK_I2Cx == CMSDK_I2C0){
CMSDK_I2C0->I2C_CR2 |= IIC_IT_SEL;
NVIC_DisableIRQ(I2C0_Event_IRQn);
NVIC_ClearPendingIRQ(I2C0_Event_IRQn);
NVIC_DisableIRQ(I2C0_Error_IRQn);
NVIC_ClearPendingIRQ(I2C0_Error_IRQn);
if(NewState == ENABLE)
NVIC_EnableIRQ(I2C0_Event_IRQn);
}
}
void IIC_Cmd(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,FunctionalState NewState) //使能IIC外设
{
if(CMSDK_I2Cx ==CMSDK_I2C0)
{
PCLK_Enable(I2C0_PCLK_EN);
}
else if(CMSDK_I2Cx ==CMSDK_I2C1)
{
PCLK_Enable(I2C1_PCLK_EN);
}
else
{
}
if(NewState == ENABLE)
CMSDK_I2Cx->I2C_CR1 |= (1);
else
CMSDK_I2Cx->I2C_CR1 &=~ (1);
}
void IIC_GenerateSTART(CMSDK_I2C_TypeDef* CMSDK_I2Cx)
{
while(IIC_Bus_BUSY(CMSDK_I2Cx));
CMSDK_I2Cx->I2C_CR1 |= (1<<3);
}
void IIC_GenerateSTOP(CMSDK_I2C_TypeDef* CMSDK_I2Cx)
{
CMSDK_I2Cx->I2C_CR1 |= (1<<4);
}
//general call 用于向总线所有设备发送消息，用于初始化从设备与设备同步
//主设备通过向总线发送0x00地址来触发GENERAL CALL
void IIC_GeneralCallCmd(CMSDK_I2C_TypeDef* CMSDK_I2Cx)
{
}
void IIC_Send7bitAddress(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,uint8_t Address)
{
CMSDK_I2Cx->I2C_DR = Address ;
}
void IIC_SendData(CMSDK_I2C_TypeDef* CMSDK_I2Cx , uint8_t data)
{
CMSDK_I2Cx->I2C_DR = data;
while(IIC_BTF_EVENT(CMSDK_I2Cx) == false); //字节传输完成
}
uint8_t IIC_ReadData(CMSDK_I2C_TypeDef* CMSDK_I2Cx)
{
return CMSDK_I2Cx->I2C_DR;
}
void I2C0_Event_Handler(void)
{
NVIC_ClearPendingIRQ(I2C0_Event_IRQn);
if(IIC_MASTER_MODE(CMSDK_I2C0) == TRUE)
{
if(IIC_SB_EVENT(CMSDK_I2C0) == true )
{
return ;
}
if(IIC_ADDR_EVENT(CMSDK_I2C0) == true )
{
return ;
}
if(IIC_ADD10_EVENT(CMSDK_I2C0) == true)
{
return;
}
}
else
{
if(IIC_ADDR_EVENT(CMSDK_I2C0) == true)
{
return ;
}
if(IIC_STOPF_EVENT(CMSDK_I2C0) == true)
{
//如果不再接收，则关闭IIC!!!
IIC_Cmd(CMSDK_I2C0 ,DISABLE) ;
CMSDK_I2C0->I2C_CR2|=(1<<7); //中断使能--bit8：buffer中断 / bit7：事件中断 / bit6：错误中断
CMSDK_I2C0->I2C_CR1|=(1);
CMSDK_I2C0->I2C_OAR = 0X78 ;
CMSDK_I2C0->I2C_CR1 |= (1<<5);
IIC_Cmd(CMSDK_I2C0 ,ENABLE) ;
return ;
}
}
if(IIC_BTF_EVENT(CMSDK_I2C0) == true)
{
}
if(IIC_RxNE_EVENT(CMSDK_I2C0) == true)
{
uint8_t read_data = (uint8_t)(CMSDK_I2C0->I2C_DR & 0xff);
printf("%d\n", read_data);
}
if(IIC_TxE_EVENT(CMSDK_I2C0) == true)
{
}
return ;
}
void I2C0_Error_Handler(void)
{
NVIC_ClearPendingIRQ(I2C0_Error_IRQn);
if(IIC_BUS_ERROR(CMSDK_I2C0) == true)
{
printf("bus error\n");
return ;
}
if(IIC_ACK_ERROR(CMSDK_I2C0) == true)
{
printf("IIC_ACK_ERROR\n");
return ;
}
if(IIC_ARBITRAT_ERROR(CMSDK_I2C0) == true)
{
printf("IIC_ARBITRAT_ERROR\n");
return ;
}
if(IIC_OVERRUN_ERROR(CMSDK_I2C0) == true)
{
printf("IIC_OVERRUN_ERROR\n");
return ;
}
}
void I2C1_Event_Handler(void)
{
NVIC_ClearPendingIRQ(I2C1_Event_IRQn);
if(IIC_MASTER_MODE(CMSDK_I2C1) == TRUE)
{
if(IIC_SB_EVENT(CMSDK_I2C1) == true )
{
return ;
}
if(IIC_ADDR_EVENT(CMSDK_I2C1) == true )
{
return;
}
if(IIC_ADD10_EVENT(CMSDK_I2C1) == true)
{
return;
}
}
else
{
if(IIC_ADDR_EVENT(CMSDK_I2C1) == true) //作为从机，进入此处则地址匹配！
{
return ;
}
if(IIC_STOPF_EVENT(CMSDK_I2C1) == true) //作为从机，接收到STOP信号
{
printf("get stop\n");
//如果不再接收，则关闭IIC!!!
IIC_Cmd(CMSDK_I2C1 ,DISABLE) ;
CMSDK_I2C1->I2C_CR2|=(1<<7); //中断使能--bit8：buffer中断 / bit7：事件中断 / bit6：错误中断
CMSDK_I2C1->I2C_CR1|=(1);
CMSDK_I2C1->I2C_OAR = 0X78 ;
CMSDK_I2C1->I2C_CR1 |= (1<<5);
IIC_Cmd(CMSDK_I2C1 ,ENABLE) ;
IIC_ITConfig(CMSDK_I2C0,0 ,DISABLE);
IIC_ITConfig(CMSDK_I2C0,0 ,ENABLE);
return ;
}
}
if(IIC_BTF_EVENT(CMSDK_I2C1) == true)
{
}
if((IIC_RxNE_EVENT(CMSDK_I2C1) == true)) //作为从机，buffer非空，读IIC_DR中的数据
{
uint8_t read_data = (uint8_t)(CMSDK_I2C1->I2C_DR & 0xff);
printf("%d\n", read_data);
}
if(IIC_TxE_EVENT(CMSDK_I2C1) == true)
{
}
return ;
}
void I2C1_Error_Handler(void)
{
NVIC_ClearPendingIRQ(I2C1_Error_IRQn);
if(IIC_BUS_ERROR(CMSDK_I2C1) == true)
{
printf("bus error\n");
return ;
}
if(IIC_ACK_ERROR(CMSDK_I2C1) == true)
{
printf("IIC_ACK_ERROR\n");
return ;
}
if(IIC_ARBITRAT_ERROR(CMSDK_I2C1) == true)
{
printf("IIC_ARBITRAT_ERROR\n");
return ;
}
if(IIC_OVERRUN_ERROR(CMSDK_I2C1) == true)
{
printf("IIC_OVERRUN_ERROR\n");
return ;
}
}

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FWLIB/source/ENS1_MTP.c Normal file
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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_MTP.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
/*
MTP说明
1、MTP部分只能按块写入,每块有1024字节大小
块的编号：
SECTOR 0 : 0000H - 03FFH
SECTOR 1 : 0400H - 07FFH
SECTOR 2 : 0800H - 0BFFH
SECTOR 3 : 0C00H - 0FFFH
SECTOR 4 : 1000H - 13FFH
SECTOR 5 : 1400H - 17FFH
SECTOR 6 : 1800H - 1BFFH
SECTOR 7 : 1C00H - 1FFFH
*/
#include "ENS1_MTP.h"
uint16_t write_current_data[4]={0,0,0,0};
STRUCT_MTP_TRIM MTP_FT_SET=
{
.OSCA_FT = 0x10, //默认值为 0X10
.OSC32K_RTRIM = 0x10, //默认值为 0X10
.BG_TRIM = 0x88,
};
uint8_t MTP_init(void)
{
#ifdef ENS1_HSI_16MHz
CMSDK_MTPREG->MTP_CR = 0x00000001;
#elif ENS1_HSI_32MHz
CMSDK_MTPREG->MTP_CR = 0x00000003;
#endif
return 0;
}
//MTP内保存的电流检测数据读取
void flash_read(uint32_t start_addr,uint16_t *test_i){
uint16_t result = 0;
result = HW16_REG(start_addr);
*test_i = result ;
}
//向MTP中写入数据（仅限于向用户自定义块写入！！！）
//可自定义读写的区域为MTP的第0x1BC0块（MTP_BASE_ADDR + 0x6F00）
int8_t flash_buff_write(uint32_t start_addr, uint16_t *buff) {
HW32_REG(start_addr) = ((uint32_t)((*(buff+1)<<16)&0xffff0000) + ((*buff)&0x0000ffff));
// while(!(CMSDK_MTPREG->MTP_SR&0x00000002)){};
if(HW32_REG(start_addr) != ((uint32_t)(*(buff+1)<<16) + *buff ))
{
printf("write error\n");
return -1;
}
return 0;
}
int8_t flash_write_ctrl(uint16_t *buff , uint32_t start_addr){
CMSDK_MTPREG->MTP_CLR = 0xffffffff; //SR寄存器
CMSDK_MTPREG->MTP_CR = 0x00000002; //2等待周期
CMSDK_MTPREG->MTP_ACLR = 0x00000000; //允许软件读写从sector0 -sector 6 （sector7 作为bootloader区）
CMSDK_MTPREG->MTP_KEYR = 0x5a5a5a5a; //key
return flash_buff_write(start_addr, buff);
}
int8_t write_data(void){
uint16_t *wr_data = (uint16_t *)malloc(8*sizeof(uint8_t));
memcpy(wr_data , write_current_data, 8);
int8_t val = flash_write_ctrl(wr_data,DATA_SAVE_ADDR); //第 0x1BC0块
val = flash_write_ctrl(wr_data+2, DATA_SAVE_ADDR + 4);
return val;
}

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_PWM.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ens1_pwm.h"
//PWMx 选择PWM输出通道
//edge_mode pwm边沿模式 默认单边
//pulse_duty 占空比 0-100 （有些偏差）
//freq_HZ 频率 单位 HZ
//pwmEnable 使能输出
void PWM_init(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue* PWM_Para , bool pwmEnable)
{
if(PWMx > 6 || PWMx < 1)
PWMx = IO16_PWM1;
int pwmsel = PWMx-2;
if(pwmsel<0)
pwmsel = 0;
if(PWM_Para->pwm_Duty_cycle>100)
PWM_Para->pwm_Duty_cycle=100;
//IO复用
CMSDK_GPIO->ALTFH |= (0x01 << ((PWMx-1)*2));
uint32_t pulse_width = (uint32_t)((uint8_t)APB_Clock_Freq / ((PRESCALE_PWM+1) * (PWM_Para->pwm_freq)));
CMSDK_PWM->MR0 = pulse_width;
/*模式： 1 单边模式 2 双边正脉冲 3 双边负脉冲*/
if(PWM_Para->mode == pwm_single_mode)
{
//pwm通道1-6的某一个通道的计数值填充
*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(PWM_Para->pwm_Duty_cycle*CMSDK_PWM->MR0/100);
}
else if(PWM_Para->mode == pwm_double_positive_mode)
{
//pwm通道1-6的某一个通道的计数值填充
CMSDK_PWM->PCR |= (1<<pwmsel) ;
if(PWMx < 6 || PWMx > 1) //仅允许使用2-6
{
*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx-1))=(uint32_t)(0);
*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(PWM_Para->pwm_Duty_cycle*pulse_width/100);
}
}
else
{
CMSDK_PWM->PCR |= (1<<pwmsel) ;
if(PWMx < 6 || PWMx >1) //仅允许使用2-6
{
*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx-1))=(uint32_t)(pulse_width);
*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)((100-PWM_Para->pwm_Duty_cycle)*pulse_width/100);
}
}
CMSDK_PWM->PR = PRESCALE_PWM;//Prescale
CMSDK_PWM->LER |= (1)|(1<<PWMx); //加载使能
CMSDK_PWM->TCR |= (1<<1); //计数使能
CMSDK_PWM->MCR |= (1<<1) ; //中断不使能和复位使能| ((PWMx*3+1)<<1)
if(pwmEnable == true)
CMSDK_PWM->PCR |= (0x01 << (PWMx+4));
else
CMSDK_PWM->PCR &=~ (0x01 << (PWMx+4));
}
void PWM_SetFreq(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue * PWM_Para )
{
CMSDK_PWM->MR0 = (uint32_t)((uint8_t)APB_Clock_Freq/ ((PRESCALE_PWM+1) * (PWM_Para->pwm_freq)));
}
void PWM_SetDutyCycle_SingleMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle) //设置占空比
{
PWM_OutputDisable(PWMx);
CMSDK_PWM->LER &=~ (1<<PWMx);
*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(DutyCycle* CMSDK_PWM->MR0/100);
CMSDK_PWM->LER |= (1<<PWMx);
PWM_OutputEnable(PWMx);
}
void PWM_SetDutyCycle_DoublePositiveMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle)
{
if(PWMx < 2)
{
return ;
}
else
{
PWM_OutputDisable(PWMx);
CMSDK_PWM->LER &=~ (1<<PWMx);
*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(DutyCycle*CMSDK_PWM->MR0/100);
CMSDK_PWM->LER |= (1<<PWMx);
PWM_OutputEnable(PWMx);
}
}
void PWM_SetDutyCycle_DoubleNegtiveMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle)
{
if(PWMx < 2)
{
return ;
}
else
{
PWM_OutputDisable(PWMx);
CMSDK_PWM->LER &=~ (1<<PWMx);
*(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)((100-DutyCycle)*CMSDK_PWM->MR0/100);
CMSDK_PWM->LER |= (1<<PWMx);
PWM_OutputEnable(PWMx);
}
}
void PWM_OutputDisable(ENS1_PWM_CHANNEL PWMx)
{
CMSDK_PWM->PCR &=~ (0x01 << (PWMx+4));
}
void PWM_OutputEnable(ENS1_PWM_CHANNEL PWMx)
{
CMSDK_PWM->PCR |= (0x01 << (PWMx+4));
}
uint32_t pwm_irq_occurred_mr[7];
void PWM_Handler(void) {
//MR0 status interrupt
if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR0_INT_STS_Msk)==CMSDK_PWM_MR0_INT_STS_Msk) {
CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR0_INT_STS_Msk;//Clear Interrupt
pwm_irq_occurred_mr[0]++;
}
//MR1 status interrupt
if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR1_INT_STS_Msk)==CMSDK_PWM_MR1_INT_STS_Msk) {
CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR1_INT_STS_Msk;//Clear Interrupt
pwm_irq_occurred_mr[1]++;
}
//MR2 status interrupt
if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR2_INT_STS_Msk)==CMSDK_PWM_MR2_INT_STS_Msk) {
CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR2_INT_STS_Msk;//Clear Interrupt
pwm_irq_occurred_mr[2]++;
}
//MR3 status interrupt
if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR3_INT_STS_Msk)==CMSDK_PWM_MR3_INT_STS_Msk) {
CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR3_INT_STS_Msk;//Clear Interrupt
pwm_irq_occurred_mr[3]++;
}
//MR4 status interrupt
if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR4_INT_STS_Msk)==CMSDK_PWM_MR4_INT_STS_Msk) {
CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR4_INT_STS_Msk;//Clear Interrupt
pwm_irq_occurred_mr[4]++;
}
//MR5 status interrupt
if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR5_INT_STS_Msk)==CMSDK_PWM_MR5_INT_STS_Msk) {
CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR5_INT_STS_Msk;//Clear Interrupt
pwm_irq_occurred_mr[5]++;
}
//MR6 status interrupt
if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR6_INT_STS_Msk)==CMSDK_PWM_MR6_INT_STS_Msk) {
CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR6_INT_STS_Msk;//Clear Interrupt
pwm_irq_occurred_mr[6]++;
}
}

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_SPI.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ENS1_SPI.h"
#include "ENS1_GPIO.h"
/*---------------------------------------------------fifo相关的函数头--------------------------------------------------*/
/*清除FIFO和计数清0*/
uint8_t CLR_TX_FIFO( CMSDK_SPI_TypeDef* SPIx)
{
return (uint8_t)(SPIx->FCR>>8 & 0x1);
}
uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx)
{
return (uint8_t)(SPIx->FCR>>1 & 0x1);
}
/*FIFO 状态读取*/
uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
{
return (uint8_t)(((SPIx->FCR & 0x1) == 0x1) ? ((uint8_t)((SPIx->FSR & 0x001f0000)>>16)):0); //读取当前接收FIFO数据长度
}
uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
{
return (uint8_t)(((SPIx->FCR & 0x1) == 0x1) ? ((uint8_t)((SPIx->FSR & 0x00001f00)>>8)):0); //读取当前发送FIFO数据长度
}
SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx)
{
return (SPI_BUSY_STATE)((((SPIx->FSR & 0x10) >> 4)==1) ? ( BUSY ) : ( NOTBUSY )); //读取当前SPI是否繁忙
}
uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
{
return (uint8_t)((((SPIx->FSR & 0x8)>> 3 )==1) ? (1) : (0)) ; //当前读取FIFO是否为满？
}
uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
{
return (uint8_t)((((SPIx->FSR & 0x4) >> 2)==1) ? (1) : (0) ) ; //当前读取FIFO是否为空？
}
uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
{
return (uint8_t)((((SPIx->FSR & 0x2) >> 1)==1) ? (1) : (0)) ; //当前发送FIFO是否为满？
}
uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
{
return (uint8_t)(((SPIx->FSR & 0x1)==1) ? (1) : (0)) ; //当前发送FIFO是否为空？
}
/*FIFO使能/DMA使能*/
uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx) //读FIFO设置
{
return (uint8_t)(SPIx->FCR & 0x1) ;
}
uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx )
{
SPIx->FCR |= 0x1;
return 0;//(uint8_t)(SPIx->FCR & 0x1) ;
}
uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx )
{
SPIx->FCR &=~ 0x1;
return (uint8_t)(SPIx->FCR & 0x1) ;
}
uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET)
{
if(TXDMA_SET == true)
SPIx->CTRL2 |= (1<<5);
else if(TXDMA_SET == false)
SPIx->CTRL2 &=~ (1<<5);
if(TXDMA_SET == true)
SPIx->CTRL2 |= (1<<4);
else if(TXDMA_SET == false)
SPIx->CTRL2 &=~ (1<<4);
return (uint8_t)((SPIx->CTRL2>>4)&0x3);
}
/*------------------------------------------------------fifo相关的函数尾--------------------------------------------------*/
/*----------------------------------------------------------SPI配置-------------------------------------------------------*/
//读取当前的SPI模式
uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx)
{
return ((SPIx->CTRL1 & 0x7000) >> 12);
}
//NSS通道选择
uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS)
{
if(ENorDIS == ENABLE)
SPIx->CTRL2 |= ( 1 << NSSx );
else
SPIx->CTRL2 &=~ ( 1 << NSSx);
return (uint8_t)((SPIx->CTRL2 & 0x0f00) >> 8);
}
//spi的参数配置
uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx ,
struct SPI_ModeConfig_Struct SPI_Config,
struct SPI_FIFO_Struct FIFO_Struct)
{
/*1、GPIO ALTER*/
if(SPIx == CMSDK_SPI1)
{
GPIO_AltFunction(GPIO_16 , ALT_FUNC2);
GPIO_AltFunction(GPIO_17 , ALT_FUNC2);
GPIO_AltFunction(GPIO_18 , ALT_FUNC2);
GPIO_AltFunction(GPIO_19 , ALT_FUNC2);
}
else if(SPIx == CMSDK_SPI0)
{
GPIO_AltFunction(GPIO_8, ALT_FUNC1);
GPIO_AltFunction(GPIO_9, ALT_FUNC1);
GPIO_AltFunction(GPIO_10,ALT_FUNC1);
GPIO_AltFunction(GPIO_11,ALT_FUNC1);
}
/*
2、写SPI_CTRL1寄存器
（1）配置时钟波特率BAUD_RATE[2:0]
（2）配置时钟极性和相位 CPOL and CPHA bits
（3）选择传输模式 BIDI_EN, BIDI_MODE, UNIDI_MODE bits
（4）配置LSB_SEL位来定义帧格式
（5）通过配置NSS_TOGGLE、NSS_MST_CTRL、NSS_MST_SW bits来选择NSS控制方式 bit11 9 8
（6）通过配置MST_SLV_SEL位选择主模式或从模式
*/
SPIx->CTRL1 = (SPIx->CTRL1&~ 0xffff) | ( SPI_Config.BAUD_FPCLKdivx << 4);
SPIx->CTRL1 |= (SPI_Config.SPI_MODE << 2);
SPIx->CTRL1 |= (SPI_Config.SPI_TRANS_MODE << 12 );
SPIx->CTRL1 &=~ (0x1 << 7); //帧格式默认大端模式
SPIx->CTRL1 &=~ (0x1 << 8); //帧格式默认大端模式
SPIx->CTRL1 &=~ (1 << 11);
SPIx->CTRL1 |= (1 << 11) ; // 默认硬件生成NSS
if(SPI_Config.MS_SEL == MASTER)
{
SPIx->CTRL1 |= (1<<1);
}
else
{
SPIx->CTRL1 &=~ (1<<1);
}
/*
3、写SPI_CTRL2寄存器
（1）配置CHAR_LEN[3:0]位来选择传输的数据长度
（2）选择“NSS端口” NSS0_EN, NSS1_EN, NSS2_EN
（3）通过配置主机选择合适的RX数据采集阶段 SAMP_PHASE(1:0)位
（4）通过配置C2T_DELAY和T2C_DELAY位，可以根据从设备的需求选择合适的C2T/T2C延迟
（5）通过配置TXDMA_EN和RXDMA_EN位使能或使能FIFO模式的TX/RX DMA。
*/
SPIx->CTRL2 = (SPIx->CTRL2&~ 0xffff);
if(SPI_Config.CHAR_LEN < 4)
{
}
else if((SPI_Config.CHAR_LEN >= 4) && (SPI_Config.CHAR_LEN < 17))
{
SPIx->CTRL2 |= (SPI_Config.CHAR_LEN -1);
}
else
{
}
SPI_NSS_CHANNEL(SPIx ,SPI_Config.NSSx ,ENABLE);
//rx读采集相位， 仅仅在主模式下有效，默认选normal
//C2T_DELAY ,仅在主模式下有效
//T2C_DELAY, 仅在主模式下有效
if(SPI_Config.MS_SEL == MASTER)
{
SPIx->CTRL2 |= (SPI_Config.SAMP_PHASE << 6);
//T2C 是Transmit-end-to-chip-inactive 的延迟时间，默认为1T SCK
//C2T 是Chip-select-active-to-transmit-start 的时间 默认1T SCK ,这里对这两参数没做设置
}
/*
4、写FIFO 寄存器
（1）配置TX_FIFO_TH或RX_FIFO_TH来定义触发级别阈值
（2）通过配置TX_FIFO_CLR和RX_FIFO_CLR位清除TX/RX FIFO
（3）通过配置fif_en位使能或禁用FIFO模式
*/
SPIx->FCR |= (FIFO_Struct.TX_FIFO_TH << 9 );
SPIx->FCR |= (FIFO_Struct.RX_FIFO_TH << 2 );
CLR_TX_FIFO(SPIx) ;
CLR_RX_FIFO(SPIx) ;
if(FIFO_Struct.FIFO_ENABLE_SET == true)
SPI_FIFO_ENABLE(SPIx);
//SPI_FIFODMA_SET(SPIx ,FIFO_Struct.TXDMA_SET ,FIFO_Struct.RXDMA_SET);
return 0;
}
/*---------------------------------------------SPI启动和停止-------------------------------------------------*/
uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx )
{
SPIx->CTRL1 |= (1);
return (uint8_t)(SPIx->CTRL1 & 0x1);
}
uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx)
{
if((READ_SPI_MODE(SPIx)==(L2_UniDirect_R & 0x7)) || (READ_SPI_MODE(SPIx)==(L1_BiDirect_R & 0x7)))
{
if(SPI_FIFO_STATE(SPIx) == 1)
{
//读 RX的FIFO 直到 FIFO长度为 0
while((RX_FIFO_LEN(SPIx) != 0) || (BUSY_STATE(SPIx) == BUSY))
{
//save_data = READ_SPI_RCVBuff(SPIx);
}
SPIx->CTRL1 &=~ (1);
}
else if(SPI_FIFO_STATE(SPIx) == 0)
{
while(BUSY_STATE(SPIx) == BUSY);
SPIx->CTRL1 &=~ (1);
}
}
else
{
if(SPI_FIFO_STATE(SPIx) == 1)
{
while((TX_FIFO_LEN(SPIx)!= 0) || (BUSY_STATE(SPIx) == BUSY));
SPIx->CTRL1 &=~ (1);
//读 RX的FIFO 直到 FIFO长度为 0
while(RX_FIFO_LEN(SPIx) != 0)
{
uint16_t save_data = READ_SPI_RCVBuff(SPIx);
}
}
else if(SPI_FIFO_STATE(SPIx) == 0)
{
while(BUSY_STATE(SPIx) == BUSY);
SPIx->CTRL1 &=~ (1);
}
}
return (uint8_t)(SPIx->CTRL1*0x1);
}
/*-----------------------------------------读 / 写 SPI BUFFER的数据-------------------------------------------------*/
//读被接收的数据 最多16bits
uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx)
{
return (uint16_t)(SPIx->RBR & 0xffff);
}
//写数据
void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data)
{
SPIx->THR = data;
while(BUSY_STATE(SPIx) == BUSY);
}
/*------------------------------------------------------SPI中断------------------------------------------------------*/
uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET)
{
NVIC_DisableIRQ(IRQn);
NVIC_ClearPendingIRQ(IRQn);
if(IRQn == SPI0_IRQn)
{
CMSDK_SPI0->IER = ((CMSDK_SPI0->IER &~ (0xff)) | SPI_INT_BIT_SET);
}
else if(IRQn == SPI1_IRQn)
{
CMSDK_SPI1->IER = ((CMSDK_SPI0->IER &~ (0xff)) | SPI_INT_BIT_SET);
}
if(SPI_INT_ENABLE == true)
{
NVIC_EnableIRQ(IRQn);
}
else
{
NVIC_DisableIRQ(IRQn);
}
return 0;
}
//中断处理函数
/*
中断有如下类型：
1、发送部分有 下溢 中断（发送数据没有啦）
2、接收部分有 溢出 中断（接满啦）
3、收发完成中断？
4、发送缓冲区空 中断
5、接收缓冲区非空 中断
*/
void SPI1_Handler(void)
{
NVIC_ClearPendingIRQ(SPI1_IRQn);
uint8_t read_fifo=0;
if((CMSDK_SPI1->INTSTATUS & 0x10 )== UNDERRUN_INT) //下溢-发送时发送数据已为空时触发
{
CMSDK_SPI1->INTCLEAR |= (1<<4); //清除中断
}
if((CMSDK_SPI1->INTSTATUS & 0x8) ==OVERRUN_INT)
{
CMSDK_SPI1->INTCLEAR |= (1<<3);
}
if((CMSDK_SPI1->INTSTATUS& 0x4) ==CMPL_INT)
{
CMSDK_SPI1->INTCLEAR |= (1<<2);
}
if((CMSDK_SPI1->INTSTATUS &0x2) ==TXE_INT)
{
}
if((CMSDK_SPI1->INTSTATUS & 1)== RXNE_INT)
{
while(!RX_FIFO_EMPTY(CMSDK_SPI1))
{
read_fifo = READ_SPI_RCVBuff(CMSDK_SPI1);
printf("masterrcv:%d\n",read_fifo);
}
}
}
void SPI0_Handler(void)
{
NVIC_ClearPendingIRQ(SPI0_IRQn);
uint8_t read_fifo=0;
if((CMSDK_SPI0->INTSTATUS & 0x10 )== UNDERRUN_INT) //下溢-发送时发送数据已为空时触发
{
CMSDK_SPI0->INTCLEAR |= (1<<4); //清除中断
}
if((CMSDK_SPI0->INTSTATUS & 0x8) ==OVERRUN_INT)
{
CMSDK_SPI0->INTCLEAR |= (1<<3);
}
if((CMSDK_SPI0->INTSTATUS& 0x4) ==CMPL_INT)
{
CMSDK_SPI0->INTCLEAR |= (1<<2);
}
if((CMSDK_SPI0->INTSTATUS &0x2) ==TXE_INT)
{
}
if((CMSDK_SPI0->INTSTATUS & 1)== RXNE_INT)
{
while(!RX_FIFO_EMPTY(CMSDK_SPI0))
{
read_fifo = READ_SPI_RCVBuff(CMSDK_SPI0);
printf("masterrcv:%d\n",read_fifo);
}
}
}

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#include "ENS1_TIMER.h"
#include "ENS_CURRENT_CALIBRATION.h"
#include "ENS1_CLOCK.h"
void TIMER0_Init(uint32_t Int_Period) //形参，输入中断触发周期 （单位ms）
{
PCLK_Enable(TIMER0_PCLK_EN);
NVIC_DisableIRQ(TIMER0_IRQn);
NVIC_ClearPendingIRQ(TIMER0_IRQn);
CMSDK_timer_Init(CMSDK_TIMER0,(uint32_t)(APB_Clock_Freq / 1000 *Int_Period) , 1); //
NVIC_EnableIRQ(TIMER0_IRQn);
}
void TIMER1_Init(uint32_t Int_Period)
{
PCLK_Enable(TIMER1_PCLK_EN);
NVIC_DisableIRQ(TIMER1_IRQn);
NVIC_ClearPendingIRQ(TIMER1_IRQn);
CMSDK_timer_Init(CMSDK_TIMER1,(uint32_t)(APB_Clock_Freq / 1000 * Int_Period) , 1); // 1ms
NVIC_EnableIRQ(TIMER1_IRQn);
}
/*使能定时器中断*/
void CMSDK_timer_EnableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
{
CMSDK_TIMER->CTRL |= CMSDK_TIMER_CTRL_IRQEN_Msk;
}
/*关闭定时器中断*/
void CMSDK_timer_DisableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
{
CMSDK_TIMER->CTRL &= ~CMSDK_TIMER_CTRL_IRQEN_Msk;
}
/*定时器启动*/
void CMSDK_timer_StartTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
{
CMSDK_TIMER->CTRL |= CMSDK_TIMER_CTRL_EN_Msk;
}
/*定时器关闭*/
void CMSDK_timer_StopTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
{
CMSDK_TIMER->CTRL &= ~CMSDK_TIMER_CTRL_EN_Msk;
}
/*获取定时器Value*/
uint32_t CMSDK_timer_GetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
{
return CMSDK_TIMER->VALUE;
}
/*设置定时器值*/
void CMSDK_timer_SetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value)
{
CMSDK_TIMER->VALUE = value;
}
/*获取重载值*/
uint32_t CMSDK_timer_GetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
{
return CMSDK_TIMER->RELOAD;
}
/*设置重载值*/
void CMSDK_timer_SetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value)
{
CMSDK_TIMER->RELOAD = value;
}
void CMSDK_timer_ClearIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
{
CMSDK_TIMER->INTCLEAR = CMSDK_TIMER_INTCLEAR_Msk;
}
/*返回定时器状态*/
uint32_t CMSDK_timer_StatusIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER)
{
return CMSDK_TIMER->INTSTATUS;
}
/*初始化定时器*/
void CMSDK_timer_Init(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload, uint8_t irq_en)
{
uint32_t new_ctrl = 0;
CMSDK_TIMER->VALUE = reload;
CMSDK_TIMER->RELOAD = reload;
if (irq_en!=0)
new_ctrl |= CMSDK_TIMER_CTRL_IRQEN_Msk; /* non zero - enable IRQ */
new_ctrl |= CMSDK_TIMER_CTRL_EN_Msk; /* enable timer */
CMSDK_TIMER->CTRL = new_ctrl;
}
/**
*
* @param *CMSDK_TIMER Timer Pointer
* @param reload The value to which the timer is to be set after an underflow has occurred
* @param irq_en Defines whether the timer IRQ is to be enabled
* @return none
* @brief Initialises the timer to use the external clock and specifies the timer reload value and whether IRQ is enabled or not.
*/
void CMSDK_timer_Init_ExtClock(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,uint32_t irq_en)
{
CMSDK_TIMER->CTRL = 0;
CMSDK_TIMER->VALUE = reload;
CMSDK_TIMER->RELOAD = reload;
if (irq_en!=0) /* non zero - enable IRQ */
CMSDK_TIMER->CTRL = (CMSDK_TIMER_CTRL_IRQEN_Msk |
CMSDK_TIMER_CTRL_SELEXTCLK_Msk |CMSDK_TIMER_CTRL_EN_Msk);
else { /* zero - do not enable IRQ */
CMSDK_TIMER->CTRL = ( CMSDK_TIMER_CTRL_EN_Msk |
CMSDK_TIMER_CTRL_SELEXTCLK_Msk); /* enable timer */
}
}
/**
*
* @brief Initialises the timer to use the internal clock but with an external enable. It also specifies the timer reload value and whether IRQ is enabled or not.
*
* @param *CMSDK_TIMER Timer Pointer
* @param reload The value to which the timer is to be set after an underflow has occurred
* @param irq_en Defines whether the timer IRQ is to be enabled
* @return none
* Timer 0 only
*
*/
void CMSDK_timer_Init_ExtEnable(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,uint32_t irq_en)
{
CMSDK_TIMER->CTRL = 0;
CMSDK_TIMER->VALUE = reload;
CMSDK_TIMER->RELOAD = reload;
if (irq_en!=0) /* non zero - enable IRQ */
CMSDK_TIMER->CTRL = (CMSDK_TIMER_CTRL_IRQEN_Msk | CMSDK_TIMER_CTRL_SELEXTEN_Msk | CMSDK_TIMER_CTRL_EN_Msk);
else{ /* zero - do not enable IRQ */
CMSDK_TIMER->CTRL = ( CMSDK_TIMER_CTRL_EN_Msk | CMSDK_TIMER_CTRL_SELEXTEN_Msk); /* enable timer */
}
}
/*DUAL Timer driver functions*/
/**
*
* @param *CMSDK_DUALTIMER DUAL Timer Pointer
* @return none
*
* @brief Start timer in dual timers.
*/
/* Start Timer */
void CMSDK_dualtimer_start(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx)
{
CMSDK_DUALTIMERx->TimerControl |= CMSDK_DUALTIMER_CTRL_EN_Msk;
}
/**
*
* @param *CMSDK_DUALTIMER DUAL Timer Pointer
* @return none
*
* @brief Stop timer in dual timers.
*/
/* Stop Timer */
void CMSDK_dualtimer_stop(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx)
{
CMSDK_DUALTIMERx->TimerControl &= ~CMSDK_DUALTIMER_CTRL_EN_Msk;
}
/**
*
* @param *CMSDK_DUALTIMER DUAL Timer Pointer
* @return none
*
* @brief Clear the interrupt request in dual timers.
*/
/* Clear the Interrupt */
void CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx)
{
CMSDK_DUALTIMERx->TimerIntClr = 0;
}
/**
*
* @param *CMSDK_DUALTIMER DUAL Timer Pointer
* @return none
*
* @brief Setup Free running mode in dual timers.
*/
/* Free running timer mode */
void CMSDK_dualtimer_setup_freerunning(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx,
unsigned int cycle, unsigned int prescale, unsigned int interrupt, unsigned int size)
{
int ctrl_val;
CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
/* Previous timer activities might have trigger interrupt flag,
so need to clear it */
CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMERx);
CMSDK_DUALTIMERx->TimerLoad = cycle;
ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
(interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
(size & 0x1) << CMSDK_DUALTIMER_CTRL_SIZE_Pos |
CMSDK_DUALTIMER_CTRL_EN_Msk;
CMSDK_DUALTIMERx->TimerControl = ctrl_val;
}
/**
*
* @param *CMSDK_DUALTIMER DUAL Timer Pointer
* @return none
*
* @brief Setup Periodic mode in dual timers.
*/
/* Periodic timer mode */
void CMSDK_dualtimer_setup_periodic(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx,
unsigned int cycle, unsigned int prescale,
unsigned int interrupt, unsigned int size)
{
int ctrl_val;
CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
/* Previous timer activities might have trigger interrupt flag,
so need to clear it */
CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMERx);
CMSDK_DUALTIMERx->TimerLoad = cycle;
ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
(interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
(size & 0x1) << CMSDK_DUALTIMER_CTRL_SIZE_Pos |
CMSDK_DUALTIMER_CTRL_EN_Msk |
CMSDK_DUALTIMER_CTRL_MODE_Msk;
CMSDK_DUALTIMERx->TimerControl = ctrl_val;
}
/**
*
* @param *CMSDK_DUALTIMER DUAL Timer Pointer
* @return none
*
* @brief Setup One shot mode in dual timers.
*/
/* One shot timer mode */
void CMSDK_dualtimer_setup_oneshot(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx,
unsigned int cycle, unsigned int prescale,
unsigned int interrupt, unsigned int size)
{
int ctrl_val;
CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */
/* Previous timer activities might have trigger interrupt flag,
so need to clear it */
CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMERx);
CMSDK_DUALTIMERx->TimerLoad = cycle;
ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos |
(interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos |
(size & 0x1) << CMSDK_DUALTIMER_CTRL_SIZE_Pos |
CMSDK_DUALTIMER_CTRL_EN_Msk |
CMSDK_DUALTIMER_CTRL_ONESHOT_Msk;
CMSDK_DUALTIMERx->TimerControl = ctrl_val;
}
/*RTC driver functions*/
/**
*
* @param *CMSDK_RTC RTC Pointer
* @return none
*
* @brief Initialize RTC Calender
*/
void CMSDK_RTC_Init_Calender(uint16_t prescaler, uint8_t data_mode, uint8_t hour_mode,
uint32_t init_time, uint32_t init_date)
{
uint32_t new_reg_ctrl = 0;
//wait for rtc prescaler sync ready
while(!((CMSDK_RTC->SR & CMSDK_RTC_PRES_SYNC_READY_Msk) >> CMSDK_RTC_PRES_SYNC_READY_Pos));
//set prescaler
CMSDK_RTC->PR = prescaler;
//config data/hour mode
if(data_mode != 0) new_reg_ctrl |= CMSDK_RTC_DATA_MODE_Msk;
if(hour_mode != 0) new_reg_ctrl |= CMSDK_RTC_HOUR_MODE_Msk;
CMSDK_RTC->CR = new_reg_ctrl;
//wait for init sync ready
while(!(CMSDK_RTC->SR & CMSDK_RTC_INIT_SYNC_READY_Msk));
//set INIT
CMSDK_RTC->CR |= CMSDK_RTC_INIT_EN_Msk;
//Set Initial Time & Date
CMSDK_RTC->TR = init_time;
CMSDK_RTC->DR = init_date;
//Clear INIT bit
CMSDK_RTC->CR &= ~CMSDK_RTC_INIT_EN_Msk;
//wait for init sync ready
while(!(CMSDK_RTC->SR & CMSDK_RTC_INIT_SYNC_READY_Msk));
return;
}
/**
*
* @param *CMSDK_RTC RTC Pointer
* @return none
*
* @brief Config RTC Alarm
*/
void CMSDK_RTC_Config_Alarm(uint16_t prescaler, uint8_t data_mode, uint8_t hour_mode,
uint32_t init_time, uint32_t init_date, uint32_t alarm_time,
uint32_t alarm_date)
{
uint32_t new_reg_ctrl = 0;
//wait for rtc prescaler sync ready
while(!((CMSDK_RTC->SR & CMSDK_RTC_PRES_SYNC_READY_Msk) >> CMSDK_RTC_PRES_SYNC_READY_Pos));
//set prescaler
CMSDK_RTC->PR = prescaler;
//config data/hour mode
if(data_mode != 0) new_reg_ctrl |= CMSDK_RTC_DATA_MODE_Msk;
if(hour_mode != 0) new_reg_ctrl |= CMSDK_RTC_HOUR_MODE_Msk;
CMSDK_RTC->CR = new_reg_ctrl;
//wait for init sync ready
while(!(CMSDK_RTC->SR & CMSDK_RTC_INIT_SYNC_READY_Msk));
//set INIT
CMSDK_RTC->CR |= CMSDK_RTC_INIT_EN_Msk;
//Set Initial Time & Date
CMSDK_RTC->TR = init_time;
CMSDK_RTC->DR = init_date;
//Set Alarm Time & Date
CMSDK_RTC->TAR = alarm_time;
CMSDK_RTC->DAR = alarm_date;
//Alarm enabled
CMSDK_RTC->CR |= CMSDK_RTC_ALARM_EN_Msk;
//Clear INIT bit
CMSDK_RTC->CR &= ~CMSDK_RTC_INIT_EN_Msk;
return;
}
/**
*
* @param *CMSDK_RTC RTC Pointer
* @return none
*
* @brief Config Period Wakeup
*/
void CMSDK_RTC_Config_PeriodWake(uint8_t clock_sel, uint16_t prescaler, uint16_t period_time)
{
if(clock_sel) {
CMSDK_RTC->CR |= CMSDK_RTC_WUT_CLK_EN_Msk;
//wait for rtc prescaler sync ready
while(!((CMSDK_RTC->SR & CMSDK_RTC_PRES_SYNC_READY_Msk) >> CMSDK_RTC_PRES_SYNC_READY_Pos));
//set prescaler
CMSDK_RTC->PR = prescaler;
}
else {
CMSDK_RTC->CR &= ~CMSDK_RTC_WUT_CLK_EN_Msk;
//wait for wut prescaler sync ready
while(!((CMSDK_RTC->SR & CMSDK_RTC_WUT_PRES_SYNC_READY_Msk) >> CMSDK_RTC_WUT_PRES_SYNC_READY_Pos));
//set prescaler
CMSDK_RTC->WPR = prescaler;
}
//wait for wut value sync ready
while(!((CMSDK_RTC->SR & CMSDK_RTC_WUT_VAL_SYNC_READY_Msk) >> CMSDK_RTC_WUT_VAL_SYNC_READY_Pos));
//set Wakeup time register
CMSDK_RTC->WTR = period_time;
//Config CR with Periodic Wakeup timer enabled
CMSDK_RTC->CR |= CMSDK_RTC_WUT_EN_Msk;
return;
}
// --------------------------------------------------------------- //
// TIMER0_IRQ
// --------------------------------------------------------------- //
uint32_t timer0_irq_occurred=0;
uint32_t time_flag =0;
void TIMER0_Handler(void){
CMSDK_TIMER0->INTCLEAR = 1;
timer0_irq_occurred++;
if(timer0_irq_occurred % 1000 == 0)
{
GPIO_Overturn(GPIO_19);
time_flag++;
printf("%d s\n",time_flag);
}
}
// --------------------------------------------------------------- //
// TIMER1_IRQ
// --------------------------------------------------------------- //
uint32_t timer1_irq_occurred=0;
void TIMER1_Handler(void){
CMSDK_TIMER1->INTCLEAR = 1;
timer1_irq_occurred++;
}

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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_UART.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
/*
ENS1 uart特性说明
1 符合AMBA APB规范
2 最高115200bps波特率(可以有更高的设置)
3 发送 接收 分离FIFO （16字节）
4 支持自动流控
5 标准异步通信位(开始、停止、奇偶校验)
6 DMA
7 支持回环测试
8 中断
9 全可编程串行接口特点:
数据位可设置： 5，6，7，8
偶、奇或非奇偶位的生成和检测
可产生1、1.5或2位停止位
*/
#include "my_header.h"
#include "ENS1_UART.h"
#include "ENS1_GPIO.h"
UART_FifoStructrue UART1_Fifo = {
.level = bytes_8 ,
.DMA_Enable = 0 ,
.FIFO_Enable = 1 ,
};
UART_InitStructure UART1_Init = {
.UART_BaudRate = 115200 , //计算出来的DLL DLH不为整数， 1、需要校准RC精确度，2、需要调整此处的波特率
.UART_HardwareFlowControl = 0,
.FifoSetting = &UART1_Fifo ,
};
UART_ITStructure UART1_ITSet = {
.UartIntModel = RLSI_EN | RDAI_EN ,
};
/*判断是否有中断挂起*/
uint8_t UART_INT_PEND(CMSDK_UART_TypeDef* UARTx) //为0时有UART的中断挂起
{
return (uint8_t)(UARTx->IIR & 0x1);
}
/*中断类型判断*/
uint8_t UART_INT_TYPE(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((UARTx->IIR >> 1) & 0x7 );
}
/*fifo 使用指示器*/
uint8_t UART_FIFO_USE(CMSDK_UART_TypeDef* UARTx) //0:非fifo模式 1：fifo 使能
{
return (uint8_t)((UARTx->IIR >> 6) & 0x3);
}
/*清除传输FIFO*/
void UART_TXCLR(CMSDK_UART_TypeDef* UARTx)
{
UARTx->FCR |= (1<<2) ;
}
/*清除接收FIFO*/
void UART_RXCLR(CMSDK_UART_TypeDef* UARTx)
{
UARTx->FCR |= (1<<1);
}
/*FIFO使能*/
void UART_FIFOEnable(CMSDK_UART_TypeDef* UARTx)
{
UARTx->FCR |= (1);
}
/*FIFO关闭*/
void UART_FIFODisable(CMSDK_UART_TypeDef* UARTx)
{
UARTx->FCR &=~ 1;
}
/*接收数据*/
uint8_t READ_UART_RCVBuff(CMSDK_UART_TypeDef* UARTx )
{
return (uint8_t)(UARTx->RBR & 0xff);
}
/*发送数据*/
void WRITE_UART_THRBuff(CMSDK_UART_TypeDef* UARTx ,uint8_t data)
{
UARTx->THR = data;
}
/*FIFO 状态读取*/
uint8_t UART_RX_FIFO_LEN(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((UARTx->FSR & 0x001f0000)>>16); //读取当前接收FIFO数据长度
}
uint8_t UART_TX_FIFO_LEN(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((UARTx->FSR & 0x00001f00)>>8); //读取当前发送FIFO数据长度
}
uint8_t UART_RX_FIFO_FULL(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((((UARTx->FSR & 0x8)>> 3 )==1) ? (1) : (0)) ; //当前读取FIFO是否为满？
}
uint8_t UART_RX_FIFO_EMPTY(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((((UARTx->FSR & 0x4) >> 2)==1) ? (1) : (0) ) ; //当前读取FIFO是否为空？
}
uint8_t UART_TX_FIFO_FULL(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((((UARTx->FSR & 0x2) >> 1)==1) ? (1) : (0)) ; //当前发送FIFO是否为满？
}
uint8_t UART_TX_FIFO_EMPTY(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)(((UARTx->FSR & 0x1)==1) ? (1) : (0)) ; //当前发送FIFO是否为空？
}
/*收发线状态获取*/
uint8_t UARTLine_RCVError(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((UARTx->LSR>>7) & 0x1); //返回0 没有错误， 返回1 在fifo和非fifo状态下都有一个校验/帧/或接收缓存或fifo 的中断指示（默认不使能break）
}
/*判断发送缓存是否为空*/
uint8_t UARTLine_TRANSEmpty(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((UARTx->LSR>>6) & 0x1) ;
}
/*判断THR是否为空*/
uint8_t UARTLine_THREmpty(CMSDK_UART_TypeDef* UARTx)
{
return (uint8_t)((UARTx->LSR>>5) & 0x1) ;
}
/*
初始化UART需要以下步骤:
1. 执行必要的设备引脚多路复用设置。
2. 通过将适当的时钟除数值写入除数锁存寄存器(DLL和DLH)来设置所需的波特率。
3. 如果要使用FIFO，请选择所需的触发等级，并通过将适当的值写入(FCR)来启用FIFO。
在FCR寄存器的 FIFOEN 位需首先配置。
4. 通过向行控制寄存器(LCR)写入适当的值来选择所需的协议设置。
5. 如果需要自动流量控制，则将适当的值写入调制解调器控制寄存器(MCR)。
请注意，并非所有uart都支持自动流量控制。
6. 对挂起事件的选择所需响应通过配置FREE位，
通过在(PMU)寄存器中设置TXRST和RXRST位来释放位并使能UART
*/
//uart初始化，参数1：uart0/1，参数2：uart参数设置结构体
void UART_Init(CMSDK_UART_TypeDef *CMSDK_UART, UART_InitStructure* uart_paraX){
uint16_t divisor_value;
uint8_t overSamp_mode;
/* 1 GPIO - alt_function*/
if(CMSDK_UART == CMSDK_UART0){
PCLK_Enable(UART0_PCLK_EN);
GPIO_AltFunction(UART0_RX , ALT_FUNC1); //rx
GPIO_AltFunction(UART0_TX , ALT_FUNC1); //tx
}
else if(CMSDK_UART == CMSDK_UART1)
{
PCLK_Enable(UART1_PCLK_EN);
GPIO_AltFunction(UART1_RX , ALT_FUNC1); //RX
GPIO_AltFunction(UART1_TX , ALT_FUNC1); //TX
}
/* 2 波特率设置*/
if(((CMSDK_UART->MDR)&0x00000001) == 0)
{
overSamp_mode = 16; //默认0
}
else
{
overSamp_mode = 13;
}
divisor_value = (uint16_t)((uint32_t)(APB_Clock_Freq / uart_paraX->UART_BaudRate / overSamp_mode) - 1);
CMSDK_UART->DLL = (uint8_t)(divisor_value & 0x0011);
CMSDK_UART->DLH = (uint8_t)((divisor_value & 0x1100)>>8);
/*FCR配置 FIFO control*/
CMSDK_UART->FCR |= (uart_paraX->FifoSetting->level <<6);
if(uart_paraX->FifoSetting->FIFO_Enable == 1)
{
CMSDK_UART->FCR |= (1);
}
/*LCR配置,不做配置，默认N 8 1 */
/*MCR自动流控配置*/
if(uart_paraX->UART_HardwareFlowControl == 1)
{
CMSDK_UART->MCR |= (1<<5);
}
/*电源管理寄存器PMU 的TXRST和RXRST设置,不需要设置*/
}
/*UART 的中断设置*/
void UART_ITConfig(CMSDK_UART_TypeDef *CMSDK_UART, UART_ITStructure* uart_paraX)
{
if(CMSDK_UART == CMSDK_UART1){
NVIC_DisableIRQ(UART1_IRQn);//Disable NVIC interrupt
NVIC_ClearPendingIRQ(UART1_IRQn);//Clear Pending NVINVIC_EnableIRQ(UART1_IRQn);//Enable NVIC interrupt
}
else if(CMSDK_UART == CMSDK_UART0){
NVIC_DisableIRQ(UART0_IRQn);//Disable NVIC interrupt
NVIC_ClearPendingIRQ(UART0_IRQn);//Clear Pending NVIC interrupt
}
/*IER配置，中断使能寄存器*/
CMSDK_UART->IER |= (uart_paraX->UartIntModel);
if(CMSDK_UART == CMSDK_UART1){
NVIC_EnableIRQ(UART1_IRQn);
}
else if(CMSDK_UART == CMSDK_UART0){
NVIC_EnableIRQ(UART0_IRQn);
}
}
unsigned char UartPutc(CMSDK_UART_TypeDef *CMSDK_UART ,unsigned char my_ch)
{
while (UARTLine_THREmpty(CMSDK_UART) == 0x0);
WRITE_UART_THRBuff(CMSDK_UART,my_ch);
return (my_ch);
}
/*
中断与中断状态清除
1 接收线状态：INT_RCV_LINE_STATUS
溢出、校验、帧错误或检测到break
中断清除方式：对于溢出错误，读取LSR 可清除中断，对于校验、帧错误或break，中断需要等待所有的错误数据被读取后才被清除
2 接收数据就绪： INT_RCV_DATA_AVAILABLE
非FIFO模式下，接收数据准备就绪， fifo模式下，达到触发阈值，如果四个字节时间内没有访问FIFO ,就再次触发
中断清除方式：非FIFO模式下，RBR被读取 ， FIFO模式下，FIFO低于触发阈值被清除
3 接收超时：INT_CHAR_TIMEOUT_INDICATION
仅仅FIFO模式有效 ， 在最后四个字节的时间内，没有字符从接收器FIFO 中移除或者输入，并且在此期间接收器FIFO中至少有一个字符
中断清除方式：（1）1个字节从接收FIFO中被读出 （2）一个新的字节到达接收FIFO （3）PMU寄存器中的URRST 位置1
4 传输保持寄存器空（THR） INT_THR_EMPTY
非FIFO模式下： THR空。 FIFO模式下，传输器FIFO空
中断清除方式：一个字节被写到 THR
*/
void UART0_Handler(void) {
uint8_t rev_data = 0;
NVIC_ClearPendingIRQ(UART0_IRQn);
//接收线中断 有错误或者break
if(UART_INT_TYPE(CMSDK_UART0) == INT_RCV_LINE_STATUS) {
CMSDK_UART0->IER &= ~CMSDK_UART_IER_RLSI_EN_Msk;
}
//数据就绪中断
//接收超时中断
if((UART_INT_TYPE(CMSDK_UART0) == INT_RCV_DATA_AVAILABLE) || (UART_INT_TYPE(CMSDK_UART0) == INT_CHAR_TIMEOUT_INDICATION))
{
CMSDK_UART0->IER &= ~CMSDK_UART_IER_RDAI_EN_Msk;
rev_data = CMSDK_UART0->RBR;
UartPutc(CMSDK_UART0,rev_data);
CMSDK_UART0->IER |= CMSDK_UART_IER_RDAI_EN_Msk;
}
return;
}
void UART1_Handler(void) {
uint8_t rev_data = 0;
NVIC_ClearPendingIRQ(UART1_IRQn);
//接收线中断 有错误或者break
if(UART_INT_TYPE(CMSDK_UART1) == INT_RCV_LINE_STATUS) {
CMSDK_UART1->IER &= ~CMSDK_UART_IER_RLSI_EN_Msk;
}
//数据就绪中断
//接收超时中断
if((UART_INT_TYPE(CMSDK_UART1) == INT_RCV_DATA_AVAILABLE) || (UART_INT_TYPE(CMSDK_UART1) == INT_CHAR_TIMEOUT_INDICATION)) {
CMSDK_UART1->IER &= ~CMSDK_UART_IER_RDAI_EN_Msk;
rev_data = CMSDK_UART1->RBR;
UartPutc(CMSDK_UART1,rev_data);
CMSDK_UART1->IER |= CMSDK_UART_IER_RDAI_EN_Msk;
}
return;
}

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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_WATCHDOG.c
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ENS1_WATCHDOG.h"
//设置load值
void WatchDogLoad(uint32_t loadvalue_us)
{
CMSDK_WATCHDOG->LOAD = loadvalue_us * (uint8_t)(APB_Clock_Freq/1000000) ;
}
//读取watchdog 递减计数器当前值
uint32_t Read_WDOGVALUE(void)
{
return ( CMSDK_WATCHDOG->VALUE & 0xffffffff );
}
//使能看门够中断事件
void WatchDog_Control(FunctionalState newstate)
{
if(newstate == ENABLE)
{
CMSDK_WATCHDOG->CTRL |= (0x3);
}
else
{
CMSDK_WATCHDOG->CTRL &=~ (0x3);
}
}
//清除看门狗中断事件,清除后将自动重载计数值
void WatchDog_IntClear(void)
{
CMSDK_WATCHDOG->INTCLR = 1 ;
}
//解除看门狗锁寄存器或给看门狗寄存器上锁
uint8_t WatchDog_LOCK_RegSet(WdogLockState newstate)
{
if(newstate == LOCK)
{
CMSDK_WATCHDOG->LOCK = 0;
}
else
{
CMSDK_WATCHDOG->LOCK = 0x1ACCE551;
}
return (CMSDK_WATCHDOG->LOCK &0x1);
}

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/*
*Copyright (C),2023 , NANOCHAP
*File name: ENS1_ADC.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ENS1_ADC.h"
#include "ENS1_GPIO.h"
#include "ENS1_CLOCK.h"
#include "ENS1_ANAC.h"
/* 一、寄存器说明：
ADC配置：转换模式 数据覆盖模式 等待模式
ADC控制： ADC使能 ， ADC启动
ADC中断使能： EOC中断使能 数据覆盖中断使能
ADC中断状态： EOC中断发生 数据覆盖中断发生
ADC状态 ： EOC标志 ADC空闲或繁忙状态
ADC时钟分频 ：分频值 2 4 6 8 10 12 16 32
ADC采样时间 ：ADC采样时间时钟数 2 3 4 5
ADC数据：
ADC通道选择 ：
ADCEOC配置 ：在连续模式下 ， 是否在接收到EOC标志后开启下次转换
*/
/* 二、单次转换模式
*ADC控制启将 给ADC_START 位置0 当接收到EOC或者EOC_WAIT_COUNT_DONE ， 无论哪一个先到来
*如果直到EOC_WAIT_COUNT_DONE 都没有接收到EOC ，数据将不会被保存
*ADC将停止转换，通过用户设置ADC_CTRL_REG 的 ADC_EN 位 为1
*如果在采样和转换期间，ADC_EN 位置为0 ，控制器将完成正在进行的转换，然后基于 EOC/EOC_WAIT_COUNT_DONE 停止转换
*数据会在EOC 到达后锁存
ADC单次转换流程：
1、设置单次转换（无等待模式）
2、设置ADC_CONFIG_reg bit0 = 0 bit2 = 0
3、单次转换启动
4、转换结束， 数据保存至ADC_Data register
5、一个ADC_EOC_IE中断生成，
6、如果使能了 IER寄存器的 EOC_INT_EN 和OVER_RUN_INT_EN 位，则系统进入中断
7、硬件停止ADC
*/
/*三、连续转换模式
1、设置ADC_CONFIG_reg bit0 = 1
2、启动位置1 ADC_EN bit and ADC_START bits
3、在每次转换完成之后，基于adc_eoc_config_regsiter[0] 启动下次转换：
如果Adc_eoc_config_register[0] =1 ， 则接收到EOC后开始下次转换
数据保存到寄存器中
4、ADC_EOC_IE 中断生成
5、如果使能了 IER寄存器的 EOC_INT_EN 和OVER_RUN_INT_EN 位，则系统进入中断
注意：ADC_eoc_config_reg寄存器仅仅在连续采样-非等待模式下有效 即：0：连续模式不接收EOC即开始启动下一次转换
1：连续模式接收到EOC后开始启动下一次转换
在连续采样-等待模式下，ADC_eoc_config_reg应该被设置为0 ！！！
*/
/*四、等待模式
1、设置ADC_CONFIG_reg bit2 = 1 （使能等待模式）
2、启动测量转换
3、在转换完成后：
存ADC数据到相应寄存器中
ADC_EOC_IE 中断生成
如果使能了 IER寄存器的 EOC_INT_EN 和OVER_RUN_INT_EN 位，则系统进入中断
4、ADC控制器进入到ADC_WAIT 等待状态直到EOC中断被清除 或者 ADC数据被系统读走
5、一旦EOC中断被清除，ADC开始下一次的转换
*/
/*五、数据锁存器
1、当ADC控制启接收到EOC后，数据将被锁存
2、如果 OVERRUN模式被使能，新的转换数据将会被锁存 无论 overrun 错误状态如何
注意： 如果overrun 模式没有被使能， 新的或者旧的转换数据将根据overrun 错误状态选择性锁存
即： 如果overrun 错误发生，数据将不会被锁存
如果没有overrun 错误发生，新数据将被锁存
*/
/*六、中断说明
1、接收到EOC后 EOC_IR 生成
2、OVERRUN错误发生后OVERRUN_IR 生成
3、EOC_IR 和overrun 作为ADC中断被 通道到系统
在系统通过 data_reg 读取走adc数据后， EOC_IR 被 EOC_IR_CLEAR 清除
*/
/*overrun 错误
此错误指的是： ADC控制器在系统读取走ADC数据前（在清除到上一个EOC_IR前），接收到新的EOC
*/
volatile uint8_t ADC_READ_STATUS = ADC_READ_DATA_IS_WAITING;
uint8_t ADC_UART_BYTE_LOW = 0;
uint8_t ADC_UART_BYTE_HIGH = 0;
uint8_t ENS1_ADCCLKConfig(uint8_t ADC_CLK_div)
{
CMSDK_ADC->ADC_CLK_DIV = ((CMSDK_ADC->ADC_CLK_DIV &~ (0x7)) | (ADC_CLK_div));
return 0;
}
/*
ENS_ADC_COV_MODE COV_MODE
ENS_ADC_OVERRUN_MODE OVERRUN_MODE
WAIT_MODE WAITorNOT
*/
uint8_t ENS1_ADC_CONFIG(ENS_ADC_SEL channelx ,
uint8_t MODE_SEL,
ENS_ADC_COV_INC_EOC EOC_CONFIG ,
uint8_t SIMLING_TIME,
uint8_t INT_MODE_SEL)
{
NVIC_ClearPendingIRQ(ADC_IRQn);
NVIC_DisableIRQ(ADC_IRQn);
if(channelx == ENS1_ADC_CHANNEL1)
{
CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<10))|(0x03<<10);
CMSDK_GPIO->ANAEN |= (1 << 21);
CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
CMSDK_ADC->ADC_CH_SEL = 1;
}
else if(channelx == ENS1_ADC_CHANNEL2)
{
CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<12))|(0x03<<12);
CMSDK_GPIO->ANAEN |= (1 << 22);
CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
CMSDK_ADC->ADC_CH_SEL = 2;
}
else if(channelx == ENS1_ADC_CHANNEL3)
{
CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<14))|(0x03<<14);
CMSDK_GPIO->ANAEN |= (1 << 23);
CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
CMSDK_ADC->ADC_CH_SEL = 3;
}
else
{
CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
CMSDK_ADC->ADC_CH_SEL = 0;
}
CMSDK_ADC->ADC_CONFG =(CMSDK_ADC->ADC_CONFG &~ 0x7 )| MODE_SEL;
CMSDK_ADC->ADC_SAMP_TIME = (CMSDK_ADC->ADC_SAMP_TIME &~ 0x3) | SIMLING_TIME;
//配置ADC_eoc_config_reg寄存器，（仅仅在连续采样-非等待模式下有效）
if( ((MODE_SEL & 0X1 )== 1 ) && (MODE_SEL & 0X4) == 0)
{
CMSDK_ADC->ADC_EOC_CONFG = (CMSDK_ADC->ADC_EOC_CONFG &~ (0x1)) | EOC_CONFIG;
}
//中断使能
CMSDK_ADC->ADC_IER = (CMSDK_ADC->ADC_IER &~ (0x3)) | ( INT_MODE_SEL );
return CMSDK_ADC->ADC_CONFG;
}
uint8_t ENS1_ADC_START(ENS_ADC_SEL channelx )
{
CMSDK_ADC->ADC_CTRL |= (1) |(1<<8);
if(CMSDK_ADC->ADC_IER != 0)
{
NVIC_EnableIRQ(ADC_IRQn);
}
return 0;
}
uint8_t ENS1_ADC_STOP(ENS_ADC_SEL channelx)
{
CMSDK_ADC->ADC_CTRL &=~ (1);
NVIC_DisableIRQ(ADC_IRQn);
return 0;
}
//连续读取数据
//ADC在不同模式下有不同的采集方式，根据Adc_config_register的配置不同，共8种模式
uint16_t save_data;
uint8_t ADC_CONFIG_READ;
//此函数未完成，测试使用连续采集+中断模式，此函数暂时用不到
uint16_t ADC_READ_DATA(void)
{
ADC_CONFIG_READ = CMSDK_ADC->ADC_CONFG;
switch(ADC_CONFIG_READ & 0x7) {
case single_mode_without_overrun_without_wait :
while(ADC_READ_STATUS == ADC_READ_DATA_IS_WAITING); //等待在中断中EOC的到来
ADC_READ_STATUS = ADC_READ_DATA_IS_WAITING; //中断发生，已经有ADC的数据了，此时再将状态切换到等待下一次数据
break;
case continious_mode_without_overrun_without_wait :
break;
case single_mode_with_overrun_without_wait :
break;
case continious_mode_with_overrun_without_wait :
break;
case single_mode_without_overrun_with_wait :
break;
case Continious_mode_without_overun_with_wait :
break;
case single_mode_with_overrun_with_wait :
break;
case continious_mode_with_overrun_with_wait :
break;
}
return (uint16_t)save_data;
}
//ADC interrupt handler
void ADC_Handler(void) __irq
{
if((CMSDK_ADC->ADC_ISR & 0x01) == 0x01) //接收到EOC
{
CMSDK_ADC->ADC_INT_CLR = (0x01<<0);
ADC_READ_STATUS = ADC_READ_DATA_IS_READY;
save_data = (CMSDK_ADC->ADC_DATA & 0x0fff); //读走数据后，可以进行下一次采集
printf("%d\n",save_data);
ADC_UART_BYTE_LOW = save_data&0xff;
ADC_UART_BYTE_HIGH = (save_data&0x0f00)>>8;
}
if(((CMSDK_ADC->ADC_ISR & 0x02)>>1) == 0x01) //overrun error
{
CMSDK_ADC->ADC_INT_CLR = (0x01<<1);
}
}

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FWLIB/source/ENS_CURRENT_CALIBRATION.c Normal file
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/*
*Copyright ,2023 , NANOCHAP
*File name: ENS1_CURRENT_CALIBRATION.C
*Author:
*Version: V1.0
*Date: 2023-11-
*Description:
*Function List:
History:
1.V1.0
Date:
Author:
Modification: 初版
*/
#include "ENS_CURRENT_CALIBRATION.h"
#include "ENS1_MTP.h"
#include "ENS1_UART.h"
#include "ENS1_TIMER.h"
/*--------------------------------波形参数的初始化幅值结构体-----------------------------*/
STRUCT_WAVEFORM_PARA ParaSet_waveform[4] =
{
/*通道1 -- ST0 ST1 */
{
.Type = SQUARE_WAVE , //波形种类选择
.PositivePulseWidth = 100 , //正半周期脉宽-微秒
.DeadTime = 10, //死区时间-微秒
.NegativePulseWidth = 100 , //负半周期脉宽-微秒
.ClientTime = 1000 , //静默时间-微秒
.DelayOutputTime_US = 0, //延迟输出时间-微秒
.OtherWaveformPara.AlternatingFreq_HZ = 0, //交替波形频率 //
.OtherWaveformPara.TotalOutputTime_S = 0, //设置总输出时间 秒
.OtherWaveformPara.NumOfPulseGroups = 0, //脉冲群模式下的每组脉冲数量
.OtherWaveformPara.TimeOfPulseGroups_MS = 0, //脉冲群模式下的组间隔时间 毫秒
},
/*通道2 -- ST2 ST3 */
{
.Type = TRIANGULAR_WAVE , //波形种类选择
.PositivePulseWidth = 0 , //正半周期脉宽-微秒
.DeadTime = 0, //死区时间-微秒
.NegativePulseWidth = 0 , //负半周期脉宽-微秒
.ClientTime = 0 , //静默时间-微秒
.DelayOutputTime_US = 0, //延迟输出时间-微秒
.OtherWaveformPara.AlternatingFreq_HZ = 0, //交替波形频率 //
.OtherWaveformPara.TotalOutputTime_S = 0, //设置总输出时间 秒
.OtherWaveformPara.NumOfPulseGroups = 0, //脉冲群模式下的每组脉冲数量
.OtherWaveformPara.TimeOfPulseGroups_MS = 0, //脉冲群模式下的组间隔时间 毫秒
},
/*通道3 -- ST4 ST5 */
{
.Type = TRIANGULAR_WAVE , //波形种类选择
.PositivePulseWidth = 0 , //正半周期脉宽-微秒
.DeadTime = 0, //死区时间-微秒
.NegativePulseWidth = 0 , //负半周期脉宽-微秒
.ClientTime = 0 , //静默时间-微秒
.DelayOutputTime_US = 0, //延迟输出时间-微秒
.OtherWaveformPara.AlternatingFreq_HZ = 0, //交替波形频率 //
.OtherWaveformPara.TotalOutputTime_S = 0, //设置总输出时间 秒
.OtherWaveformPara.NumOfPulseGroups = 0, //脉冲群模式下的每组脉冲数量
.OtherWaveformPara.TimeOfPulseGroups_MS = 0, //脉冲群模式下的组间隔时间 毫秒
},
/*通道4 -- ST6 ST7 */
{
.Type = TRIANGULAR_WAVE , //波形种类选择
.PositivePulseWidth = 0 , //正半周期脉宽-微秒
.DeadTime = 0, //死区时间-微秒
.NegativePulseWidth = 0 , //负半周期脉宽-微秒
.ClientTime = 0 , //静默时间-微秒
.DelayOutputTime_US = 0, //延迟输出时间-微秒
.OtherWaveformPara.AlternatingFreq_HZ = 0, //交替波形频率 //
.OtherWaveformPara.TotalOutputTime_S = 0, //设置总输出时间 秒
.OtherWaveformPara.NumOfPulseGroups = 0, //脉冲群模式下的每组脉冲数量
.OtherWaveformPara.TimeOfPulseGroups_MS = 0, //脉冲群模式下的组间隔时间 毫秒
},
};
/*-------------------------------------------------------------------------------------*/
/*-------------------------获取到FT测试后的实际测量单元电流值---------------------------*/
uint16_t FT_CURRENT_SAVE[4]={0,0,0,0}; //用于保存FT读取出的数据
uint8_t CUSTOM_UNIT_CURRENT[4]={33,33,33,33}; //用于自定义单元电流值
uint8_t unit_current[4] ={0,0,0,0}; //保存计算好的实际单元电流值
uint8_t GET_FT_CURRENT(void) //电流设置：208*4
{
//当需要使用FT后的芯片时，打开注释， 此时自动计算单元电流
//当手动校准时，修改CUSTOM_UNIT_CURRENT[4] 数组中的数据，并将下面4行注释掉
// flash_read(DATA_SAVE_ADDR ,&FT_CURRENT_SAVE[0]);//读出保存在MTP中的实际检测电流值用于计算实际单元电流
// flash_read(DATA_SAVE_ADDR+2 ,&FT_CURRENT_SAVE[1]);//读出保存在MTP中的实际检测电流值用于计算实际单元电流
// flash_read(DATA_SAVE_ADDR+4 ,&FT_CURRENT_SAVE[2]);//读出保存在MTP中的实际检测电流值用于计算实际单元电流
// flash_read(DATA_SAVE_ADDR+6 ,&FT_CURRENT_SAVE[3]);//读出保存在MTP中的实际检测电流值用于计算实际单元电流
for(int i = 0 ;i<4;i++)
{
if(FT_CURRENT_SAVE[i] != 0)
unit_current[i] = (uint8_t)(FT_CURRENT_SAVE[i] /( 208 * 4 )) ; //计算实际单元电流
else
unit_current[i] = CUSTOM_UNIT_CURRENT[i] ;
}
return 0;
}
/*-------------------------------------输出电流大小设置--------------------------------*/
//正弦波计算数据填充值
double sin_cal(uint8_t angle) //0-180
{
double radian = angle*PI/180;
return sin(radian);
}
//计算不同波形下的的64个点的值，当前有方波，正弦波，三角波
uint16_t unit_t[4]; //保存计算后的单元电流系数（0-7） 共四个通道
uint32_t isel_t[4][64]; //保存计算后得到的电流挡位（0-255）共四个通道
BasicWaveformType wavePara_type[4];
uint8_t cal_output_current_mA(CHANNEL_NUM CHANNEL_X,float mA,BasicWaveformType type, uint16_t* unit , uint32_t (*isel)[64]) // uint16_t read_current_data
{
CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK;
if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0;
else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1;
else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2;
else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3;
if(!mA)
{
for(uint8_t i = 0 ;i<4;i++){
unit_t[i] = 0;
for(uint8_t j = 0;j<64;j++)
{
isel_t[i][j] = 0;
}
}
}
else
{
if(type == SQUARE_WAVE)
{
//保存计算结果,用于给电流相关的寄存器赋值
*(unit+CHANNEL_X) = (uint16_t)(mA * 1000 / (unit_current[CHANNEL_X] * 255)); // 0 - 7
for(int i = 0 ;i<64;i++)
{
*(isel[0]+CHANNEL_X*64+i) = (uint16_t)(mA * 1000 / ((*(unit+CHANNEL_X)+1)*unit_current[CHANNEL_X])); // 0 - 255
}
}
else if(type== SINE_WAVE)
{
//保存计算结果,用于给电流相关的寄存器赋值
*(unit+CHANNEL_X) = (uint16_t)(mA * 1000 / (unit_current[CHANNEL_X] * 255)); // 0 - 7
for(int i = 0 ;i<64;i++)
{
*(isel[0]+CHANNEL_X*64+i) = (uint16_t)(mA * 1000 / ((*(unit+CHANNEL_X) + 1)*unit_current[CHANNEL_X])*sin_cal(i*2.85714)); // 0 - 255
}
}
else //三角波赋值(type == TRIANGULAR_WAVE )
{
//保存计算结果,用于给电流相关的寄存器赋值
*(unit+CHANNEL_X) = (uint16_t)(mA * 1000 / (unit_current[CHANNEL_X] * 255)); // 0 - 7
*(isel[0]+CHANNEL_X*64) = 0;
*(isel[0]+CHANNEL_X*64+63) = 0;
for(int j = 1 ; j<32 ; j++)
{
*(isel[0]+CHANNEL_X*64+j) = (uint16_t)(mA * 1000 / ((*(unit+CHANNEL_X)+1)*unit_current[CHANNEL_X]) * 0.033258*j); // 0 - 255
// printf("%d\n",*(isel[0]+CHANNEL_X*64+j));
}
for(int k = 32 ; k<63 ; k++)
{
*(isel[0]+CHANNEL_X*64+k) =*(isel[0]+CHANNEL_X*64+(63-k)) ;
// printf("%d\n",*(isel[0]+CHANNEL_X*64+k));
}
}
}
return 0;
}
/*初始化设置*/
/*CONFIG寄存器设置*/
uint8_t ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_NUM CHANNEL_X , DRV_CONFIG BIT)
{
CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK;
if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0;
else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1;
else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2;
else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3;
if(BIT == DISABLE_ALL_BIT)
{
WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG = 0x00;
return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ;
}
if(BIT == ENABLE_ALL_BIT)
{
WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG = ENABLE_ALL_BIT;
return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ;
}
if((BIT != DISABLE_ALL_BIT) && (BIT != ENABLE_ALL_BIT))
{
WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG |= BIT;
}
return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ;
}
uint8_t ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_NUM CHANNEL_X , DRV_CONFIG BIT)
{
CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK;
if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0;
else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1;
else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2;
else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3;
if(BIT == DISABLE_ALL_BIT)
{
WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG = 0x00;
return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ;
}
if(BIT == ENABLE_ALL_BIT)
{
WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG = ENABLE_ALL_BIT;
return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ;
}
if((BIT != DISABLE_ALL_BIT) && (BIT != ENABLE_ALL_BIT))
{
WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG &=~ BIT;
}
return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ;
}
/*---------------------------电刺激有关的寄存器的初始化--------------------------------*/
uint32_t StimulatorInit(CHANNEL_NUM CHANNEL_X)
{
//uint32_t WaveformFreq=0;
CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK;
if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0;
else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1;
else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2;
else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3;
//config 设置
ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,DISABLE_ALL_BIT);
//1 、 死区时间不为0，波形不为sine波 ,使能REST
if((ParaSet_waveform[CHANNEL_X].DeadTime > 0)){
ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,REST_BIT);
}
else
{
ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,REST_BIT);
}
//2 、 负半周期脉宽大于0 使能 NEGATIVE_BIT 和 SOURCE_B_BIT
if(ParaSet_waveform[CHANNEL_X].NegativePulseWidth > 0)
{
ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,SOURCE_B_BIT ); //SOURCEB不使能则负半周期的数据无效（=0）
ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,NEGATIVE_BIT );
}
//3、静默时间不为0，开启SILENT_BIT
if(ParaSet_waveform[CHANNEL_X].ClientTime>0)
{
ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,SILENT_BIT);
}
else
{
ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,SILENT_BIT);
}
//4、交替模式ALTERNATING_POSITIVE_BIT
if(ParaSet_waveform[CHANNEL_X].OtherWaveformPara.AlternatingFreq_HZ > 0 )
{
ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,ALTERNATING_POSITIVE_BIT);
ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,SOURCE_B_BIT);
ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,NEGATIVE_BIT);
//交替时间与主频有关,输入的参数为交替频率，需要转化为时钟个数，时钟个数不能超过2^16
WAVE_GEN_BLK ->WAVE_GEN_DRV_ALT_LIM_REG =(uint16_t)(ParaSet_waveform[CHANNEL_X].PositivePulseWidth / (uint16_t)ParaSet_waveform[CHANNEL_X].OtherWaveformPara.AlternatingFreq_HZ * (uint16_t)(APB_Clock_Freq/1000000)) ;
ParaSet_waveform[CHANNEL_X].NegativePulseWidth = 0;
}
else
{
ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,ALTERNATING_POSITIVE_BIT);
}
ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,CONTINUE_REPEATING_BIT);
//延迟输出时间计算 单位us
WAVE_GEN_BLK->WAVE_GEN_DRV_DELAY_LIM_REG = (uint8_t)(APB_Clock_Freq/1000000)*ParaSet_waveform[CHANNEL_X].DelayOutputTime_US;
//根据初始化后的STRUCT_WAVEFORM_PARA结构体给对应的寄存器赋值
WAVE_GEN_BLK->WAVE_GEN_DRV_NEG_HLF_WAVE_PRD_REG = ParaSet_waveform[CHANNEL_X].NegativePulseWidth;
WAVE_GEN_BLK->WAVE_GEN_DRV_HLF_WAVE_PRD_REG = ParaSet_waveform[CHANNEL_X].PositivePulseWidth;
WAVE_GEN_BLK->WAVE_GEN_DRV_CLK_FREQ_REG = (uint32_t)(APB_Clock_Freq/1000000); //
WAVE_GEN_BLK->WAVE_GEN_DRV_SILENT_T_REG = ParaSet_waveform[CHANNEL_X].ClientTime;
WAVE_GEN_BLK->WAVE_GEN_DRV_REST_T_REG = ParaSet_waveform[CHANNEL_X].DeadTime;
WAVE_GEN_BLK->WAVE_GEN_DRV_NEG_SCALE_REG = 1; //寄存器默认为0， 必须写大于0的数
WAVE_GEN_BLK->WAVE_GEN_DRV_NEG_OFFSET_REG = 0;
//WaveformFreq = (uint32_t)(1000000 / (wavePara.ClientTime + wavePara.DeadTime +wavePara.NegativePulseWidth + wavePara.PositivePulseWidth));
//保存波形类型数据
wavePara_type[CHANNEL_X] = ParaSet_waveform[CHANNEL_X].Type;
TOTAL_TIME_THRESHOLD_VALUE[CHANNEL_X] = ParaSet_waveform[CHANNEL_X].OtherWaveformPara.TotalOutputTime_S * 1000;
if( (ParaSet_waveform[CHANNEL_X].OtherWaveformPara.TimeOfPulseGroups_MS > 0) || (ParaSet_waveform[CHANNEL_X].OtherWaveformPara.NumOfPulseGroups >0))
{
TRIGGER_TIME_COUNT[CHANNEL_X] = 0; //间隔时间清零
TRIGGER_TIME_THRESHOLD_VALUE[CHANNEL_X]=ParaSet_waveform[CHANNEL_X].OtherWaveformPara.TimeOfPulseGroups_MS ;
NUM_OF_PULSES_THRESHOLD[CHANNEL_X] = ParaSet_waveform[CHANNEL_X].OtherWaveformPara.NumOfPulseGroups ;
WAVE_GEN_BLK->WAVE_GEN_DRV_INT_REG = 0x001f0001;
}
uint8_t returnValue = cal_output_current_mA(CHANNEL_X,0, wavePara_type[CHANNEL_X], unit_t , isel_t) ;
return (uint32_t)(WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG); //返回波形的频率
}
/*--------------------------------------启动输出-----------------------------------------*/
volatile uint8_t statics_config=0; //明确当前有几个通道在输出 0 / 1 / 2 /4 / 8
void StartStimulatorOut(CHANNEL_NUM CHANNEL_X)
{
CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK;
if(CHANNEL_X == CHANNEL_0) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; statics_config |= (1<<0); }
else if(CHANNEL_X == CHANNEL_1) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; statics_config |= (1<<1);}
else if(CHANNEL_X == CHANNEL_2) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; statics_config |= (1<<2);}
else {WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; statics_config |= (1<<3) ;}
if(statics_config > 1)
{
ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,MULTI_ELECTRODE_BIT); //多电极使能
}
WAVE_GEN_BLK->WAVE_GEN_DRV_CTRL_REG = 1;
}
/*--------------------------------------停止输出----------------------------------------*/
void StopStimulatorOut(CHANNEL_NUM CHANNEL_X)
{
CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK;
if(CHANNEL_X == CHANNEL_0) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; statics_config &=~(1<<0); }
else if(CHANNEL_X == CHANNEL_1) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; statics_config &=~(1<<1); }
else if(CHANNEL_X == CHANNEL_2) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; statics_config &=~(1<<2); }
else {WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; statics_config &=~(1<<3); }
WAVE_GEN_BLK->WAVE_GEN_DRV_CTRL_REG = 0;
if(statics_config < 2)
{
ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,MULTI_ELECTRODE_BIT);
}
}
/*-----------------------------电刺激过程中的电流、频率设置-------------------------------*/
/*输出电流大小修改*/
uint8_t CURRENT_AMPLITUDE_MODIFY(CHANNEL_NUM CHANNEL_X , float mA)
{
CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK;
if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0;
else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1;
else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2;
else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3;
NVIC_DisableIRQ(WG_DRV_IRQn);
WAVE_GEN_BLK->WAVE_GEN_DRV_INT_REG = 0;
StopStimulatorOut(CHANNEL_X);
cal_output_current_mA(CHANNEL_X,mA, wavePara_type[CHANNEL_X], unit_t , isel_t) ;
WAVE_GEN_BLK ->WAVE_GEN_DRV_ISEL_REG = unit_t[CHANNEL_X]; //范围 0x00 - 0x07 单元电流
for(int i=0; i<64; i++){
WAVE_GEN_BLK->WAVE_GEN_DRV_IN_WAVE_ADDR_REG = i;
WAVE_GEN_BLK->WAVE_GEN_DRV_IN_WAVE_REG = isel_t[CHANNEL_X][i]; //最大0xff 电流挡位
}
WAVE_GEN_BLK->WAVE_GEN_DRV_INT_REG = 0x001f0001;
NVIC_EnableIRQ(WG_DRV_IRQn);
StartStimulatorOut(CHANNEL_X);
return (uint8_t)(WAVE_GEN_BLK->WAVE_GEN_DRV_CTRL_REG); //返回状态
}
/*输出波形频率的实时修改，输出时，波形频率=(1000000/(正半周期脉宽 + 负半周期脉宽 + 死区时间 + 静默时间))*/
uint32_t CURRENT_FREQ_MODIFY(CHANNEL_NUM CHANNEL_X , uint32_t freq)
{
uint32_t Pulse_Width = 0;
CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK;
if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0;
else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1;
else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2;
else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3;
if(freq > 50000 )
freq = 50000;
else if(freq < 10)
freq = 10;
//死区数值不改动，如果静默时间不为0 ，则通过修改静默时间修改波形频率 ，如果静默时间为0，则修改正半周期/负半周期脉宽修改频率
if(ParaSet_waveform[CHANNEL_X].ClientTime > 0)
{
Pulse_Width/*静默时间*/ = (uint32_t)((1000000/freq) - ParaSet_waveform[CHANNEL_X].DeadTime - ParaSet_waveform[CHANNEL_X].PositivePulseWidth - ParaSet_waveform[CHANNEL_X].NegativePulseWidth);
WAVE_GEN_BLK->WAVE_GEN_DRV_SILENT_T_REG = Pulse_Width;
return Pulse_Width;
}
else if(ParaSet_waveform[CHANNEL_X].ClientTime == 0)
{
Pulse_Width/*正+负脉宽*/ = (uint32_t)((1000000/freq) - ParaSet_waveform[CHANNEL_X].DeadTime) ;
if(ParaSet_waveform[CHANNEL_X].NegativePulseWidth == 0)
WAVE_GEN_BLK->WAVE_GEN_DRV_HLF_WAVE_PRD_REG = Pulse_Width;
else
{
WAVE_GEN_BLK->WAVE_GEN_DRV_HLF_WAVE_PRD_REG = (uint32_t) (Pulse_Width / 2) ;
WAVE_GEN_BLK->WAVE_GEN_DRV_NEG_HLF_WAVE_PRD_REG = (uint32_t) (Pulse_Width / 2) ;
}
return Pulse_Width;
}
else
{
return 0;
}
}
//电刺激时间计时
uint32_t StimuTimeCount_S(CHANNEL_NUM CHANNEL_X , TIME_COUNT_MODE MODE)
{
uint32_t count_time = 0;
if(MODE == TOTAL_TIME_MODE)
{
count_time = *(CHANNEL_TIME_COUNT+CHANNEL_X) ;
}
else //MODE == TRIGGER_TIME_MODE 间隔时间
{
count_time = *(TRIGGER_TIME_COUNT+CHANNEL_X);
}
return count_time;
}
//返回当前波形发生了多少次（需要开启波形发生器的中断）
uint32_t waveformOccurreCount(CHANNEL_NUM CHANNEL_X)
{
return (uint32_t)(wave_gen_irq_occurred[CHANNEL_X]/4);
}
/*-------------------------------电刺激驱动器中断处理函数-----------------------*/
volatile uint32_t NUM_OF_PULSES_THRESHOLD[4]={0,0,0,0};
volatile uint32_t wave_gen_irq_occurred[4]={0,0,0,0};
void WG_DRV_Handler(void)
{
CMSDK_WAVE_GEN_TypeDef *DRVA;
for(int i =0; i<4;i++)
{
if(i==0){ DRVA= WAVE_GEN_DRVA_BLK0; }
else if(i==1){ DRVA= WAVE_GEN_DRVA_BLK1; }
else if(i==2){ DRVA= WAVE_GEN_DRVA_BLK2; }
else if(i==3){ DRVA= WAVE_GEN_DRVA_BLK3; }
if((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_READ_DRIVER_NUM_Msk) == i) //判断哪个通道发生了中断
{
if((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_STS_Msk) == CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_STS_Msk)//第一中断点发生中断
{
if(((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Msk)>>CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Pos) == 0)
{
if((NUM_OF_PULSES_THRESHOLD[i] > 0) && (wave_gen_irq_occurred[i] > (NUM_OF_PULSES_THRESHOLD[i]*4 - 2)))
DRVA->WAVE_GEN_DRV_INT_REG = (63 << CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Pos) | (0 << CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Pos) | CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Msk | CMSDK_WAVE_GEN_DRV_INT_EN_Msk;
else
DRVA->WAVE_GEN_DRV_INT_REG = (63 << CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Pos) | (32 << CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Pos) | CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Msk | CMSDK_WAVE_GEN_DRV_INT_EN_Msk;
}
else if(((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Msk)>>CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Pos) == 32)
{
DRVA->WAVE_GEN_DRV_INT_REG = (31 << CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Pos) | (0 << CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Pos) | CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Msk | CMSDK_WAVE_GEN_DRV_INT_EN_Msk;
}
if((NUM_OF_PULSES_THRESHOLD[i] > 0)) //需要脉冲计数功能才开启计数
wave_gen_irq_occurred[i]++;
}
if((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_STS_Msk) == CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_STS_Msk)
{
StopStimulatorOut((CHANNEL_NUM)i);
DRVA->WAVE_GEN_DRV_INT_REG = CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_CLR_Msk | CMSDK_WAVE_GEN_DRV_INT_EN_Msk;
NVIC_DisableIRQ(WG_DRV_IRQn);
DRVA->WAVE_GEN_DRV_INT_REG = 0;
TRIGGER_TIME_COUNT_FLAG |= (1<<i); //脉冲群标志置1
wave_gen_irq_occurred[i] = 0; //清零计数
}
}
}
}

83
FWLIB/source/retarget.c Normal file
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@ -0,0 +1,83 @@
/*
*-----------------------------------------------------------------------------
* The confidential and proprietary information contained in this file may
* only be used by a person authorised under and to the extent permitted
* by a subsisting licensing agreement from Arm Limited or its affiliates.
*
* (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
* ALL RIGHTS RESERVED
*
* This entire notice must be reproduced on all copies of this file
* and copies of this file may only be made by a person if such person is
* permitted to do so under the terms of a subsisting license agreement
* from Arm Limited or its affiliates.
*
* SVN Information
*
* Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
*
* Revision : $Revision: 371321 $
*
* Release Information : Cortex-M System Design Kit-r1p1-00rel0
*-----------------------------------------------------------------------------
*/
#if defined ( __CC_ARM )
/******************************************************************************/
/* Retarget functions for ARM DS-5 Professional / Keil MDK */
/******************************************************************************/
#include <stdio.h>
#include <time.h>
#include <rt_misc.h>
#include "CMSDK_CM0.h"
#pragma import(__use_no_semihosting_swi)
//extern unsigned char UartGetc(void);
extern unsigned char UartPutc(CMSDK_UART_TypeDef *CMSDK_UART ,unsigned char my_ch);
struct __FILE { int handle; /* Add whatever you need here */ };
FILE __stdout;
FILE __stdin;
int fputc(int ch, FILE *f) {
return (UartPutc(CMSDK_UART1 ,ch));
}
int ferror(FILE *f) {
/* Your implementation of ferror */
return EOF;
}
void _ttywrch(int ch) {
UartPutc (CMSDK_UART1 ,ch);
}
void _sys_exit(int return_code) {
label: goto label; /* endless loop */
}
#else
/******************************************************************************/
/* Retarget functions for GNU Tools for ARM Embedded Processors */
/******************************************************************************/
#include <stdio.h>
#include <sys/stat.h>
extern unsigned char UartPutc(unsigned char my_ch);
__attribute__ ((used)) int _write (int fd, char *ptr, int len)
{
size_t i;
for (i=0; i<len;i++) {
UartPutc(ptr[i]); // call character output function
}
return len;
}
#endif

2206
JLinkLog.txt Normal file
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39
JLinkSettings.ini Normal file
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@ -0,0 +1,39 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

1109
Listings/ENS001_BASIC_PRJ.map Normal file
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883
Listings/startup_armcm0.lst Normal file
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@ -0,0 +1,883 @@
ARM Macro Assembler Page 1
1 00000000 ;/******************************************************
********************//**
2 00000000 ; * @file startup_ARMCM0.s
3 00000000 ; * @brief CMSIS Core Device Startup File for
4 00000000 ; * ARMCM0 Device Series
5 00000000 ; * @version V1.08
6 00000000 ; * @date 23. November 2012
7 00000000 ; *
8 00000000 ; * @note
9 00000000 ; *
10 00000000 ; ******************************************************
************************/
11 00000000 ;/* Copyright (c) 2011 - 2012 ARM LIMITED
12 00000000 ;
13 00000000 ; All rights reserved.
14 00000000 ; Redistribution and use in source and binary forms, w
ith or without
15 00000000 ; modification, are permitted provided that the follow
ing conditions are met:
16 00000000 ; - Redistributions of source code must retain the abo
ve copyright
17 00000000 ; notice, this list of conditions and the following
disclaimer.
18 00000000 ; - Redistributions in binary form must reproduce the
above copyright
19 00000000 ; notice, this list of conditions and the following
disclaimer in the
20 00000000 ; documentation and/or other materials provided with
the distribution.
21 00000000 ; - Neither the name of ARM nor the names of its contr
ibutors may be used
22 00000000 ; to endorse or promote products derived from this s
oftware without
23 00000000 ; specific prior written permission.
24 00000000 ; *
25 00000000 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS A
ND CONTRIBUTORS "AS IS"
26 00000000 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BU
T NOT LIMITED TO, THE
27 00000000 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FO
R A PARTICULAR PURPOSE
28 00000000 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS
AND CONTRIBUTORS BE
29 00000000 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL
, EXEMPLARY, OR
30 00000000 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO
, PROCUREMENT OF
31 00000000 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS
32 00000000 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LI
ABILITY, WHETHER IN
33 00000000 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLI
GENCE OR OTHERWISE)
34 00000000 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE
35 00000000 ; POSSIBILITY OF SUCH DAMAGE.
36 00000000 ; ----------------------------------------------------
-----------------------*/
37 00000000 ;/*
ARM Macro Assembler Page 2
38 00000000 ;//-------- <<< Use Configuration Wizard in Context Menu
>>> ------------------
39 00000000 ;*/
40 00000000
41 00000000
42 00000000 ; <h> Stack Configuration
43 00000000 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
44 00000000 ; </h>
45 00000000
46 00000000 00000400
Stack_Size
EQU 0x00000400
47 00000000
48 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
=3
49 00000000 Stack_Mem
SPACE Stack_Size
50 00000400 __initial_sp
51 00000400
52 00000400
53 00000400 ; <h> Heap Configuration
54 00000400 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
55 00000400 ; </h>
56 00000400
57 00000400 00000C00
Heap_Size
EQU 0x00000C00
58 00000400
59 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
3
60 00000000 __heap_base
61 00000000 Heap_Mem
SPACE Heap_Size
62 00000C00 __heap_limit
63 00000C00
64 00000C00
65 00000C00 PRESERVE8
66 00000C00 THUMB
67 00000C00
68 00000C00
69 00000C00 ; Vector Table Mapped to Address 0 at Reset
70 00000C00
71 00000C00 AREA RESET, DATA, READONLY
72 00000000 EXPORT __Vectors
73 00000000 EXPORT __Vectors_End
74 00000000 EXPORT __Vectors_Size
75 00000000
76 00000000 00000000
__Vectors
DCD __initial_sp ; Top of Stack
77 00000004 00000000 DCD Reset_Handler ; Reset Handler
78 00000008 00000000 DCD NMI_Handler ; NMI Handler
79 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
Handler
80 00000010 00000000 DCD 0 ; Reserved
81 00000014 00000000 DCD 0 ; Reserved
82 00000018 00000000 DCD 0 ; Reserved
83 0000001C 00000000 DCD 0 ; Reserved
84 00000020 00000000 DCD 0 ; Reserved
ARM Macro Assembler Page 3
85 00000024 00000000 DCD 0 ; Reserved
86 00000028 00000000 DCD 0 ; Reserved
87 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
88 00000030 00000000 DCD 0 ; Reserved
89 00000034 00000000 DCD 0 ; Reserved
90 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
91 0000003C 00000000 DCD SysTick_Handler
; SysTick Handler
92 00000040
93 00000040 ; External Interrupts
94 00000040 00000000 DCD WDT_IRQHandler ; 0: Watchdog
Timer
95 00000044 00000000 DCD RTC_IRQHandler ; 1: Real Time
Clock
96 00000048 00000000 DCD TIM0_IRQHandler ; 2: Timer0 /
Timer1
97 0000004C 00000000 DCD TIM2_IRQHandler ; 3: Timer2 /
Timer3
98 00000050 00000000 DCD MCIA_IRQHandler ; 4: MCIa
99 00000054 00000000 DCD MCIB_IRQHandler ; 5: MCIb
100 00000058 00000000 DCD UART0_IRQHandler ; 6: UART0 -
DUT FPGA
101 0000005C 00000000 DCD UART1_IRQHandler ; 7: UART1 -
DUT FPGA
102 00000060 00000000 DCD UART2_IRQHandler ; 8: UART2 -
DUT FPGA
103 00000064 00000000 DCD UART4_IRQHandler ; 9: UART4 -
not connected
104 00000068 00000000 DCD AACI_IRQHandler
; 10: AACI / AC97
105 0000006C 00000000 DCD CLCD_IRQHandler ; 11: CLCD Comb
ined Interrupt
106 00000070 00000000 DCD ENET_IRQHandler ; 12: Ethernet
107 00000074 00000000 DCD USBDC_IRQHandler
; 13: USB Device
108 00000078 00000000 DCD USBHC_IRQHandler ; 14: USB Host
Controller
109 0000007C 00000000 DCD CHLCD_IRQHandler
; 15: Character LCD
110 00000080 00000000 DCD FLEXRAY_IRQHandler
; 16: Flexray
111 00000084 00000000 DCD CAN_IRQHandler ; 17: CAN
112 00000088 00000000 DCD LIN_IRQHandler ; 18: LIN
113 0000008C 00000000 DCD I2C_IRQHandler
; 19: I2C ADC/DAC
114 00000090 00000000 DCD 0 ; 20: Reserved
115 00000094 00000000 DCD 0 ; 21: Reserved
116 00000098 00000000 DCD 0 ; 22: Reserved
117 0000009C 00000000 DCD 0 ; 23: Reserved
118 000000A0 00000000 DCD 0 ; 24: Reserved
119 000000A4 00000000 DCD 0 ; 25: Reserved
120 000000A8 00000000 DCD 0 ; 26: Reserved
121 000000AC 00000000 DCD 0 ; 27: Reserved
122 000000B0 00000000 DCD CPU_CLCD_IRQHandler ; 28: Reser
ved - CPU FPGA CLCD
123 000000B4 00000000 DCD 0 ; 29: Reserved - CP
ARM Macro Assembler Page 4
U FPGA
124 000000B8 00000000 DCD UART3_IRQHandler ; 30: UART3
- CPU FPGA
125 000000BC 00000000 DCD SPI_IRQHandler ; 31: SPI Touchs
creen - CPU FPGA
126 000000C0 __Vectors_End
127 000000C0
128 000000C0 000000C0
__Vectors_Size
EQU __Vectors_End - __Vectors
129 000000C0
130 000000C0 AREA |.text|, CODE, READONLY
131 00000000
132 00000000
133 00000000 ; Reset Handler
134 00000000
135 00000000 Reset_Handler
PROC
136 00000000 EXPORT Reset_Handler [WEAK
]
137 00000000 IMPORT SystemInit
138 00000000 IMPORT __main
139 00000000 4807 LDR R0, =SystemInit
140 00000002 4780 BLX R0
141 00000004 4807 LDR R0, =__main
142 00000006 4700 BX R0
143 00000008 ENDP
144 00000008
145 00000008
146 00000008 ; Dummy Exception Handlers (infinite loops which can be
modified)
147 00000008
148 00000008 NMI_Handler
PROC
149 00000008 EXPORT NMI_Handler [WEAK
]
150 00000008 E7FE B .
151 0000000A ENDP
153 0000000A HardFault_Handler
PROC
154 0000000A EXPORT HardFault_Handler [WEAK
]
155 0000000A E7FE B .
156 0000000C ENDP
157 0000000C SVC_Handler
PROC
158 0000000C EXPORT SVC_Handler [WEAK
]
159 0000000C E7FE B .
160 0000000E ENDP
161 0000000E PendSV_Handler
PROC
162 0000000E EXPORT PendSV_Handler [WEAK
]
163 0000000E E7FE B .
164 00000010 ENDP
165 00000010 SysTick_Handler
PROC
166 00000010 EXPORT SysTick_Handler [WEAK
ARM Macro Assembler Page 5
]
167 00000010 E7FE B .
168 00000012 ENDP
169 00000012
170 00000012 Default_Handler
PROC
171 00000012
172 00000012 EXPORT WDT_IRQHandler [WEAK
]
173 00000012 EXPORT RTC_IRQHandler [WEAK
]
174 00000012 EXPORT TIM0_IRQHandler [WEAK
]
175 00000012 EXPORT TIM2_IRQHandler [WEAK
]
176 00000012 EXPORT MCIA_IRQHandler [WEAK
]
177 00000012 EXPORT MCIB_IRQHandler [WEAK
]
178 00000012 EXPORT UART0_IRQHandler [WEAK
]
179 00000012 EXPORT UART1_IRQHandler [WEAK
]
180 00000012 EXPORT UART2_IRQHandler [WEAK
]
181 00000012 EXPORT UART3_IRQHandler [WEAK
]
182 00000012 EXPORT UART4_IRQHandler [WEAK
]
183 00000012 EXPORT AACI_IRQHandler [WEAK
]
184 00000012 EXPORT CLCD_IRQHandler [WEAK
]
185 00000012 EXPORT ENET_IRQHandler [WEAK
]
186 00000012 EXPORT USBDC_IRQHandler [WEAK
]
187 00000012 EXPORT USBHC_IRQHandler [WEAK
]
188 00000012 EXPORT CHLCD_IRQHandler [WEAK
]
189 00000012 EXPORT FLEXRAY_IRQHandler [WEAK
]
190 00000012 EXPORT CAN_IRQHandler [WEAK
]
191 00000012 EXPORT LIN_IRQHandler [WEAK
]
192 00000012 EXPORT I2C_IRQHandler [WEAK
]
193 00000012 EXPORT CPU_CLCD_IRQHandler [WEAK
]
194 00000012 EXPORT SPI_IRQHandler [WEAK
]
195 00000012
196 00000012 WDT_IRQHandler
197 00000012 RTC_IRQHandler
198 00000012 TIM0_IRQHandler
199 00000012 TIM2_IRQHandler
200 00000012 MCIA_IRQHandler
ARM Macro Assembler Page 6
201 00000012 MCIB_IRQHandler
202 00000012 UART0_IRQHandler
203 00000012 UART1_IRQHandler
204 00000012 UART2_IRQHandler
205 00000012 UART3_IRQHandler
206 00000012 UART4_IRQHandler
207 00000012 AACI_IRQHandler
208 00000012 CLCD_IRQHandler
209 00000012 ENET_IRQHandler
210 00000012 USBDC_IRQHandler
211 00000012 USBHC_IRQHandler
212 00000012 CHLCD_IRQHandler
213 00000012 FLEXRAY_IRQHandler
214 00000012 CAN_IRQHandler
215 00000012 LIN_IRQHandler
216 00000012 I2C_IRQHandler
217 00000012 CPU_CLCD_IRQHandler
218 00000012 SPI_IRQHandler
219 00000012 E7FE B .
220 00000014
221 00000014 ENDP
222 00000014
223 00000014
224 00000014 ALIGN
225 00000014
226 00000014
227 00000014 ; User Initial Stack & Heap
228 00000014
229 00000014 IF :DEF:__MICROLIB
236 00000014
237 00000014 IMPORT __use_two_region_memory
238 00000014 EXPORT __user_initial_stackheap
239 00000014
240 00000014 __user_initial_stackheap
PROC
241 00000014 4804 LDR R0, = Heap_Mem
242 00000016 4905 LDR R1, =(Stack_Mem + Stack_Size)
243 00000018 4A05 LDR R2, = (Heap_Mem + Heap_Size)
244 0000001A 4B06 LDR R3, = Stack_Mem
245 0000001C 4770 BX LR
246 0000001E ENDP
247 0000001E
248 0000001E 00 00 ALIGN
249 00000020
250 00000020 ENDIF
251 00000020
252 00000020
253 00000020 END
00000000
00000000
00000000
00000400
00000C00
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw
ork --depend=.\objects\startup_armcm0.d -o.\objects\startup_armcm0.o -IC:\Users
\admin\Desktop\---工作中---\0、重要内容：ENS驱动开发\程序\RTE\_ENS001_BASIC_PRJ
-IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.0\Device\ARM\ARMCM0\Include -IC:\Keil_v5\A
RM\CMSIS\Include --predefine="__UVISION_VERSION SETA 522" --predefine="ARMCM0 S
ARM Macro Assembler Page 7
ETA 1" --list=.\listings\startup_armcm0.lst CORE\startup_ARMCM0.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
STACK 00000000
Symbol: STACK
Definitions
At line 48 in file CORE\startup_ARMCM0.s
Uses
None
Comment: STACK unused
Stack_Mem 00000000
Symbol: Stack_Mem
Definitions
At line 49 in file CORE\startup_ARMCM0.s
Uses
At line 242 in file CORE\startup_ARMCM0.s
At line 244 in file CORE\startup_ARMCM0.s
__initial_sp 00000400
Symbol: __initial_sp
Definitions
At line 50 in file CORE\startup_ARMCM0.s
Uses
At line 76 in file CORE\startup_ARMCM0.s
Comment: __initial_sp used once
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
HEAP 00000000
Symbol: HEAP
Definitions
At line 59 in file CORE\startup_ARMCM0.s
Uses
None
Comment: HEAP unused
Heap_Mem 00000000
Symbol: Heap_Mem
Definitions
At line 61 in file CORE\startup_ARMCM0.s
Uses
At line 241 in file CORE\startup_ARMCM0.s
At line 243 in file CORE\startup_ARMCM0.s
__heap_base 00000000
Symbol: __heap_base
Definitions
At line 60 in file CORE\startup_ARMCM0.s
Uses
None
Comment: __heap_base unused
__heap_limit 00000C00
Symbol: __heap_limit
Definitions
At line 62 in file CORE\startup_ARMCM0.s
Uses
None
Comment: __heap_limit unused
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
RESET 00000000
Symbol: RESET
Definitions
At line 71 in file CORE\startup_ARMCM0.s
Uses
None
Comment: RESET unused
__Vectors 00000000
Symbol: __Vectors
Definitions
At line 76 in file CORE\startup_ARMCM0.s
Uses
At line 72 in file CORE\startup_ARMCM0.s
At line 128 in file CORE\startup_ARMCM0.s
__Vectors_End 000000C0
Symbol: __Vectors_End
Definitions
At line 126 in file CORE\startup_ARMCM0.s
Uses
At line 73 in file CORE\startup_ARMCM0.s
At line 128 in file CORE\startup_ARMCM0.s
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 130 in file CORE\startup_ARMCM0.s
Uses
None
Comment: .text unused
AACI_IRQHandler 00000012
Symbol: AACI_IRQHandler
Definitions
At line 207 in file CORE\startup_ARMCM0.s
Uses
At line 104 in file CORE\startup_ARMCM0.s
At line 183 in file CORE\startup_ARMCM0.s
CAN_IRQHandler 00000012
Symbol: CAN_IRQHandler
Definitions
At line 214 in file CORE\startup_ARMCM0.s
Uses
At line 111 in file CORE\startup_ARMCM0.s
At line 190 in file CORE\startup_ARMCM0.s
CHLCD_IRQHandler 00000012
Symbol: CHLCD_IRQHandler
Definitions
At line 212 in file CORE\startup_ARMCM0.s
Uses
At line 109 in file CORE\startup_ARMCM0.s
At line 188 in file CORE\startup_ARMCM0.s
CLCD_IRQHandler 00000012
Symbol: CLCD_IRQHandler
Definitions
At line 208 in file CORE\startup_ARMCM0.s
Uses
At line 105 in file CORE\startup_ARMCM0.s
At line 184 in file CORE\startup_ARMCM0.s
CPU_CLCD_IRQHandler 00000012
Symbol: CPU_CLCD_IRQHandler
Definitions
At line 217 in file CORE\startup_ARMCM0.s
Uses
At line 122 in file CORE\startup_ARMCM0.s
At line 193 in file CORE\startup_ARMCM0.s
Default_Handler 00000012
Symbol: Default_Handler
Definitions
At line 170 in file CORE\startup_ARMCM0.s
Uses
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
None
Comment: Default_Handler unused
ENET_IRQHandler 00000012
Symbol: ENET_IRQHandler
Definitions
At line 209 in file CORE\startup_ARMCM0.s
Uses
At line 106 in file CORE\startup_ARMCM0.s
At line 185 in file CORE\startup_ARMCM0.s
FLEXRAY_IRQHandler 00000012
Symbol: FLEXRAY_IRQHandler
Definitions
At line 213 in file CORE\startup_ARMCM0.s
Uses
At line 110 in file CORE\startup_ARMCM0.s
At line 189 in file CORE\startup_ARMCM0.s
HardFault_Handler 0000000A
Symbol: HardFault_Handler
Definitions
At line 153 in file CORE\startup_ARMCM0.s
Uses
At line 79 in file CORE\startup_ARMCM0.s
At line 154 in file CORE\startup_ARMCM0.s
I2C_IRQHandler 00000012
Symbol: I2C_IRQHandler
Definitions
At line 216 in file CORE\startup_ARMCM0.s
Uses
At line 113 in file CORE\startup_ARMCM0.s
At line 192 in file CORE\startup_ARMCM0.s
LIN_IRQHandler 00000012
Symbol: LIN_IRQHandler
Definitions
At line 215 in file CORE\startup_ARMCM0.s
Uses
At line 112 in file CORE\startup_ARMCM0.s
At line 191 in file CORE\startup_ARMCM0.s
MCIA_IRQHandler 00000012
Symbol: MCIA_IRQHandler
Definitions
At line 200 in file CORE\startup_ARMCM0.s
Uses
At line 98 in file CORE\startup_ARMCM0.s
At line 176 in file CORE\startup_ARMCM0.s
MCIB_IRQHandler 00000012
Symbol: MCIB_IRQHandler
ARM Macro Assembler Page 3 Alphabetic symbol ordering
Relocatable symbols
Definitions
At line 201 in file CORE\startup_ARMCM0.s
Uses
At line 99 in file CORE\startup_ARMCM0.s
At line 177 in file CORE\startup_ARMCM0.s
NMI_Handler 00000008
Symbol: NMI_Handler
Definitions
At line 148 in file CORE\startup_ARMCM0.s
Uses
At line 78 in file CORE\startup_ARMCM0.s
At line 149 in file CORE\startup_ARMCM0.s
PendSV_Handler 0000000E
Symbol: PendSV_Handler
Definitions
At line 161 in file CORE\startup_ARMCM0.s
Uses
At line 90 in file CORE\startup_ARMCM0.s
At line 162 in file CORE\startup_ARMCM0.s
RTC_IRQHandler 00000012
Symbol: RTC_IRQHandler
Definitions
At line 197 in file CORE\startup_ARMCM0.s
Uses
At line 95 in file CORE\startup_ARMCM0.s
At line 173 in file CORE\startup_ARMCM0.s
Reset_Handler 00000000
Symbol: Reset_Handler
Definitions
At line 135 in file CORE\startup_ARMCM0.s
Uses
At line 77 in file CORE\startup_ARMCM0.s
At line 136 in file CORE\startup_ARMCM0.s
SPI_IRQHandler 00000012
Symbol: SPI_IRQHandler
Definitions
At line 218 in file CORE\startup_ARMCM0.s
Uses
At line 125 in file CORE\startup_ARMCM0.s
At line 194 in file CORE\startup_ARMCM0.s
SVC_Handler 0000000C
Symbol: SVC_Handler
Definitions
At line 157 in file CORE\startup_ARMCM0.s
Uses
At line 87 in file CORE\startup_ARMCM0.s
At line 158 in file CORE\startup_ARMCM0.s
ARM Macro Assembler Page 4 Alphabetic symbol ordering
Relocatable symbols
SysTick_Handler 00000010
Symbol: SysTick_Handler
Definitions
At line 165 in file CORE\startup_ARMCM0.s
Uses
At line 91 in file CORE\startup_ARMCM0.s
At line 166 in file CORE\startup_ARMCM0.s
TIM0_IRQHandler 00000012
Symbol: TIM0_IRQHandler
Definitions
At line 198 in file CORE\startup_ARMCM0.s
Uses
At line 96 in file CORE\startup_ARMCM0.s
At line 174 in file CORE\startup_ARMCM0.s
TIM2_IRQHandler 00000012
Symbol: TIM2_IRQHandler
Definitions
At line 199 in file CORE\startup_ARMCM0.s
Uses
At line 97 in file CORE\startup_ARMCM0.s
At line 175 in file CORE\startup_ARMCM0.s
UART0_IRQHandler 00000012
Symbol: UART0_IRQHandler
Definitions
At line 202 in file CORE\startup_ARMCM0.s
Uses
At line 100 in file CORE\startup_ARMCM0.s
At line 178 in file CORE\startup_ARMCM0.s
UART1_IRQHandler 00000012
Symbol: UART1_IRQHandler
Definitions
At line 203 in file CORE\startup_ARMCM0.s
Uses
At line 101 in file CORE\startup_ARMCM0.s
At line 179 in file CORE\startup_ARMCM0.s
UART2_IRQHandler 00000012
Symbol: UART2_IRQHandler
Definitions
At line 204 in file CORE\startup_ARMCM0.s
Uses
At line 102 in file CORE\startup_ARMCM0.s
At line 180 in file CORE\startup_ARMCM0.s
UART3_IRQHandler 00000012
Symbol: UART3_IRQHandler
Definitions
ARM Macro Assembler Page 5 Alphabetic symbol ordering
Relocatable symbols
At line 205 in file CORE\startup_ARMCM0.s
Uses
At line 124 in file CORE\startup_ARMCM0.s
At line 181 in file CORE\startup_ARMCM0.s
UART4_IRQHandler 00000012
Symbol: UART4_IRQHandler
Definitions
At line 206 in file CORE\startup_ARMCM0.s
Uses
At line 103 in file CORE\startup_ARMCM0.s
At line 182 in file CORE\startup_ARMCM0.s
USBDC_IRQHandler 00000012
Symbol: USBDC_IRQHandler
Definitions
At line 210 in file CORE\startup_ARMCM0.s
Uses
At line 107 in file CORE\startup_ARMCM0.s
At line 186 in file CORE\startup_ARMCM0.s
USBHC_IRQHandler 00000012
Symbol: USBHC_IRQHandler
Definitions
At line 211 in file CORE\startup_ARMCM0.s
Uses
At line 108 in file CORE\startup_ARMCM0.s
At line 187 in file CORE\startup_ARMCM0.s
WDT_IRQHandler 00000012
Symbol: WDT_IRQHandler
Definitions
At line 196 in file CORE\startup_ARMCM0.s
Uses
At line 94 in file CORE\startup_ARMCM0.s
At line 172 in file CORE\startup_ARMCM0.s
__user_initial_stackheap 00000014
Symbol: __user_initial_stackheap
Definitions
At line 240 in file CORE\startup_ARMCM0.s
Uses
At line 238 in file CORE\startup_ARMCM0.s
Comment: __user_initial_stackheap used once
32 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
Heap_Size 00000C00
Symbol: Heap_Size
Definitions
At line 57 in file CORE\startup_ARMCM0.s
Uses
At line 61 in file CORE\startup_ARMCM0.s
At line 243 in file CORE\startup_ARMCM0.s
Stack_Size 00000400
Symbol: Stack_Size
Definitions
At line 46 in file CORE\startup_ARMCM0.s
Uses
At line 49 in file CORE\startup_ARMCM0.s
At line 242 in file CORE\startup_ARMCM0.s
__Vectors_Size 000000C0
Symbol: __Vectors_Size
Definitions
At line 128 in file CORE\startup_ARMCM0.s
Uses
At line 74 in file CORE\startup_ARMCM0.s
Comment: __Vectors_Size used once
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
SystemInit 00000000
Symbol: SystemInit
Definitions
At line 137 in file CORE\startup_ARMCM0.s
Uses
At line 139 in file CORE\startup_ARMCM0.s
Comment: SystemInit used once
__main 00000000
Symbol: __main
Definitions
At line 138 in file CORE\startup_ARMCM0.s
Uses
At line 141 in file CORE\startup_ARMCM0.s
Comment: __main used once
__use_two_region_memory 00000000
Symbol: __use_two_region_memory
Definitions
At line 237 in file CORE\startup_ARMCM0.s
Uses
None
Comment: __use_two_region_memory unused
3 symbols
384 symbols in table

804
Listings/startup_cmsdk_cm0.lst Normal file
View File

@ -0,0 +1,804 @@
ARM Macro Assembler Page 1
1 00000000 ;/******************************************************
********************//**
2 00000000 ; * @file startup_CMSDK_CM0.s
3 00000000 ; * @brief CMSIS Cortex-M0 Core Device Startup File f
or
4 00000000 ; * Device CMSDK_CM0
5 00000000 ; * @version V3.01
6 00000000 ; * @date 06. March 2012
7 00000000 ; *
8 00000000 ; * @note
9 00000000 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
10 00000000 ; *
11 00000000 ; * @par
12 00000000 ; * ARM Limited (ARM) is supplying this software for use
with Cortex-M
13 00000000 ; * processor based microcontrollers. This file can be
freely distributed
14 00000000 ; * within development tools that are supporting such AR
M based processors.
15 00000000 ; *
16 00000000 ; * @par
17 00000000 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, W
HETHER EXPRESS, IMPLIED
18 00000000 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED
WARRANTIES OF
19 00000000 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
APPLY TO THIS SOFTWARE.
20 00000000 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR S
PECIAL, INCIDENTAL, OR
21 00000000 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 00000000 ; *
23 00000000 ; ******************************************************
************************/
24 00000000 ;/*
25 00000000 ;//-------- <<< Use Configuration Wizard in Context Menu
>>> ------------------
26 00000000 ;*/
27 00000000
28 00000000
29 00000000 ; <h> Stack Configuration
30 00000000 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31 00000000 ; </h>
32 00000000
33 00000000 00000200
Stack_Size
EQU 0x00000200
34 00000000
35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
=3
36 00000000 Stack_Mem
SPACE Stack_Size
37 00000200 __initial_sp
38 00000200
39 00000200
40 00000200 ; <h> Heap Configuration
41 00000200 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
42 00000200 ; </h>
43 00000200
ARM Macro Assembler Page 2
44 00000200 00000100
Heap_Size
EQU 0x00000100
45 00000200
46 00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=
3
47 00000000 __heap_base
48 00000000 Heap_Mem
SPACE Heap_Size
49 00000100 __heap_limit
50 00000100
51 00000100
52 00000100 PRESERVE8
53 00000100 THUMB
54 00000100
55 00000100
56 00000100 ; Vector Table Mapped to Address 0 at Reset
57 00000100
58 00000100 AREA RESET, DATA, READONLY
59 00000000 EXPORT __Vectors
60 00000000 EXPORT __Vectors_End
61 00000000 EXPORT __Vectors_Size
62 00000000
63 00000000 00000000
__Vectors
DCD __initial_sp ; Top of Stack
64 00000004 00000000 DCD Reset_Handler ; Reset Handler
65 00000008 00000000 DCD NMI_Handler ; NMI Handler
66 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
Handler
67 00000010 00000000 DCD 0 ; Reserved
68 00000014 00000000 DCD 0 ; Reserved
69 00000018 00000000 DCD 0 ; Reserved
70 0000001C 00000000 DCD 0 ; Reserved
71 00000020 00000000 DCD 0 ; Reserved
72 00000024 00000000 DCD 0 ; Reserved
73 00000028 00000000 DCD 0 ; Reserved
74 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
75 00000030 00000000 DCD 0 ; Reserved
76 00000034 00000000 DCD 0 ; Reserved
77 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
78 0000003C 00000000 DCD SysTick_Handler
; SysTick Handler
79 00000040 00000000 DCD LVD_Handler ;
80 00000044 00000000 DCD RTC_Handler ;
81 00000048 00000000 DCD COMP0_Handler ;
82 0000004C 00000000 DCD COMP1_Handler ;
83 00000050 00000000 DCD GPIO0_7_Handler ;
84 00000054 00000000 DCD GPIO8_15_Handler ;
85 00000058 00000000 DCD GPIO16_23_Handler ;
86 0000005C 00000000 DCD MTP_Handler ;
87 00000060 00000000 DCD CHARGER_OK_Handler ;
88 00000064 00000000 DCD CHARGER_END_Handler ;
89 00000068 00000000 DCD ADC_Handler ;
90 0000006C 00000000 DCD LCD_Handler ;
91 00000070 00000000 DCD UART0_Handler ;
92 00000074 00000000 DCD UART1_Handler ;
93 00000078 00000000 DCD SPI0_Handler ;
ARM Macro Assembler Page 3
94 0000007C 00000000 DCD SPI1_Handler ;
95 00000080 00000000 DCD I2C0_Event_Handler ;
96 00000084 00000000 DCD I2C0_Error_Handler ;
97 00000088 00000000 DCD I2C1_Event_Handler ;
98 0000008C 00000000 DCD I2C1_Error_Handler ;
99 00000090 00000000 DCD PWM_Handler ;
100 00000094 00000000 DCD TIMER0_Handler ;
101 00000098 00000000 DCD TIMER1_Handler ;
102 0000009C 00000000 DCD DUALTIMER_Handler ;
103 000000A0 00000000 DCD OVER_TEMP_Handler ;
104 000000A4 00000000 DCD WG_DRV_Handler ;
105 000000A8 00000000 DCD 0 ;
106 000000AC 00000000 DCD 0 ;
107 000000B0 00000000 DCD 0 ;
108 000000B4 00000000 DCD 0 ;
109 000000B8 00000000 DCD 0 ;
110 000000BC 00000000 DCD 0 ;
111 000000C0 __Vectors_End
112 000000C0
113 000000C0 000000C0
__Vectors_Size
EQU __Vectors_End - __Vectors
114 000000C0
115 000000C0 AREA |.text|, CODE, READONLY
116 00000000
117 00000000
118 00000000 ; Reset Handler
119 00000000
120 00000000 Reset_Handler
PROC
121 00000000 EXPORT Reset_Handler [WEAK
]
122 00000000 IMPORT SystemInit
123 00000000 IMPORT __main
124 00000000 4804 LDR R0, =SystemInit
125 00000002 4780 BLX R0
126 00000004 4804 LDR R0, =__main
127 00000006 4700 BX R0
128 00000008 ENDP
129 00000008
130 00000008
131 00000008 ; Dummy Exception Handlers (infinite loops which can be
modified)
132 00000008
133 00000008 NMI_Handler
PROC
134 00000008 EXPORT NMI_Handler [WEAK
]
135 00000008 E7FE B .
136 0000000A ENDP
138 0000000A HardFault_Handler
PROC
139 0000000A EXPORT HardFault_Handler [WEAK
]
140 0000000A E7FE B .
141 0000000C ENDP
142 0000000C SVC_Handler
PROC
143 0000000C EXPORT SVC_Handler [WEAK
ARM Macro Assembler Page 4
]
144 0000000C E7FE B .
145 0000000E ENDP
146 0000000E PendSV_Handler
PROC
147 0000000E EXPORT PendSV_Handler [WEAK
]
148 0000000E E7FE B .
149 00000010 ENDP
150 00000010 SysTick_Handler
PROC
151 00000010 EXPORT SysTick_Handler [WEA
K]
152 00000010 E7FE B .
153 00000012 ENDP
154 00000012 Default_Handler
PROC
155 00000012 EXPORT LVD_Handler [WEAK]
156 00000012 EXPORT RTC_Handler [WEAK]
157 00000012 EXPORT COMP0_Handler [WEAK]
158 00000012 EXPORT COMP1_Handler [WEAK]
159 00000012 EXPORT GPIO0_7_Handler [WEAK]
160 00000012 EXPORT GPIO8_15_Handler [WEAK]
161 00000012 EXPORT GPIO16_23_Handler [WEAK]
162 00000012 EXPORT MTP_Handler [WEAK]
163 00000012 EXPORT CHARGER_OK_Handler [WEAK]
164 00000012 EXPORT CHARGER_END_Handler [WEAK]
165 00000012 EXPORT ADC_Handler [WEAK]
166 00000012 EXPORT LCD_Handler [WEAK]
167 00000012 EXPORT UART0_Handler [WEAK]
168 00000012 EXPORT UART1_Handler [WEAK]
169 00000012 EXPORT SPI0_Handler [WEAK]
170 00000012 EXPORT SPI1_Handler [WEAK]
171 00000012 EXPORT I2C0_Event_Handler [WEAK]
172 00000012 EXPORT I2C0_Error_Handler [WEAK]
173 00000012 EXPORT I2C1_Event_Handler [WEAK]
174 00000012 EXPORT I2C1_Error_Handler [WEAK]
175 00000012 EXPORT PWM_Handler [WEAK]
176 00000012 EXPORT TIMER0_Handler [WEAK]
177 00000012 EXPORT TIMER1_Handler [WEAK]
178 00000012 EXPORT DUALTIMER_Handler [WEAK]
179 00000012 EXPORT OVER_TEMP_Handler [WEAK]
180 00000012 EXPORT WG_DRV_Handler [WEAK]
181 00000012 LVD_Handler
182 00000012 RTC_Handler
183 00000012 COMP0_Handler
184 00000012 COMP1_Handler
185 00000012 GPIO0_7_Handler
186 00000012 GPIO8_15_Handler
187 00000012 GPIO16_23_Handler
188 00000012 MTP_Handler
189 00000012 CHARGER_OK_Handler
190 00000012 CHARGER_END_Handler
191 00000012 ADC_Handler
192 00000012 LCD_Handler
193 00000012 UART0_Handler
194 00000012 UART1_Handler
195 00000012 SPI0_Handler
196 00000012 SPI1_Handler
ARM Macro Assembler Page 5
197 00000012 I2C0_Event_Handler
198 00000012 I2C0_Error_Handler
199 00000012 I2C1_Event_Handler
200 00000012 I2C1_Error_Handler
201 00000012 PWM_Handler
202 00000012 TIMER0_Handler
203 00000012 TIMER1_Handler
204 00000012 DUALTIMER_Handler
205 00000012 OVER_TEMP_Handler
206 00000012 WG_DRV_Handler
207 00000012 E7FE B .
208 00000014 ENDP
209 00000014
210 00000014
211 00000014 ALIGN
212 00000014
213 00000014
214 00000014 ; User Initial Stack & Heap
215 00000014
216 00000014 IF :DEF:__MICROLIB
217 00000014
218 00000014 EXPORT __initial_sp
219 00000014 EXPORT __heap_base
220 00000014 EXPORT __heap_limit
221 00000014
222 00000014 ELSE
237 ENDIF
238 00000014
239 00000014
240 00000014 END
00000000
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw
ork --depend=.\objects\startup_cmsdk_cm0.d -o.\objects\startup_cmsdk_cm0.o -ID:
\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\
Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include --predefine="__MICROLIB SE
TA 1" --predefine="__UVISION_VERSION SETA 538" --predefine="ARMCM0 SETA 1" --li
st=.\listings\startup_cmsdk_cm0.lst CORE\ARM\startup_CMSDK_CM0.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
STACK 00000000
Symbol: STACK
Definitions
At line 35 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
None
Comment: STACK unused
Stack_Mem 00000000
Symbol: Stack_Mem
Definitions
At line 36 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
None
Comment: Stack_Mem unused
__initial_sp 00000200
Symbol: __initial_sp
Definitions
At line 37 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 63 in file CORE\ARM\startup_CMSDK_CM0.s
At line 218 in file CORE\ARM\startup_CMSDK_CM0.s
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
HEAP 00000000
Symbol: HEAP
Definitions
At line 46 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
None
Comment: HEAP unused
Heap_Mem 00000000
Symbol: Heap_Mem
Definitions
At line 48 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
None
Comment: Heap_Mem unused
__heap_base 00000000
Symbol: __heap_base
Definitions
At line 47 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 219 in file CORE\ARM\startup_CMSDK_CM0.s
Comment: __heap_base used once
__heap_limit 00000100
Symbol: __heap_limit
Definitions
At line 49 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 220 in file CORE\ARM\startup_CMSDK_CM0.s
Comment: __heap_limit used once
4 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
RESET 00000000
Symbol: RESET
Definitions
At line 58 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
None
Comment: RESET unused
__Vectors 00000000
Symbol: __Vectors
Definitions
At line 63 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 59 in file CORE\ARM\startup_CMSDK_CM0.s
At line 113 in file CORE\ARM\startup_CMSDK_CM0.s
__Vectors_End 000000C0
Symbol: __Vectors_End
Definitions
At line 111 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 60 in file CORE\ARM\startup_CMSDK_CM0.s
At line 113 in file CORE\ARM\startup_CMSDK_CM0.s
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
.text 00000000
Symbol: .text
Definitions
At line 115 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
None
Comment: .text unused
ADC_Handler 00000012
Symbol: ADC_Handler
Definitions
At line 191 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 89 in file CORE\ARM\startup_CMSDK_CM0.s
At line 165 in file CORE\ARM\startup_CMSDK_CM0.s
CHARGER_END_Handler 00000012
Symbol: CHARGER_END_Handler
Definitions
At line 190 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 88 in file CORE\ARM\startup_CMSDK_CM0.s
At line 164 in file CORE\ARM\startup_CMSDK_CM0.s
CHARGER_OK_Handler 00000012
Symbol: CHARGER_OK_Handler
Definitions
At line 189 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 87 in file CORE\ARM\startup_CMSDK_CM0.s
At line 163 in file CORE\ARM\startup_CMSDK_CM0.s
COMP0_Handler 00000012
Symbol: COMP0_Handler
Definitions
At line 183 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 81 in file CORE\ARM\startup_CMSDK_CM0.s
At line 157 in file CORE\ARM\startup_CMSDK_CM0.s
COMP1_Handler 00000012
Symbol: COMP1_Handler
Definitions
At line 184 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 82 in file CORE\ARM\startup_CMSDK_CM0.s
At line 158 in file CORE\ARM\startup_CMSDK_CM0.s
DUALTIMER_Handler 00000012
Symbol: DUALTIMER_Handler
Definitions
At line 204 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
At line 102 in file CORE\ARM\startup_CMSDK_CM0.s
At line 178 in file CORE\ARM\startup_CMSDK_CM0.s
Default_Handler 00000012
Symbol: Default_Handler
Definitions
At line 154 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
None
Comment: Default_Handler unused
GPIO0_7_Handler 00000012
Symbol: GPIO0_7_Handler
Definitions
At line 185 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 83 in file CORE\ARM\startup_CMSDK_CM0.s
At line 159 in file CORE\ARM\startup_CMSDK_CM0.s
GPIO16_23_Handler 00000012
Symbol: GPIO16_23_Handler
Definitions
At line 187 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 85 in file CORE\ARM\startup_CMSDK_CM0.s
At line 161 in file CORE\ARM\startup_CMSDK_CM0.s
GPIO8_15_Handler 00000012
Symbol: GPIO8_15_Handler
Definitions
At line 186 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 84 in file CORE\ARM\startup_CMSDK_CM0.s
At line 160 in file CORE\ARM\startup_CMSDK_CM0.s
HardFault_Handler 0000000A
Symbol: HardFault_Handler
Definitions
At line 138 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 66 in file CORE\ARM\startup_CMSDK_CM0.s
At line 139 in file CORE\ARM\startup_CMSDK_CM0.s
I2C0_Error_Handler 00000012
Symbol: I2C0_Error_Handler
Definitions
At line 198 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 96 in file CORE\ARM\startup_CMSDK_CM0.s
At line 172 in file CORE\ARM\startup_CMSDK_CM0.s
I2C0_Event_Handler 00000012
Symbol: I2C0_Event_Handler
ARM Macro Assembler Page 3 Alphabetic symbol ordering
Relocatable symbols
Definitions
At line 197 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 95 in file CORE\ARM\startup_CMSDK_CM0.s
At line 171 in file CORE\ARM\startup_CMSDK_CM0.s
I2C1_Error_Handler 00000012
Symbol: I2C1_Error_Handler
Definitions
At line 200 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 98 in file CORE\ARM\startup_CMSDK_CM0.s
At line 174 in file CORE\ARM\startup_CMSDK_CM0.s
I2C1_Event_Handler 00000012
Symbol: I2C1_Event_Handler
Definitions
At line 199 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 97 in file CORE\ARM\startup_CMSDK_CM0.s
At line 173 in file CORE\ARM\startup_CMSDK_CM0.s
LCD_Handler 00000012
Symbol: LCD_Handler
Definitions
At line 192 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 90 in file CORE\ARM\startup_CMSDK_CM0.s
At line 166 in file CORE\ARM\startup_CMSDK_CM0.s
LVD_Handler 00000012
Symbol: LVD_Handler
Definitions
At line 181 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 79 in file CORE\ARM\startup_CMSDK_CM0.s
At line 155 in file CORE\ARM\startup_CMSDK_CM0.s
MTP_Handler 00000012
Symbol: MTP_Handler
Definitions
At line 188 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 86 in file CORE\ARM\startup_CMSDK_CM0.s
At line 162 in file CORE\ARM\startup_CMSDK_CM0.s
NMI_Handler 00000008
Symbol: NMI_Handler
Definitions
At line 133 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 65 in file CORE\ARM\startup_CMSDK_CM0.s
At line 134 in file CORE\ARM\startup_CMSDK_CM0.s
ARM Macro Assembler Page 4 Alphabetic symbol ordering
Relocatable symbols
OVER_TEMP_Handler 00000012
Symbol: OVER_TEMP_Handler
Definitions
At line 205 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 103 in file CORE\ARM\startup_CMSDK_CM0.s
At line 179 in file CORE\ARM\startup_CMSDK_CM0.s
PWM_Handler 00000012
Symbol: PWM_Handler
Definitions
At line 201 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 99 in file CORE\ARM\startup_CMSDK_CM0.s
At line 175 in file CORE\ARM\startup_CMSDK_CM0.s
PendSV_Handler 0000000E
Symbol: PendSV_Handler
Definitions
At line 146 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 77 in file CORE\ARM\startup_CMSDK_CM0.s
At line 147 in file CORE\ARM\startup_CMSDK_CM0.s
RTC_Handler 00000012
Symbol: RTC_Handler
Definitions
At line 182 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 80 in file CORE\ARM\startup_CMSDK_CM0.s
At line 156 in file CORE\ARM\startup_CMSDK_CM0.s
Reset_Handler 00000000
Symbol: Reset_Handler
Definitions
At line 120 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 64 in file CORE\ARM\startup_CMSDK_CM0.s
At line 121 in file CORE\ARM\startup_CMSDK_CM0.s
SPI0_Handler 00000012
Symbol: SPI0_Handler
Definitions
At line 195 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 93 in file CORE\ARM\startup_CMSDK_CM0.s
At line 169 in file CORE\ARM\startup_CMSDK_CM0.s
SPI1_Handler 00000012
Symbol: SPI1_Handler
Definitions
ARM Macro Assembler Page 5 Alphabetic symbol ordering
Relocatable symbols
At line 196 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 94 in file CORE\ARM\startup_CMSDK_CM0.s
At line 170 in file CORE\ARM\startup_CMSDK_CM0.s
SVC_Handler 0000000C
Symbol: SVC_Handler
Definitions
At line 142 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 74 in file CORE\ARM\startup_CMSDK_CM0.s
At line 143 in file CORE\ARM\startup_CMSDK_CM0.s
SysTick_Handler 00000010
Symbol: SysTick_Handler
Definitions
At line 150 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 78 in file CORE\ARM\startup_CMSDK_CM0.s
At line 151 in file CORE\ARM\startup_CMSDK_CM0.s
TIMER0_Handler 00000012
Symbol: TIMER0_Handler
Definitions
At line 202 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 100 in file CORE\ARM\startup_CMSDK_CM0.s
At line 176 in file CORE\ARM\startup_CMSDK_CM0.s
TIMER1_Handler 00000012
Symbol: TIMER1_Handler
Definitions
At line 203 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 101 in file CORE\ARM\startup_CMSDK_CM0.s
At line 177 in file CORE\ARM\startup_CMSDK_CM0.s
UART0_Handler 00000012
Symbol: UART0_Handler
Definitions
At line 193 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 91 in file CORE\ARM\startup_CMSDK_CM0.s
At line 167 in file CORE\ARM\startup_CMSDK_CM0.s
UART1_Handler 00000012
Symbol: UART1_Handler
Definitions
At line 194 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 92 in file CORE\ARM\startup_CMSDK_CM0.s
At line 168 in file CORE\ARM\startup_CMSDK_CM0.s
ARM Macro Assembler Page 6 Alphabetic symbol ordering
Relocatable symbols
WG_DRV_Handler 00000012
Symbol: WG_DRV_Handler
Definitions
At line 206 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 104 in file CORE\ARM\startup_CMSDK_CM0.s
At line 180 in file CORE\ARM\startup_CMSDK_CM0.s
34 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Absolute symbols
Heap_Size 00000100
Symbol: Heap_Size
Definitions
At line 44 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 48 in file CORE\ARM\startup_CMSDK_CM0.s
Comment: Heap_Size used once
Stack_Size 00000200
Symbol: Stack_Size
Definitions
At line 33 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 36 in file CORE\ARM\startup_CMSDK_CM0.s
Comment: Stack_Size used once
__Vectors_Size 000000C0
Symbol: __Vectors_Size
Definitions
At line 113 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 61 in file CORE\ARM\startup_CMSDK_CM0.s
Comment: __Vectors_Size used once
3 symbols
ARM Macro Assembler Page 1 Alphabetic symbol ordering
External symbols
SystemInit 00000000
Symbol: SystemInit
Definitions
At line 122 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 124 in file CORE\ARM\startup_CMSDK_CM0.s
Comment: SystemInit used once
__main 00000000
Symbol: __main
Definitions
At line 123 in file CORE\ARM\startup_CMSDK_CM0.s
Uses
At line 126 in file CORE\ARM\startup_CMSDK_CM0.s
Comment: __main used once
2 symbols
384 symbols in table

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<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.38.0.0
Copyright (C) 2022 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: rick chen, hangzhouQX, LIC=RC93N-YY58Z-RAADM-X0YVM-V5YIY-0QTVL
Tool Versions:
Toolchain: MDK-ARM Plus Version: 5.38.0.0
Toolchain Path: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin
C Compiler: Armcc.exe V5.06 update 6 (build 750)
Assembler: Armasm.exe V5.06 update 6 (build 750)
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
CPU DLL: SARMCM3.DLL V5.38.0.0
Dialog DLL: DARMCM1.DLL V1.19.6.0
Target DLL: Segger\JL2CM3.dll V2.99.42.0
Dialog DLL: TARMCM1.DLL V1.14.6.0
<h2>Project:</h2>
E:\Workspace\TIMER_DEMO\ENS001_BASIC_PRJ.uvprojx
Project File Date: 08/13/2025
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin'
Build target 'ENS001_BASIC_PRJ'
".\Objects\ENS001_BASIC_PRJ.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
https://www.keil.com/pack/ARM.Cortex_DFP.1.1.0.pack
ARM.Cortex_DFP.1.1.0
ARM Cortex Reference Subsystems Device Family Pack
<h2>Collection of Component include folders:</h2>
D:/Keil_v5/ARM/Packs/ARM/Cortex_DFP/1.1.0/Device/ARMCM0/Include
<h2>Collection of Component Files used:</h2>
Build Time Elapsed: 00:00:00
</pre>
</body>
</html>

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:020000041000EA
:1000000048020020D5000010DD000010DF000010C5
:1000100000000000000000000000000000000000E0
:10002000000000000000000000000000E1000010DF
:100030000000000000000000E3000010E5000010D8
:10004000E7000010E7000010E7000010E7000010D4
:10005000E7000010E7000010E7000010E7000010C4
:10006000E7000010E7000010E7000010E7000010B4
:100070003D0C0010A90C0010E7000010E700001074
:10008000E7000010E7000010E7000010E700001094
:10009000E70000108D0B0010210C0010E70000108D
:1000A000E7000010E7000010000000000000000062
:1000B0000000000000000000000000000000000040
:1000C0000348854600F096FA004800475111001099
:1000D000480200200448804704480047FEE7FEE746
:1000E000FEE7FEE7FEE7FEE77D0B0010C100001013
:1000F00030B50B46014600202022012409E00D46C0
:10010000D5409D4205D31D469540491B2546954047
:1001100040191546521E002DF1DC30BDF0B50C46DD
:100120005C4085B0E40FE40703944C0000266408AB
:1001300059009446490802460296224321D062465D
:100140000A431ED06200570D4A000E032303550DCB
:10015000012402462C492405781B1B0B360B401842
:1001600023432643614600901C46501AB44103D3F2
:100170000098401C009002E0921800985B41002813
:1001800003DA0020014605B0F0BD00200121090579
:100190000746864611E064461D46141BB54106D34A
:1001A0006546521BB341744607430C43A646CD0730
:1001B00040084908284392185B4105460D43EAD19F
:1001C0001046184313D0604619465040714008430A
:1001D00006D06046101AB34106D20122002306E081
:1001E00000220123DB0702E00122D24353100098D2
:1001F00074460105381C6141029C039D0019694148
:1002000000F055F8BFE70000FD0300000EB5C2176F
:10021000C10F5040CA0740180021054B02930192BC
:1002200000910A460B4600F04FF803B000BD0000F5
:10023000330400000EB505490291002100910A46E1
:100240000B46019100F040F803B000BD33040000FC
:100250004A0009030123090B1B051943094B10B57B
:10026000520D9A4201DA002010BD064B34339A42F7
:1002700003DC9A1A00F00AF810BD034951188840AF
:1002800010BD0000FF030000CDFBFFFF10B5202ACA
:1002900004DB0846203AD040002110BD0B46D34075
:1002A000D0402024A21A91400843194610BD10B531
:1002B000002B08DA0024401C614192185B411A436C
:1002C00001D14008400010BDF0B51FB482B0054612
:1002D0000C0003D0084600F0C5FD02E000F0C2FDAE
:1002E0002030024600902146284600F095F9049BF4
:1002F000059A04460F4618431143084314D0184684
:1003000010431BD0009840210A1A18460599FFF7A0
:10031000BDFF05460E46009A0599049800F07CF949
:10032000084305D0012004E02046394607B0F0BD5F
:100330000020C11705430E432C43374300990E9804
:100340006305401A7905E40A00220C43FD0A0A30CD
:1003500002D500200146E9E70105101969410C9C0E
:100360000D9D00196941FFF7A2FFDFE7F0B50746D1
:100370000846584087B0C00F049048000E46590008
:1003800040084908BC1A884105D2384631461E4605
:1003900017460B4602465800400810434CD0300D1B
:1003A000039040055900400D490D0590401A0290F8
:1003B000402872DA18030121000B09050843019057
:1003C00004980092002805D00199524200208841EB
:1003D00000920190029840210A1A0199009800F0B9
:1003E0001BF905460C466B4607CB00F025F9C019F2
:1003F0007141039A0E0D0023D71756401A467A40D2
:10040000164344D0049A002A2DD0029A012A039A56
:1004100015DC1205C01A914101263605001C7141F8
:10042000D20F059ED2070093019202962A462346D8
:10043000FFF74AFF07B0F0BD38463146FAE7160528
:10044000224A0F46B218C01AB74101210905001C03
:100450004F4100187F41114618187941E20F1043AF
:100460006D19644113E0E2076D0815436408C20783
:100470001443039A01261205C01A91413605001C47
:100480007141CE07400830434908C01851412A46FF
:100490002346FFF70CFFCDE7FFE704980122400059
:1004A000C117121A00238B4104983146C417381A19
:1004B000A141EEE730B40124E407634030BC55E7C6
:1004C00030B40124E407614030BC4FE70000E0FF96
:1004D000F0B51FB488B00B990998002448400999D9
:1004E000C00F490049080991C0070B9900904900C5
:1004F00049080B9109990898A64608431CD00B9906
:100500000A98084318D0099801244000420D480079
:10051000410D099824050003000B204309900B9816
:100520000003000B20430B9050181C494018002278
:1005300001901446104605E0002001460DB0F0BDC4
:10054000032801DA034600E003239C46C11A0AAEE1
:100550000AE05F0008ADED5B4F00F75B7D430027CD
:10056000AA187C41491C5B1E6145F2DD410004ABC9
:100570005A522104120C0A43240C401C0828DFDBC9
:10058000019802900099704601910090059B049A91
:1005900007990698FFF798FED0E700000DFCFFFFD3
:1005A00070B54B005B0803430BD04B005C0D00267D
:1005B00033466542B341D417AD1AA34102DB002094
:1005C000014670BD12053018514170BD10B50029AB
:1005D00004DB0124E40740428C412146002B04DB6C
:1005E0001C460123DB075242A341994200D19042AD
:1005F00010BD0000064C0125064E05E0E36807CC5F
:100600002B430C3C98471034B442F7D3FFF75CFD02
:10061000701C0010901C001010B5202A04DB01464D
:10062000203A9140002010BD914020239C1A03469F
:10063000E3401943904010BD10B5202A06DBCB17CC
:100640000846203A1041C1170B4306E00B46134100
:10065000D0402024A21A91400843194610BDFEB58F
:1006600000231A461B1A8A4103DB0020014603B00F
:10067000F0BD4A000D0301212D0B0905520D0D435C
:10068000D10702D100186D41521E5110FF31FF31C8
:100690000131002704463E46384600970191024644
:1006A000012100200905FFF7F1FDC3197141F81878
:1006B000324684468E464A4161462846611A904138
:1006C00004D36046241A954176461F4624190098A3
:1006D0006D41401C00903428E1DDF919304670412D
:1006E000091BA84103D20022D243134601E0002295
:1006F000134601980105381C7141FFF7D8FDB6E794
:1007000010B51346002241608160002B01D00824FF
:10071000224301242243026010BD000010B50448AA
:1007200000F00CF80349086000200349486110BD3F
:100730001C0000201800002000000240F0B587B027
:1007400004460027544800682178090408435249A8
:100750000860207800281AD10846406861780901AD
:1007600008434D4948606178881CFFF74FFD0246F9
:100770000B460591049000200121890700F00EFD31
:100780000546FFF765FDC7B244494F4328E020788E
:10079000012803D1A77841494F4321E0207802285E
:1007A00001D187031CE02078032801D1A78817E036
:1007B00039484068617809010843374948606178E1
:1007C000881CFFF723FD02460B460591049000208C
:1007D0000121890700F0E2FC0546FFF739FDC7B2A9
:1007E0002D480068A17908432B49086000BF2A48BA
:1007F00000684007C00F0028F9D127480068217A17
:10080000090208432449086008460068E1790903A1
:10081000084321490860207A00281BDD217AC81E80
:10082000FFF7F4FC05462A460B4600200121890704
:1008300000F0B4FC039102903846FFF7FBFC0191F5
:100840000090039B029AFFF769FC05910490FFF763
:10085000FFFC0746E07900281BDDE179C81EFFF7A1
:10086000D5FC05462A460B4600200121890700F0E9
:1008700095FC039102903846FFF7DCFC0191009053
:10088000039B029AFFF74AFC05910490FFF7E0FCF6
:100890000746384607B0F0BD0000024040420F0056
:1008A00010B502460F2A14DD1348806B1346103B27
:1008B0005C000323A34098430F4B98631846806B5A
:1008C0001346103B5C000B46A34018430A4B986349
:1008D0000FE00948406B54000323A3409843064BA4
:1008E00058631846406B54000B46A3401843024B14
:1008F0005863002010BD000000100240014604486B
:10090000406801228A401040C840C0B270470000D1
:1009100000100240FFB504460D461E460B9F002105
:100920002046FFF7BDFF012D10D1012F0ED14F48FA
:1009300000690121A14088434C490861084640698B
:100940000121A1400843494948613BE0012D10D1F4
:10095000002F0ED1454800690121A1408843434939
:100960000861084640690121A14088433F49486128
:1009700028E0002D14D1012F12D13C4840690121FB
:10098000A140884339494861084600690121A140D6
:10099000084336490861099848620298086311E0E3
:1009A000002D0FD1002F0DD1304800690121A14049
:1009B00088432E490861084640690121A1408843C7
:1009C0002A494861022E0ED1284880690121A140A0
:1009D0008843264988610846C1690120A0408143B7
:1009E0002248C1611FE0002E0ED1204880690121FC
:1009F000A14008431D4988610846C0690121A14002
:100A000088431A49C8610EE0012E0CD1174881694C
:100A10000120A040814315488161C0690121A140A6
:100A200008431249C8611148816A0120A0408143EE
:100A30000E488162806A0A99C907C90FA14008431C
:100A40000A4988620846C06A0121A14088430749D3
:100A5000C8620846C06A0A998907C90FA1400843BD
:100A60000249C862002004B0F0BD0000001002403E
:100A7000012907D1074A5268012383401A43054BD5
:100A80005A6006E0034A5268012383409A43014BAF
:100A90005A6070470010024000B503461846FFF741
:100AA0002DFF012803D1184600F00AF807E0184688
:100AB000FFF724FF002802D1184600F00BF800BD14
:100AC00003494968012282409143014A51607047BD
:100AD0000010024003494968012282401143014A43
:100AE000516070470010024000207047C206D20ECD
:100AF00001219140014A11607047000080E200E04E
:100B0000C206D20E01219140014A116070470000D7
:100B100080E200E0C206D20E01219140014A11603C
:100B20007047000080E100E0C206D20E0121914032
:100B3000014A11607047000080E100E0C206D20E59
:100B400001219140014A11607047000000E100E07E
:100B5000C206D20E01219140014A11607047000087
:100B600000E100E001460448406901228A40104348
:100B7000014A5061002070470000024001480249CC
:100B80000860704700E1F5054000002010B5012025
:100B90000E49C8600E480068401C0D4908607D2160
:100BA000C9000B480068FFF7A3FA00290CD11320F5
:100BB000FFF772FF07480068401C064908600846B6
:100BC000016805A000F03EF910BD00000080004063
:100BD0003000002034000020256420730A0000004B
:100BE00070B504460820FFF7BDFF1520FFF79CFFF6
:100BF0001520FFF785FF7D21C90007480068FFF732
:100C000077FA60430546012229460448FFF778FD3C
:100C10001520FFF79DFF70BD1800002000800040E8
:100C200001200449C86004480068401C024908606B
:100C300070470000009000403800002010B50024EC
:100C40000C20FFF753FF0120800700F062F8032813
:100C500006D10120800740680421884309074860C5
:100C60000120800700F055F8022805D001208007F8
:100C700000F04FF8062816D1012080074068400890
:100C8000400001218907486008460068C4B2214637
:100C90000120800700F0C4F801208007406801218E
:100CA00008438907486010BD10B500240D20FFF7E8
:100CB0001DFF144800F02DF8032805D111484068A5
:100CC000042188430F4948600E4800F022F80228AA
:100CD00004D00C4800F01DF8062812D109484068DD
:100CE000400840000749486008460068C4B22146F1
:100CF000044800F095F80348406801210843014981
:100D0000486010BD00100040014648698006C00FD1
:100D10007047014688680007400F704770B5044669
:100D20000D461348844206D10D20FFF7F3FE0D2037
:100D3000FFF7DCFE09E001208007844205D10C208A
:100D4000FFF7E8FE0C20FFF7D1FE60682978084322
:100D500060600748844203D10D20FFF7EFFE06E0F4
:100D600001208007844202D10C20FFF7E7FE70BD0E
:100D700000100040F8B504460D460120800784426B
:100D80000BD10020FFF7EEFE01210220FFF788FDC6
:100D900001210320FFF784FD0DE01F4884420AD1A2
:100DA0000120FFF7DFFE01210C20FFF779FD012173
:100DB0000D20FFF775FD606BC007C00F002801D143
:100DC000102700E00D27154869680068FFF790F9C3
:100DD00039460090FFF78CF9401E86B21120304052
:100DE000206211200002304000126062A068E968B1
:100DF000097889010843A060E8688078012803D158
:100E0000A06801210843A060287A012803D1206945
:100E1000202108432061F8BD001000401800002088
:100E200000B503460A4600BF1846FFF76DFF0028CD
:100E3000FAD01146184600F002F8104600BD0160D5
:100E4000704700000FB410B503A9044B044A029880
:100E500000F0CCF810BC08BC04B018473D110010DD
:100E6000280000202021020C01D010211046020A87
:100E700001D010460839020901D01046091F820826
:100E800001D01046891E420801D0881E7047081AFA
:100E9000704700004900CA020243100000D004203D
:100EA0004A0D01D001221043044A490D914201D15B
:100EB00002210843012800D105207047FF070000E8
:100EC000F8B504464F1EC8000838211815461E46BE
:100ED000086849683A4606239A4310D02A463346A2
:100EE000FFF7F6FA3A46D200083AA3181A687F1EAE
:100EF0005B68FFF73BFA06223B469343EED1022F95
:100F000023D0042F11D0062F2FD12A463346FFF7C6
:100F1000DFFAE36AA26AFFF729FA2A463346FFF7A7
:100F2000D7FA636A226AFFF721FA2A463346FFF7A7
:100F3000CFFAE369A269FFF719FA2A463346FFF7A9
:100F4000C7FA63692269FFF711FA2A463346FFF7A9
:100F5000BFFAE368A268FFF709FA2A463346FFF7AB
:100F6000B7FA63682268FFF701FAF8BD002210B5EE
:100F7000134610460149FFF7D1F810BD0000F03FBD
:100F800010B5FFF7F3F910BD002210B51346104657
:100F90001146FFF7C3F810BD10B50721024A002023
:100FA0000907FFF7FDFA10BD01030000034A10B561
:100FB00000201107FFF7F4FA10BD000001FDFFFF4C
:100FC00002E008C8121F08C1002AFAD17047704712
:100FD000002001E001C1121F002AFBD17047000070
:100FE000014908607047000044000020FFB58DB043
:100FF0000446002506E025280AD0109A0F9990474C
:10100000641C6D1C20780028F5D1284611B0F0BD75
:1010100000270121484A009700E00743641C237819
:101020000846203B98401042F7D120782E2817D14F
:10103000042007436078641C2A280CD10E98641C95
:1010400002C800910E900BE000990A2251433039FA
:101050004018641C00902078014630390929F3D9E2
:1010600020780028D1D0642808D0692806D07528B7
:101070001ED0109A0F9990476D1C5BE00A200E99C4
:10108000019001C90E91002802DA40422D2102E0B0
:10109000390504D52B216A461172012103E0F907B5
:1010A00004D02021F7E70BAE0B910DE00021FAE709
:1010B0000A200E99019001C90E91F7E70199FFF7F7
:1010C00017F83031761E31700028F7D103A8801B45
:1010D00020300190780701D5009801E001200090B0
:1010E0000199884201DD401A00E0002000270090AD
:1010F00006E002A8109AC05D0F9990476D1C7F1CF6
:101100000B988742F5DB04E0109A30200F99904746
:101110006D1C0099481E00900029F5DC05E0307830
:10112000109A761C0F9990476D1C0199481E0190EA
:101130000029F4DC641C65E70928010070B5044649
:101140000D46E1B20148FFF76BFE70BD0010004094
:101150000EB5FFF7C9FCFFF7E1FA0120002100916D
:1011600002230A46019102901320FFF7D3FB0021CE
:101170001320FFF77DFC06490648FFF7FBFD0649F3
:101180000448FFF7CBFD0120FFF72AFD00BFFEE773
:10119000040000200010004014000020F0B51FB42F
:1011A00096B084460C460246199D18980390490053
:1011B00068006300490840080193002A01D0012615
:1011C00000E000269E19FE4BF6185B109E422BD3C2
:1011D0006E00039F0296002F00D00127F719F84EEA
:1011E000F84BBE199E421FD3039E0346F64F33436E
:1011F00009D03B469C4201D1002A04D0019B002A21
:1012000005D0012604E0002039461BB0F0BD0026C1
:101210009E19EE4B9E4207D8039F029E002F00D0DE
:101220000127F6199E4207D92B4660462146189A97
:10123000FFF7A6FE1BB0F0BD0023002C29DAE44E18
:10124000B04226DAE34EB04201DB022321E0DE4E5B
:10125000B0421EDBE04E070DBE19142E09DD342707
:10126000BF1B039EFE400196BE40039FBE420BD0B3
:101270000FE0039F002F0CD11427BF1B0646FE4032
:101280000196BE40864204D1019BDE07F60F022381
:101290009B1B0E46164318D1002D16DA002C03D0E6
:1012A000022B01D0012B06D00220FFF799FEFFF799
:1012B0005DFE1BB0F0BD0220FFF792FEFFF756FE69
:1012C0000122D20751401BB0F0BD039E002E61D118
:1012D000BF4EB04220D1C148844201D1002A08D07B
:1012E000B948814209DB002D10DB189829461BB054
:1012F000F0BD0020B4491BB0F0BD002D06DA01227C
:101300002946D207189851401BB0F0BDB449794422
:10131000086849681BB0F0BDAB4FB84225D1002D1D
:101320001FDA002904D0B14212D1002A09D018E0F6
:10133000002A72D1A649E20F0020D20711431BB048
:10134000F0BD0020E20F0146D20711431BB0F0BDF3
:10135000B14206DA234600203946FEF7DFFE1BB015
:10136000F0BD104621461BB0F0BDB14212DA012695
:10137000B607B54203D1234610461946FEE3994EFF
:10138000B54207D1261E05DB1046314600F004FCAD
:101390001BB0F0BD67007F081646002A40D1002927
:1013A0000AD08B4A914229D1002C0EDD002D1CDB86
:1013B000002011461BB0F0BD022B16D0002C14D01B
:1013C000012B12D1002C14DB0FE0002C28DA002DA9
:1013D00009DB012B03D000207D491BB0F0BD0020AC
:1013E00081491BB0F0BD012B03D0002001461BB08A
:1013F000F0BD00200121C9071BB0F0BD724A914227
:101400000ED1002C01DA002B17D0022B06D00020C1
:10141000C043FEF7FBFE1BB0F0BD90E20120F8E7F1
:10142000E217521C94461A4307D000220892664CD9
:1014300062465B1E1A4307D009E00120FFF7D0FD8A
:10144000FFF7A2FD1BB0F0BD0022644C0892674A72
:1014500090427DDD664B674A98421FDD914202DC77
:10146000002D05DB4DE05848814217DB002D48DD9B
:101470000220FFF7B5FDFFF78FFD05460E4600225F
:10148000534B21460898FFF723F808467100490896
:10149000C00FC007014328461BB0F0BD914215DACA
:1014A000002D2EDA0220FFF79BFDFFF775FD0546A4
:1014B0000E460022464B21460898FFF709F87200B5
:1014C0005208C80FC0070243114617E03E4B99422D
:1014D00023DD002D15DD0220FFF782FDFFF75CFD07
:1014E00005460E4600223A4B21460898FEF7F0FFCB
:1014F000084671004908C00FC007014328461BB0C9
:10150000F0BD0220FFF76CFDFFF750FD49004908D0
:10151000E20FD20711431BB0F0BD0022304639461E
:10152000FEF7C8FF012205460E46D243FFF738F802
:10153000314A324BFEF7C4FF2A463346FEF7C8FF56
:101540000022284BFEF7BCFF07462A46334600E040
:1015500064E0039110461946FEF7BAFF3A46039B32
:10156000FEF7B6FF0746032209915207244B28468F
:101570003146FEF7ADFF07910C90224A204B3846CA
:101580000999FEF7A5FF074601911F4A1F4B284600
:101590003146FEF79DFF3A46019BFEF78BFF07465B
:1015A0000B460246099107990C98FEF7DFFE0025CD
:1015B0000E462846079B0C9AFEF77CFF3A4627E02A
:1015C000FFFF1F00FFFF0F000000F03F0000E0FFE3
:1015D0000000F07F0000404301FCFFFF0000F0BF6F
:1015E000560900000000E03F0000F0FF0000E0416D
:1015F0000000F043FFFFEF3F555555555555D53F7A
:101600004715F73FFE822B6544DF5DF80BAE543E75
:10161000099BFEF755FF02460B4652E101250020CB
:101620002D05A94207DA352230463946FEF7B8FFC4
:1016300006463420C0430A151218FE4810180390BD
:101640000803FD49000B01430F46FC49884201DCB9
:10165000002003E0FA49884202DA0120119005E0F7
:10166000002011900398401C7F1B03901198059750
:10167000C200F4480F9278448018436802683946E3
:1016800030460D930292FEF715FF07910C903046FD
:101690000D9B029A0599FEF769FE02460B46002053
:1016A000E549FEF73BFD09910490079B0C9AFEF774
:1016B0000FFF129000201090E3480D467844006818
:1016C0000E90012178104907084311990D9B890458
:1016D00040180121C90447183946029A0E98FEF7AE
:1016E000E9FE3246059BFEF7EBFE02460B46294615
:1016F0001098FEF7EDFE064602913B4629460E9AEB
:101700001098FEF7E5FE079B0C9AFEF7D9FE3246CD
:10171000029BFEF7CFFE099B049AFEF7D9FE0591C6
:10172000129A0A902B4610461946FEF7D1FE06463D
:101730000246C6480F460B4606217844FFF7C0FB19
:1017400032463B460091049010461946FEF7C0FE13
:10175000009B049AFEF7BCFE06460F462B46194630
:10176000129A1098FEF702FE059B0A9AFEF7B0FE49
:1017700032463B46FEF7FAFD109A079104902B463D
:1017800010461946FEF7A4FEB14E002233460991D9
:101790000290FEF7EBFD079B049AFEF7E7FD0020A1
:1017A0000746024633460091FEF784FE099B029AE3
:1017B000FEF780FE079B049AFEF782FE06460D9117
:1017C0003A462946009B1098FEF782FE07910C903E
:1017D0002B463046129A0D99FEF77AFE05460E46C4
:1017E0003A46009B05990A98FEF772FE33462A4650
:1017F000FEF7BCFD02460B460746099107990C9877
:10180000FEF7B4FD00250E462846079B0C9AFEF70E
:1018100051FE3A46099BFEF753FE074607220991FF
:1018200052078C4B31462846FEF752FE0791009036
:10183000894A884B38460999FEF74AFE07460191C6
:10184000864A874B31462846FEF742FE3A46019BC0
:10185000FEF78CFD834B7B440F9A9B181A685B68DC
:10186000FEF784FD029009910398FEF7CFFC0591E5
:101870000490099B029A07990098FEF777FD7A4B2E
:101880007B440F9A9B181A685B6817460393FEF710
:101890006DFD059B049AFEF769FD0E462846059BE3
:1018A000049AFEF707FE3A46039BFEF703FE079BEA
:1018B000009AFEF7FFFD099B029AFEF701FE024621
:1018C0000B46199900200C900F461898FEF700FE61
:1018D000029104903B460C9A19991898FEF7EAFD7C
:1018E0002A463346FEF7F4FD029B049AFEF73EFDBE
:1018F00009910E902A46334639460C98FEF7E8FDCA
:1019000006460F46099B0E9AFEF730FD574A0D46D4
:10191000914220DB5242AA18024310D132463B4684
:10192000FEF7C8FD04900391514A524B09990E9855
:10193000FEF71CFD039B049AFEF748FE1ED2022010
:10194000FFF74EFBFFF728FB49004908E20FD207DB
:1019500011431BB0F0BD6A00474B52089A420DD3A9
:10196000464AAA18024300D0CBE532463B46FEF772
:10197000A1FD099B0E9AFEF729FEF5D96800002308
:1019800040082C490393020D3D4B5218984223DD29
:1019900001200005521CD04042195000400D401853
:1019A00038497944096813468C463749C1408B430E
:1019B00012030121120B090551181422101AC140FB
:1019C0000391002D01DA48420390624630463946C1
:1019D000FEF770FD06460F4632463B4609990E98C3
:1019E000FEF7C4FC00252A46284B28460591FEF741
:1019F0006FFD07910C90264A264B28460599FEF765
:101A000067FD0091029032463B4628460599FEF755
:101A100051FD099B0E9AFEF753FD1F4A1F4BFEF71F
:101A200057FD009B029AFEF7A1FC07460B460246B3
:101A3000099135E001FCFFFF0000F03F8E980300A4
:101A40007AB60B0066050000A8050000D20400006D
:101A50000000084009C7EE3FFD033ADCF5015B14C6
:101A6000E02F3EBEA60300006C0300000000904083
:101A7000FE822B654715973C00CC904000346F3FA9
:101A80000000E03FC2020000FFFF0F00432EE63FD0
:101A9000396CA80C615C20BEEF39FAFE422EE63F9D
:101AA00007990C98FEF762FC05460E46079B0C9AB8
:101AB000FEF700FD3A46099BFEF702FD09912A4612
:101AC00033460E9010461946FEF702FD07460246C1
:101AD0002F480B46059105217844FFF7F1F93A4666
:101AE000059BFEF7F5FC2A463346FEF7E9FC074660
:101AF000019128463146099B0E9AFEF7E9FC099BA5
:101B00000E9AFEF733FC012304910C9000229B07F0
:101B100038460199FEF7CEFC05910E903A462846CC
:101B20003146019BFEF7D4FC059B0E9AFEF7F6FAB0
:101B3000049B0C9AFEF7BEFC2A463346FEF7BAFC1D
:101B40000022144BFEF7BCFC064603980D46000528
:101B500041190915002912DC30462946039AFEF77F
:101B60001FFDFFF797F9042801D1FFF71FFA304650
:101B70002946039AFEF714FD064601E004E0291801
:101B80000B46324621460898FEF7A2FC1BB0F0BD7A
:101B9000640100000000F03FF8B506460C46FEF771
:101BA0005EFD051E0F4600D00120014349000B4891
:101BB0004908411AC90F0DD0002E01D0012100E0C3
:101BC00000210C4361004908401AC00F02D10120D6
:101BD000FFF706FA28463946F8BD00000000F07FFE
:101BE000000000000000F03F000000000000F83F8F
:101BF00000000000000000000000004003B8E23FC9
:101C0000000000000000000006D0CF43EBFD4C3E7A
:101C1000033333333333E33FFFAB6FDBB66DDB3F6F
:101C20004D268F515555D53F01411DA96074D13FB7
:101C300065DBC9934A86CD3FEF4E454A287ECA3FB1
:101C40003E5555555555C53F93BDBE166CC166BF33
:101C50002CDE25AF6A56113FF16BD2C541BDBBBE2C
:101C6000D0A4BE726937663E00000000000000008C
:101C7000901C00100000002048000000C00F001061
:101C8000D81C00104800002000020000D00F0010F7
:101C9000020001000000000000C20100000000007E
:101CA000000000200500000000000000000300000C
:101CB0000000000000000000000000000000000024
:101CC00000000000000000000000000000E1F50539
:081CD00000E1F5050000000031
:04000005100000C126
:00000001FF

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html><head>
<title>Static Call Graph - [.\Objects\ENS001_BASIC_PRJ.axf]</title></head>
<body><HR>
<H1>Static Call Graph for image .\Objects\ENS001_BASIC_PRJ.axf</H1><HR>
<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060750: Last Updated: Wed Aug 13 16:25:22 2025
<BR><P>
<H3>Maximum Stack Usage = 352 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
Call chain for Maximum Stack Depth:</H3>
main &rArr; ClockInit &rArr; ClockInitSet &rArr; pow &rArr; __kernel_poly &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; __aeabi_llsl
<P>
<H3>
Mutually Recursive functions
</H3> <LI><a href="#[1]">NMI_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1]">NMI_Handler</a><BR>
<LI><a href="#[2]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[2]">HardFault_Handler</a><BR>
<LI><a href="#[3]">SVC_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[3]">SVC_Handler</a><BR>
<LI><a href="#[4]">PendSV_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[4]">PendSV_Handler</a><BR>
<LI><a href="#[5]">SysTick_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[5]">SysTick_Handler</a><BR>
<LI><a href="#[10]">ADC_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[10]">ADC_Handler</a><BR>
</UL>
<P>
<H3>
Function Pointers
</H3><UL>
<LI><a href="#[10]">ADC_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[f]">CHARGER_END_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[e]">CHARGER_OK_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[8]">COMP0_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[9]">COMP1_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[1d]">DUALTIMER_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[a]">GPIO0_7_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[c]">GPIO16_23_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[b]">GPIO8_15_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[2]">HardFault_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[17]">I2C0_Error_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[16]">I2C0_Event_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[19]">I2C1_Error_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[18]">I2C1_Event_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[11]">LCD_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[6]">LVD_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[d]">MTP_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[1]">NMI_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[1e]">OVER_TEMP_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[1a]">PWM_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[4]">PendSV_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[7]">RTC_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[0]">Reset_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[14]">SPI0_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[15]">SPI1_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[3]">SVC_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[5]">SysTick_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[21]">SystemInit</a> from system_cmsdk_cm0.o(i.SystemInit) referenced from startup_cmsdk_cm0.o(.text)
<LI><a href="#[1b]">TIMER0_Handler</a> from ens1_timer.o(i.TIMER0_Handler) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[1c]">TIMER1_Handler</a> from ens1_timer.o(i.TIMER1_Handler) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[12]">UART0_Handler</a> from ens1_uart.o(i.UART0_Handler) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[13]">UART1_Handler</a> from ens1_uart.o(i.UART1_Handler) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[1f]">WG_DRV_Handler</a> from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET)
<LI><a href="#[22]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from startup_cmsdk_cm0.o(.text)
<LI><a href="#[23]">fputc</a> from retarget.o(i.fputc) referenced from printf1.o(i.__0printf$1)
<LI><a href="#[20]">main</a> from mian.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
</UL>
<P>
<H3>
Global Symbols
</H3>
<P><STRONG><a name="[22]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(.text)
</UL>
<P><STRONG><a name="[5f]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
<P><STRONG><a name="[24]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
<BR><BR>[Calls]<UL><LI><a href="#[25]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>
<P><STRONG><a name="[34]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
<BR><BR>[Called By]<UL><LI><a href="#[25]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>
<P><STRONG><a name="[60]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
<P><STRONG><a name="[61]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
<P><STRONG><a name="[62]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
<P><STRONG><a name="[63]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
<P><STRONG><a name="[64]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[3]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SVC_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[4]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PendSV_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[5]"></a>SysTick_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[10]"></a>ADC_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[10]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[10]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[f]"></a>CHARGER_END_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[e]"></a>CHARGER_OK_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[8]"></a>COMP0_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[9]"></a>COMP1_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[1d]"></a>DUALTIMER_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[a]"></a>GPIO0_7_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[c]"></a>GPIO16_23_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[b]"></a>GPIO8_15_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[17]"></a>I2C0_Error_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[16]"></a>I2C0_Event_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[19]"></a>I2C1_Error_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[18]"></a>I2C1_Event_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[11]"></a>LCD_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[6]"></a>LVD_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[d]"></a>MTP_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[1e]"></a>OVER_TEMP_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[1a]"></a>PWM_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[7]"></a>RTC_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[14]"></a>SPI0_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[15]"></a>SPI1_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[1f]"></a>WG_DRV_Handler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[65]"></a>__aeabi_uidiv</STRONG> (Thumb, 0 bytes, Stack size 12 bytes, uidiv.o(.text), UNUSED)
<P><STRONG><a name="[3f]"></a>__aeabi_uidivmod</STRONG> (Thumb, 44 bytes, Stack size 12 bytes, uidiv.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = __aeabi_uidivmod
</UL>
<BR>[Called By]<UL><LI><a href="#[1b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Handler
<LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Init
<LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Init
<LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_core
</UL>
<P><STRONG><a name="[26]"></a>__aeabi_ddiv</STRONG> (Thumb, 234 bytes, Stack size 40 bytes, ddiv.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = __aeabi_ddiv &rArr; _double_round
</UL>
<BR>[Calls]<UL><LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_round
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
<LI><a href="#[37]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ClockInitSet
<LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_invalid
<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_divzero
</UL>
<P><STRONG><a name="[28]"></a>__aeabi_i2d</STRONG> (Thumb, 34 bytes, Stack size 16 bytes, dflti.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = __aeabi_i2d &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[29]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
<LI><a href="#[37]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ClockInitSet
</UL>
<P><STRONG><a name="[2a]"></a>__aeabi_ui2d</STRONG> (Thumb, 24 bytes, Stack size 16 bytes, dfltui.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = __aeabi_ui2d &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[29]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
</UL>
<BR>[Called By]<UL><LI><a href="#[37]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ClockInitSet
</UL>
<P><STRONG><a name="[2b]"></a>__aeabi_d2uiz</STRONG> (Thumb, 50 bytes, Stack size 8 bytes, dfixui.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_d2uiz &rArr; __aeabi_llsr
</UL>
<BR>[Calls]<UL><LI><a href="#[2c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsr
</UL>
<BR>[Called By]<UL><LI><a href="#[37]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ClockInitSet
</UL>
<P><STRONG><a name="[2c]"></a>__aeabi_llsr</STRONG> (Thumb, 34 bytes, Stack size 8 bytes, llushr.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_llsr
</UL>
<BR>[Called By]<UL><LI><a href="#[2b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_d2uiz
<LI><a href="#[35]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_dsqrt
<LI><a href="#[29]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
</UL>
<P><STRONG><a name="[66]"></a>_ll_ushift_r</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, llushr.o(.text), UNUSED)
<P><STRONG><a name="[67]"></a>__I$use$fp</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, iusefp.o(.text), UNUSED)
<P><STRONG><a name="[27]"></a>_double_round</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, depilogue.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _double_round
</UL>
<BR>[Called By]<UL><LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
<LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
<LI><a href="#[35]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_dsqrt
<LI><a href="#[29]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
</UL>
<P><STRONG><a name="[29]"></a>_double_epilogue</STRONG> (Thumb, 164 bytes, Stack size 48 bytes, depilogue.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[2e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsl
<LI><a href="#[2d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__ARM_clz
<LI><a href="#[2c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsr
<LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_round
</UL>
<BR>[Called By]<UL><LI><a href="#[33]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
<LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
<LI><a href="#[2a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2d
<LI><a href="#[28]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_i2d
</UL>
<P><STRONG><a name="[2f]"></a>__aeabi_dadd</STRONG> (Thumb, 328 bytes, Stack size 48 bytes, dadd.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = __aeabi_dadd &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[30]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_lasr
<LI><a href="#[2e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsl
<LI><a href="#[29]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
<LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_round
</UL>
<BR>[Called By]<UL><LI><a href="#[31]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dsub
<LI><a href="#[32]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_drsub
<LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
<LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__kernel_poly
<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_infnan2
</UL>
<P><STRONG><a name="[31]"></a>__aeabi_dsub</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = __aeabi_dsub &rArr; __aeabi_dadd &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[32]"></a>__aeabi_drsub</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = __aeabi_drsub &rArr; __aeabi_dadd &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[33]"></a>__aeabi_dmul</STRONG> (Thumb, 202 bytes, Stack size 72 bytes, dmul.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = __aeabi_dmul &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[29]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
<LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__kernel_poly
</UL>
<P><STRONG><a name="[57]"></a>__ARM_scalbn</STRONG> (Thumb, 44 bytes, Stack size 16 bytes, dscalb.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __ARM_scalbn
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_underflow
<LI><a href="#[56]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_overflow
</UL>
<P><STRONG><a name="[68]"></a>scalbn</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, dscalb.o(.text), UNUSED)
<P><STRONG><a name="[5d]"></a>__aeabi_cdrcmple</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, cdrcmple.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[25]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[34]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main_after_scatterload
</UL>
<BR>[Called By]<UL><LI><a href="#[24]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_main_scatterload
</UL>
<P><STRONG><a name="[69]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
<P><STRONG><a name="[2e]"></a>__aeabi_llsl</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, llshl.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_llsl
</UL>
<BR>[Called By]<UL><LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
<LI><a href="#[29]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
</UL>
<P><STRONG><a name="[6a]"></a>_ll_shift_l</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, llshl.o(.text), UNUSED)
<P><STRONG><a name="[30]"></a>__aeabi_lasr</STRONG> (Thumb, 38 bytes, Stack size 8 bytes, llsshr.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_lasr
</UL>
<BR>[Called By]<UL><LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
</UL>
<P><STRONG><a name="[6b]"></a>_ll_sshift_r</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, llsshr.o(.text), UNUSED)
<P><STRONG><a name="[35]"></a>_dsqrt</STRONG> (Thumb, 162 bytes, Stack size 32 bytes, dsqrt.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = _dsqrt &rArr; __aeabi_llsr
</UL>
<BR>[Calls]<UL><LI><a href="#[2c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_llsr
<LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_round
</UL>
<BR>[Called By]<UL><LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;sqrt
</UL>
<P><STRONG><a name="[45]"></a>CMSDK_timer_Init</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, ens1_timer.o(i.CMSDK_timer_Init))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = CMSDK_timer_Init
</UL>
<BR>[Called By]<UL><LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Init
</UL>
<P><STRONG><a name="[36]"></a>ClockInit</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, ens1_clock.o(i.ClockInit))
<BR><BR>[Stack]<UL><LI>Max Depth = 336<LI>Call Chain = ClockInit &rArr; ClockInitSet &rArr; pow &rArr; __kernel_poly &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[37]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ClockInitSet
</UL>
<BR>[Called By]<UL><LI><a href="#[20]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[37]"></a>ClockInitSet</STRONG> (Thumb, 348 bytes, Stack size 48 bytes, ens1_clock.o(i.ClockInitSet))
<BR><BR>[Stack]<UL><LI>Max Depth = 328<LI>Call Chain = ClockInitSet &rArr; pow &rArr; __kernel_poly &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
<LI><a href="#[2a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ui2d
<LI><a href="#[28]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_i2d
<LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
<LI><a href="#[2b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_d2uiz
</UL>
<BR>[Called By]<UL><LI><a href="#[36]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ClockInit
</UL>
<P><STRONG><a name="[3a]"></a>GPIO_AltFunction</STRONG> (Thumb, 86 bytes, Stack size 8 bytes, ens1_gpio.o(i.GPIO_AltFunction))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = GPIO_AltFunction
</UL>
<BR>[Called By]<UL><LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Init
<LI><a href="#[39]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_IO_Init
</UL>
<P><STRONG><a name="[3c]"></a>GPIO_GetOutputValue</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, ens1_gpio.o(i.GPIO_GetOutputValue))
<BR><BR>[Called By]<UL><LI><a href="#[3b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Overturn
</UL>
<P><STRONG><a name="[39]"></a>GPIO_IO_Init</STRONG> (Thumb, 342 bytes, Stack size 36 bytes, ens1_gpio.o(i.GPIO_IO_Init))
<BR><BR>[Stack]<UL><LI>Max Depth = 44<LI>Call Chain = GPIO_IO_Init &rArr; GPIO_AltFunction
</UL>
<BR>[Calls]<UL><LI><a href="#[3a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_AltFunction
</UL>
<BR>[Called By]<UL><LI><a href="#[20]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[5a]"></a>GPIO_Output</STRONG> (Thumb, 36 bytes, Stack size 0 bytes, ens1_gpio.o(i.GPIO_Output))
<BR><BR>[Called By]<UL><LI><a href="#[20]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[3b]"></a>GPIO_Overturn</STRONG> (Thumb, 40 bytes, Stack size 4 bytes, ens1_gpio.o(i.GPIO_Overturn))
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = GPIO_Overturn
</UL>
<BR>[Calls]<UL><LI><a href="#[3e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_SetOutput
<LI><a href="#[3d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_ResetOutput
<LI><a href="#[3c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_GetOutputValue
</UL>
<BR>[Called By]<UL><LI><a href="#[1b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Handler
</UL>
<P><STRONG><a name="[3d]"></a>GPIO_ResetOutput</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, ens1_gpio.o(i.GPIO_ResetOutput))
<BR><BR>[Called By]<UL><LI><a href="#[3b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Overturn
</UL>
<P><STRONG><a name="[3e]"></a>GPIO_SetOutput</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, ens1_gpio.o(i.GPIO_SetOutput))
<BR><BR>[Called By]<UL><LI><a href="#[3b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Overturn
</UL>
<P><STRONG><a name="[59]"></a>MTP_init</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, ens1_mtp.o(i.MTP_init))
<BR><BR>[Called By]<UL><LI><a href="#[20]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[42]"></a>PCLK_Enable</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, ens1_clock.o(i.PCLK_Enable))
<BR><BR>[Called By]<UL><LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Init
<LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Init
</UL>
<P><STRONG><a name="[21]"></a>SystemInit</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, system_cmsdk_cm0.o(i.SystemInit))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(.text)
</UL>
<P><STRONG><a name="[1b]"></a>TIMER0_Handler</STRONG> (Thumb, 62 bytes, Stack size 8 bytes, ens1_timer.o(i.TIMER0_Handler))
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = TIMER0_Handler &rArr; __2printf
</UL>
<BR>[Calls]<UL><LI><a href="#[3b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Overturn
<LI><a href="#[40]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__2printf
<LI><a href="#[3f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uidivmod
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[41]"></a>TIMER0_Init</STRONG> (Thumb, 56 bytes, Stack size 16 bytes, ens1_timer.o(i.TIMER0_Init))
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = TIMER0_Init &rArr; __aeabi_uidivmod
</UL>
<BR>[Calls]<UL><LI><a href="#[45]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;CMSDK_timer_Init
<LI><a href="#[46]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NVIC_EnableIRQ
<LI><a href="#[43]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NVIC_DisableIRQ
<LI><a href="#[44]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NVIC_ClearPendingIRQ
<LI><a href="#[42]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PCLK_Enable
<LI><a href="#[3f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uidivmod
</UL>
<BR>[Called By]<UL><LI><a href="#[20]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[1c]"></a>TIMER1_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, ens1_timer.o(i.TIMER1_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[12]"></a>UART0_Handler</STRONG> (Thumb, 108 bytes, Stack size 8 bytes, ens1_uart.o(i.UART0_Handler))
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = UART0_Handler &rArr; UartPutc
</UL>
<BR>[Calls]<UL><LI><a href="#[49]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UartPutc
<LI><a href="#[48]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_INT_TYPE
<LI><a href="#[47]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NVIC_ClearPendingIRQ
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[13]"></a>UART1_Handler</STRONG> (Thumb, 92 bytes, Stack size 8 bytes, ens1_uart.o(i.UART1_Handler))
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = UART1_Handler &rArr; UartPutc
</UL>
<BR>[Calls]<UL><LI><a href="#[49]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UartPutc
<LI><a href="#[48]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_INT_TYPE
<LI><a href="#[47]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NVIC_ClearPendingIRQ
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
</UL>
<P><STRONG><a name="[4e]"></a>UARTLine_THREmpty</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, ens1_uart.o(i.UARTLine_THREmpty))
<BR><BR>[Called By]<UL><LI><a href="#[49]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UartPutc
</UL>
<P><STRONG><a name="[48]"></a>UART_INT_TYPE</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, ens1_uart.o(i.UART_INT_TYPE))
<BR><BR>[Called By]<UL><LI><a href="#[13]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART1_Handler
<LI><a href="#[12]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART0_Handler
</UL>
<P><STRONG><a name="[4a]"></a>UART_ITConfig</STRONG> (Thumb, 84 bytes, Stack size 16 bytes, ens1_uart.o(i.UART_ITConfig))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = UART_ITConfig
</UL>
<BR>[Calls]<UL><LI><a href="#[4c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NVIC_EnableIRQ
<LI><a href="#[4b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NVIC_DisableIRQ
<LI><a href="#[47]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NVIC_ClearPendingIRQ
</UL>
<BR>[Called By]<UL><LI><a href="#[20]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[4d]"></a>UART_Init</STRONG> (Thumb, 164 bytes, Stack size 24 bytes, ens1_uart.o(i.UART_Init))
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = UART_Init &rArr; __aeabi_uidivmod
</UL>
<BR>[Calls]<UL><LI><a href="#[42]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;PCLK_Enable
<LI><a href="#[3a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_AltFunction
<LI><a href="#[3f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uidivmod
</UL>
<BR>[Called By]<UL><LI><a href="#[20]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>
<P><STRONG><a name="[49]"></a>UartPutc</STRONG> (Thumb, 30 bytes, Stack size 4 bytes, ens1_uart.o(i.UartPutc))
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = UartPutc
</UL>
<BR>[Calls]<UL><LI><a href="#[4f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;WRITE_UART_THRBuff
<LI><a href="#[4e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UARTLine_THREmpty
</UL>
<BR>[Called By]<UL><LI><a href="#[23]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fputc
<LI><a href="#[13]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART1_Handler
<LI><a href="#[12]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART0_Handler
</UL>
<P><STRONG><a name="[4f]"></a>WRITE_UART_THRBuff</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, ens1_uart.o(i.WRITE_UART_THRBuff))
<BR><BR>[Called By]<UL><LI><a href="#[49]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UartPutc
</UL>
<P><STRONG><a name="[50]"></a>__0printf$1</STRONG> (Thumb, 24 bytes, Stack size 24 bytes, printf1.o(i.__0printf$1), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[51]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_core
</UL>
<P><STRONG><a name="[6c]"></a>__1printf$1</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printf1.o(i.__0printf$1), UNUSED)
<P><STRONG><a name="[40]"></a>__2printf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printf1.o(i.__0printf$1))
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = __2printf
</UL>
<BR>[Called By]<UL><LI><a href="#[1b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Handler
</UL>
<P><STRONG><a name="[2d]"></a>__ARM_clz</STRONG> (Thumb, 46 bytes, Stack size 0 bytes, depilogue.o(i.__ARM_clz))
<BR><BR>[Called By]<UL><LI><a href="#[29]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_double_epilogue
</UL>
<P><STRONG><a name="[5e]"></a>__ARM_fpclassify</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, fpclassify.o(i.__ARM_fpclassify))
<BR><BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[52]"></a>__kernel_poly</STRONG> (Thumb, 172 bytes, Stack size 24 bytes, poly.o(i.__kernel_poly))
<BR><BR>[Stack]<UL><LI>Max Depth = 152<LI>Call Chain = __kernel_poly &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[33]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
<LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[53]"></a>__mathlib_dbl_divzero</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_divzero))
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = __mathlib_dbl_divzero &rArr; __aeabi_ddiv &rArr; _double_round
</UL>
<BR>[Calls]<UL><LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[54]"></a>__mathlib_dbl_infnan2</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_infnan2))
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = __mathlib_dbl_infnan2 &rArr; __aeabi_dadd &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[55]"></a>__mathlib_dbl_invalid</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_invalid))
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = __mathlib_dbl_invalid &rArr; __aeabi_ddiv &rArr; _double_round
</UL>
<BR>[Calls]<UL><LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[56]"></a>__mathlib_dbl_overflow</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_overflow))
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = __mathlib_dbl_overflow &rArr; __ARM_scalbn
</UL>
<BR>[Calls]<UL><LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__ARM_scalbn
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[58]"></a>__mathlib_dbl_underflow</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_underflow))
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = __mathlib_dbl_underflow &rArr; __ARM_scalbn
</UL>
<BR>[Calls]<UL><LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__ARM_scalbn
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P><STRONG><a name="[6d]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
<P><STRONG><a name="[6e]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
<P><STRONG><a name="[6f]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
<P><STRONG><a name="[5b]"></a>__set_errno</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, errno.o(i.__set_errno))
<BR><BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;sqrt
</UL>
<P><STRONG><a name="[23]"></a>fputc</STRONG> (Thumb, 16 bytes, Stack size 16 bytes, retarget.o(i.fputc))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = fputc &rArr; UartPutc
</UL>
<BR>[Calls]<UL><LI><a href="#[49]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UartPutc
</UL>
<BR>[Address Reference Count : 1]<UL><LI> printf1.o(i.__0printf$1)
</UL>
<P><STRONG><a name="[20]"></a>main</STRONG> (Thumb, 64 bytes, Stack size 16 bytes, mian.o(i.main))
<BR><BR>[Stack]<UL><LI>Max Depth = 352<LI>Call Chain = main &rArr; ClockInit &rArr; ClockInitSet &rArr; pow &rArr; __kernel_poly &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[4d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Init
<LI><a href="#[4a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_ITConfig
<LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Init
<LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MTP_init
<LI><a href="#[5a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_Output
<LI><a href="#[39]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;GPIO_IO_Init
<LI><a href="#[36]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ClockInit
</UL>
<BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
</UL>
<P><STRONG><a name="[38]"></a>pow</STRONG> (Thumb, 2548 bytes, Stack size 128 bytes, pow.o(i.pow))
<BR><BR>[Stack]<UL><LI>Max Depth = 280<LI>Call Chain = pow &rArr; __kernel_poly &rArr; __aeabi_dmul &rArr; _double_epilogue &rArr; __aeabi_llsl
</UL>
<BR>[Calls]<UL><LI><a href="#[31]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dsub
<LI><a href="#[32]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_drsub
<LI><a href="#[33]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dmul
<LI><a href="#[2f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_dadd
<LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_cdrcmple
<LI><a href="#[57]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__ARM_scalbn
<LI><a href="#[28]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_i2d
<LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_ddiv
<LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__set_errno
<LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;sqrt
<LI><a href="#[52]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__kernel_poly
<LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__ARM_fpclassify
<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_underflow
<LI><a href="#[56]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_overflow
<LI><a href="#[55]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_invalid
<LI><a href="#[54]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_infnan2
<LI><a href="#[53]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__mathlib_dbl_divzero
</UL>
<BR>[Called By]<UL><LI><a href="#[37]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ClockInitSet
</UL>
<P><STRONG><a name="[5c]"></a>sqrt</STRONG> (Thumb, 66 bytes, Stack size 24 bytes, sqrt.o(i.sqrt))
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = sqrt &rArr; _dsqrt &rArr; __aeabi_llsr
</UL>
<BR>[Calls]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__set_errno
<LI><a href="#[35]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_dsqrt
</UL>
<BR>[Called By]<UL><LI><a href="#[38]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;pow
</UL>
<P>
<H3>
Local Symbols
</H3>
<P><STRONG><a name="[47]"></a>NVIC_ClearPendingIRQ</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, ens1_uart.o(i.NVIC_ClearPendingIRQ))
<BR><BR>[Called By]<UL><LI><a href="#[13]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART1_Handler
<LI><a href="#[12]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART0_Handler
<LI><a href="#[4a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_ITConfig
</UL>
<P><STRONG><a name="[4b]"></a>NVIC_DisableIRQ</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, ens1_uart.o(i.NVIC_DisableIRQ))
<BR><BR>[Called By]<UL><LI><a href="#[4a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_ITConfig
</UL>
<P><STRONG><a name="[4c]"></a>NVIC_EnableIRQ</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, ens1_uart.o(i.NVIC_EnableIRQ))
<BR><BR>[Called By]<UL><LI><a href="#[4a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_ITConfig
</UL>
<P><STRONG><a name="[44]"></a>NVIC_ClearPendingIRQ</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, ens1_timer.o(i.NVIC_ClearPendingIRQ))
<BR><BR>[Called By]<UL><LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Init
</UL>
<P><STRONG><a name="[43]"></a>NVIC_DisableIRQ</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, ens1_timer.o(i.NVIC_DisableIRQ))
<BR><BR>[Called By]<UL><LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Init
</UL>
<P><STRONG><a name="[46]"></a>NVIC_EnableIRQ</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, ens1_timer.o(i.NVIC_EnableIRQ))
<BR><BR>[Called By]<UL><LI><a href="#[41]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER0_Init
</UL>
<P><STRONG><a name="[51]"></a>_printf_core</STRONG> (Thumb, 332 bytes, Stack size 88 bytes, printf1.o(i._printf_core), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[3f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uidivmod
</UL>
<BR>[Called By]<UL><LI><a href="#[50]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__0printf$1
</UL>
<P>
<H3>
Undefined Global Symbols
</H3><HR></body></html>

14
Objects/ENS001_BASIC_PRJ.lnp Normal file
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@ -0,0 +1,14 @@
--cpu Cortex-M0
".\objects\mian.o"
".\objects\ens1_uart.o"
".\objects\ens1_gpio.o"
".\objects\ens1_mtp.o"
".\objects\ens1_clock.o"
".\objects\retarget.o"
".\objects\ens1_timer.o"
".\objects\system_cmsdk_cm0.o"
".\objects\startup_cmsdk_cm0.o"
--library_type=microlib --strict --scatter ".\Objects\ENS001_BASIC_PRJ.sct"
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\Listings\ENS001_BASIC_PRJ.map" -o .\Objects\ENS001_BASIC_PRJ.axf

16
Objects/ENS001_BASIC_PRJ.sct Normal file
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@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x10000000 0x00008000 { ; load region size_region
ER_IROM1 0x10000000 0x00008000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
}

104
Objects/ENS001_BASIC_PRJ_ENS001_BASIC_PRJ.dep Normal file
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@ -0,0 +1,104 @@
Dependencies for Project 'ENS001_BASIC_PRJ', Target 'ENS001_BASIC_PRJ': (DO NOT MODIFY !)
CompilerVersion: 5060750::V5.06 update 6 (build 750)::.\ARM_Compiler_5.06u7
F (.\USER\mian.c)(0x689C4ADA)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\mian.o --omf_browse .\objects\mian.crf --depend .\objects\mian.d)
I (USER\my_header.h)(0x689C4B9B)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E)
I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8)
I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E)
I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6)
I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6)
I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6)
I (.\USER\my_header.h)(0x689C4B9B)
I (.\FWLIB\include\ENS1_MTP.h)(0x65605CD6)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdlib.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\string.h)(0x599ECD2C)
I (.\FWLIB\include\ENS1_CLOCK.h)(0x68358097)
I (.\FWLIB\include\ENS1_UART.h)(0x689C4BC8)
I (.\FWLIB\include\ENS1_GPIO.h)(0x656546CE)
F (.\FWLIB\source\ENS1_UART.c)(0x689C4BE6)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_uart.o --omf_browse .\objects\ens1_uart.crf --depend .\objects\ens1_uart.d)
I (.\USER\my_header.h)(0x689C4B9B)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E)
I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8)
I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E)
I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6)
I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6)
I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6)
I (.\FWLIB\include\ENS1_UART.h)(0x689C4BC8)
I (.\FWLIB\include\ENS1_CLOCK.h)(0x68358097)
I (.\FWLIB\include\ENS1_GPIO.h)(0x656546CE)
F (.\FWLIB\source\ENS1_GPIO.c)(0x689C4B85)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_gpio.o --omf_browse .\objects\ens1_gpio.crf --depend .\objects\ens1_gpio.d)
I (.\USER\my_header.h)(0x689C4B9B)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E)
I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8)
I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E)
I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6)
I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6)
I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6)
I (.\FWLIB\include\ENS1_GPIO.h)(0x656546CE)
F (.\FWLIB\source\ENS1_MTP.c)(0x680B4E85)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_mtp.o --omf_browse .\objects\ens1_mtp.crf --depend .\objects\ens1_mtp.d)
I (.\FWLIB\include\ENS1_MTP.h)(0x65605CD6)
I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8)
I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E)
I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6)
I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdlib.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\string.h)(0x599ECD2C)
I (.\USER\my_header.h)(0x689C4B9B)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E)
I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6)
F (.\FWLIB\source\ENS1_CLOCK.c)(0x68358347)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_clock.o --omf_browse .\objects\ens1_clock.crf --depend .\objects\ens1_clock.d)
I (.\FWLIB\include\ENS1_CLOCK.h)(0x68358097)
I (.\USER\my_header.h)(0x689C4B9B)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E)
I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8)
I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E)
I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6)
I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6)
I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6)
F (.\FWLIB\source\retarget.c)(0x6565495A)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\retarget.o --omf_browse .\objects\retarget.crf --depend .\objects\retarget.d)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\time.h)(0x599ECD2E)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\rt_misc.h)(0x599ECD2E)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stddef.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E)
I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8)
I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6)
I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6)
F (.\FWLIB\source\ENS1_TIMER.c)(0x689C4BF1)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_timer.o --omf_browse .\objects\ens1_timer.crf --depend .\objects\ens1_timer.d)
I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6)
I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8)
I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E)
I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6)
I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6)
I (.\USER\my_header.h)(0x689C4B9B)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E)
I (.\FWLIB\include\ENS_CURRENT_CALIBRATION.h)(0x6566A27C)
I (.\FWLIB\include\ENS1_CLOCK.h)(0x68358097)
F (.\CORE\system_CMSDK_CM0.c)(0x63648DE6)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\system_cmsdk_cm0.o --omf_browse .\objects\system_cmsdk_cm0.crf --depend .\objects\system_cmsdk_cm0.d)
I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E)
I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8)
I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6)
I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6)
I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6)
F (.\CORE\ARM\startup_CMSDK_CM0.s)(0x6365EF56)(--cpu Cortex-M0 --li -g --apcs=interwork --pd "__MICROLIB SETA 1" -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include --pd "__UVISION_VERSION SETA 538" --pd "ARMCM0 SETA 1" --list .\listings\startup_cmsdk_cm0.lst --xref -o .\objects\startup_cmsdk_cm0.o --depend .\objects\startup_cmsdk_cm0.d)

15
Objects/ENS001_BASIC_PRJ_sct.Bak Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x10000000 0x00008000 { ; load region size_region
ER_IROM1 0x10000000 0x00008000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
}

2
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[EXTDLL]
Count=0

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12
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.\objects\ens1_anac.o: FWLIB\source\ENS1_ANAC.c
.\objects\ens1_anac.o: .\FWLIB\include\ens1_anac.h
.\objects\ens1_anac.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens1_anac.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_anac.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_anac.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens1_anac.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_anac.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_anac.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_anac.o: .\USER\my_header.h
.\objects\ens1_anac.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
.\objects\ens1_anac.o: .\FWLIB\include\ENS1_GPIO.h

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.\objects\ens1_boost.o: FWLIB\source\ENS1_BOOST.c
.\objects\ens1_boost.o: .\FWLIB\include\ENS1_BOOST.h
.\objects\ens1_boost.o: .\USER\my_header.h
.\objects\ens1_boost.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens1_boost.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
.\objects\ens1_boost.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_boost.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_boost.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens1_boost.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_boost.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_boost.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_boost.o: .\FWLIB\include\ENS1_CLOCK.h

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Objects/ens1_clock.d Normal file
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.\objects\ens1_clock.o: FWLIB\source\ENS1_CLOCK.c
.\objects\ens1_clock.o: .\FWLIB\include\ENS1_CLOCK.h
.\objects\ens1_clock.o: .\USER\my_header.h
.\objects\ens1_clock.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h
.\objects\ens1_clock.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h
.\objects\ens1_clock.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_clock.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_clock.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h
.\objects\ens1_clock.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_clock.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_clock.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_clock.o: .\FWLIB\include\ENS1_TIMER.h
.\objects\ens1_clock.o: .\USER\my_header.h

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.\objects\ens1_exti.o: FWLIB\source\ENS1_EXTI.c
.\objects\ens1_exti.o: .\FWLIB\include\ENS1_EXTI.h
.\objects\ens1_exti.o: .\USER\my_header.h
.\objects\ens1_exti.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens1_exti.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
.\objects\ens1_exti.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_exti.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_exti.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens1_exti.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_exti.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_exti.o: .\CORE\INCLUDE\system_CMSDK_CM0.h

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Objects/ens1_gpio.d Normal file
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.\objects\ens1_gpio.o: FWLIB\source\ENS1_GPIO.c
.\objects\ens1_gpio.o: .\USER\my_header.h
.\objects\ens1_gpio.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h
.\objects\ens1_gpio.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h
.\objects\ens1_gpio.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_gpio.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_gpio.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h
.\objects\ens1_gpio.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_gpio.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_gpio.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_gpio.o: .\FWLIB\include\ENS1_TIMER.h
.\objects\ens1_gpio.o: .\USER\my_header.h
.\objects\ens1_gpio.o: .\FWLIB\include\ENS1_GPIO.h

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.\objects\ens1_iic.o: FWLIB\source\ENS1_IIC.c
.\objects\ens1_iic.o: .\FWLIB\include\ENS1_IIC.h
.\objects\ens1_iic.o: .\USER\my_header.h
.\objects\ens1_iic.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens1_iic.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
.\objects\ens1_iic.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_iic.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_iic.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens1_iic.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_iic.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_iic.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_iic.o: .\FWLIB\include\ens1_uart.h
.\objects\ens1_iic.o: .\FWLIB\include\ENS1_CLOCK.h
.\objects\ens1_iic.o: .\FWLIB\include\ENS1_GPIO.h

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Objects/ens1_mtp.d Normal file
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.\objects\ens1_mtp.o: FWLIB\source\ENS1_MTP.c
.\objects\ens1_mtp.o: .\FWLIB\include\ENS1_MTP.h
.\objects\ens1_mtp.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_mtp.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h
.\objects\ens1_mtp.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_mtp.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_mtp.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdlib.h
.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\string.h
.\objects\ens1_mtp.o: .\USER\my_header.h
.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h
.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h
.\objects\ens1_mtp.o: .\FWLIB\include\ENS1_TIMER.h
.\objects\ens1_mtp.o: .\USER\my_header.h

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.\objects\ens1_pwm.o: FWLIB\source\ENS1_PWM.c
.\objects\ens1_pwm.o: .\FWLIB\include\ens1_pwm.h
.\objects\ens1_pwm.o: .\USER\my_header.h
.\objects\ens1_pwm.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens1_pwm.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
.\objects\ens1_pwm.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_pwm.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_pwm.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens1_pwm.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_pwm.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_pwm.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_pwm.o: .\FWLIB\include\ENS1_CLOCK.h

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.\objects\ens1_spi.o: FWLIB\source\ENS1_SPI.c
.\objects\ens1_spi.o: .\FWLIB\include\ENS1_SPI.h
.\objects\ens1_spi.o: .\USER\my_header.h
.\objects\ens1_spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens1_spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
.\objects\ens1_spi.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_spi.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens1_spi.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_spi.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_spi.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_spi.o: .\FWLIB\include\ENS1_GPIO.h

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.\objects\ens1_timer.o: FWLIB\source\ENS1_TIMER.c
.\objects\ens1_timer.o: .\FWLIB\include\ENS1_TIMER.h
.\objects\ens1_timer.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_timer.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_timer.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h
.\objects\ens1_timer.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_timer.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_timer.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_timer.o: .\USER\my_header.h
.\objects\ens1_timer.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h
.\objects\ens1_timer.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h
.\objects\ens1_timer.o: .\FWLIB\include\ENS1_TIMER.h
.\objects\ens1_timer.o: .\FWLIB\include\ENS_CURRENT_CALIBRATION.h
.\objects\ens1_timer.o: .\FWLIB\include\ENS1_CLOCK.h

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.\objects\ens1_uart.o: FWLIB\source\ENS1_UART.c
.\objects\ens1_uart.o: .\USER\my_header.h
.\objects\ens1_uart.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h
.\objects\ens1_uart.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h
.\objects\ens1_uart.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_uart.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_uart.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h
.\objects\ens1_uart.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_uart.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_uart.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_uart.o: .\FWLIB\include\ENS1_TIMER.h
.\objects\ens1_uart.o: .\USER\my_header.h
.\objects\ens1_uart.o: .\FWLIB\include\ENS1_UART.h
.\objects\ens1_uart.o: .\FWLIB\include\ENS1_CLOCK.h
.\objects\ens1_uart.o: .\FWLIB\include\ENS1_GPIO.h

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.\objects\ens1_watchdog.o: FWLIB\source\ENS1_WATCHDOG.c
.\objects\ens1_watchdog.o: .\FWLIB\include\ENS1_WATCHDOG.h
.\objects\ens1_watchdog.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens1_watchdog.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens1_watchdog.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens1_watchdog.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens1_watchdog.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens1_watchdog.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens1_watchdog.o: .\FWLIB\include\ENS1_CLOCK.h
.\objects\ens1_watchdog.o: .\USER\my_header.h
.\objects\ens1_watchdog.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens1_watchdog.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h

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.\objects\ens_adc.o: FWLIB\source\ENS_ADC.c
.\objects\ens_adc.o: .\FWLIB\include\ENS1_ADC.h
.\objects\ens_adc.o: .\USER\my_header.h
.\objects\ens_adc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens_adc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
.\objects\ens_adc.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens_adc.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens_adc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens_adc.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens_adc.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens_adc.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens_adc.o: .\FWLIB\include\ENS1_GPIO.h

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.\objects\ens_current_calibration.o: FWLIB\source\ENS_CURRENT_CALIBRATION.c
.\objects\ens_current_calibration.o: .\FWLIB\include\ENS_CURRENT_CALIBRATION.h
.\objects\ens_current_calibration.o: .\USER\my_header.h
.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h
.\objects\ens_current_calibration.o: .\CORE\INCLUDE\CMSDK_CM0.h
.\objects\ens_current_calibration.o: .\CORE\INCLUDE\core_cm0.h
.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
.\objects\ens_current_calibration.o: .\CORE\INCLUDE\core_cmInstr.h
.\objects\ens_current_calibration.o: .\CORE\INCLUDE\core_cmFunc.h
.\objects\ens_current_calibration.o: .\CORE\INCLUDE\system_CMSDK_CM0.h
.\objects\ens_current_calibration.o: .\FWLIB\include\ENS1_TIMER.h
.\objects\ens_current_calibration.o: .\FWLIB\include\ENS1_MTP.h
.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
.\objects\ens_current_calibration.o: .\FWLIB\include\ENS1_UART.h
.\objects\ens_current_calibration.o: .\FWLIB\include\ENS1_CLOCK.h

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