diff --git a/Bin/ENS001_BASIC_PRJ.bin b/Bin/ENS001_BASIC_PRJ.bin new file mode 100644 index 0000000..8ac4559 Binary files /dev/null and b/Bin/ENS001_BASIC_PRJ.bin differ diff --git a/CORE/ARM/startup_CMSDK_CM0.s b/CORE/ARM/startup_CMSDK_CM0.s new file mode 100644 index 0000000..7e116f7 --- /dev/null +++ b/CORE/ARM/startup_CMSDK_CM0.s @@ -0,0 +1,240 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000100 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD LVD_Handler ; + DCD RTC_Handler ; + DCD COMP0_Handler ; + DCD COMP1_Handler ; + DCD GPIO0_7_Handler ; + DCD GPIO8_15_Handler ; + DCD GPIO16_23_Handler ; + DCD MTP_Handler ; + DCD CHARGER_OK_Handler ; + DCD CHARGER_END_Handler ; + DCD ADC_Handler ; + DCD LCD_Handler ; + DCD UART0_Handler ; + DCD UART1_Handler ; + DCD SPI0_Handler ; + DCD SPI1_Handler ; + DCD I2C0_Event_Handler ; + DCD I2C0_Error_Handler ; + DCD I2C1_Event_Handler ; + DCD I2C1_Error_Handler ; + DCD PWM_Handler ; + DCD TIMER0_Handler ; + DCD TIMER1_Handler ; + DCD DUALTIMER_Handler ; + DCD OVER_TEMP_Handler ; + DCD WG_DRV_Handler ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT LVD_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT COMP0_Handler [WEAK] + EXPORT COMP1_Handler [WEAK] + EXPORT GPIO0_7_Handler [WEAK] + EXPORT GPIO8_15_Handler [WEAK] + EXPORT GPIO16_23_Handler [WEAK] + EXPORT MTP_Handler [WEAK] + EXPORT CHARGER_OK_Handler [WEAK] + EXPORT CHARGER_END_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT LCD_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT SPI0_Handler [WEAK] + EXPORT SPI1_Handler [WEAK] + EXPORT I2C0_Event_Handler [WEAK] + EXPORT I2C0_Error_Handler [WEAK] + EXPORT I2C1_Event_Handler [WEAK] + EXPORT I2C1_Error_Handler [WEAK] + EXPORT PWM_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_Handler [WEAK] + EXPORT OVER_TEMP_Handler [WEAK] + EXPORT WG_DRV_Handler [WEAK] +LVD_Handler +RTC_Handler +COMP0_Handler +COMP1_Handler +GPIO0_7_Handler +GPIO8_15_Handler +GPIO16_23_Handler +MTP_Handler +CHARGER_OK_Handler +CHARGER_END_Handler +ADC_Handler +LCD_Handler +UART0_Handler +UART1_Handler +SPI0_Handler +SPI1_Handler +I2C0_Event_Handler +I2C0_Error_Handler +I2C1_Event_Handler +I2C1_Error_Handler +PWM_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_Handler +OVER_TEMP_Handler +WG_DRV_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/CORE/GCC/startup_CMSDK_CM0.s b/CORE/GCC/startup_CMSDK_CM0.s new file mode 100644 index 0000000..9f4f92b --- /dev/null +++ b/CORE/GCC/startup_CMSDK_CM0.s @@ -0,0 +1,263 @@ +/**************************************************************************//** + * @file startup_CMSDK_CM0.s + * @brief CMSIS Cortex-M0 Core Device Startup File for + * Device CMSDK_CM0 + * @version V3.01 + * @date 06. March 2012 + * + * @note Should use with GCC for ARM Embedded Processors + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/*****************************************************************************/ +/* startup_CMSDK_CM3.s: Startup file for CMSDK device series */ +/*****************************************************************************/ +/* Version: GNU Tools for ARM Embedded Processors */ +/*****************************************************************************/ + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x200 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + +/* Vector Table */ + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long LVD_Handler /* 16+ 0: LVD Handler */ + .long RTC_Handler /* 16+ 1: RTC Handler */ + .long COMP0_Handler /* 16+ 2: Comp0 Handle */ + .long COMP1_Handler /* 16+ 3: Comp1 Handler */ + .long GPIO0_7_Handler /* 16+ 4: GPIO0_7 Handler */ + .long GPIO8_15_Handler /* 16+ 5: GPIO8_15 Handler */ + .long GPIO16_23_Handler /* 16+ 6: GPIO16_23 Handler */ + .long MTP_Handler /* 16+ 7: MTP Handler */ + .long CHARGER_OK_Handler /* 16+ 8: Charge ok Handler */ + .long CHARGER_END_Handler /* 16+ 9: Charge end Handler */ + .long ADC_Handler /* 16+10: ADC Handler */ + .long LCD_Handler /* 16+11: LCD Handler */ + .long UART0_Handler /* 16+12: UART0 Handler */ + .long UART1_Handler /* 16+13: UART1 Handler */ + .long SPI0_Handler /* 16+14: SPI0 Handler */ + .long SPI1_Handler /* 16+15: SPI1 Handler */ + .long I2C0_Event_Handler /* 16+16: I2C0 Event Handler */ + .long I2C0_Error_Handler /* 16+17: I2C0 Error Handler */ + .long I2C1_Event_Handler /* 16+18: I2C1 Event Handler */ + .long I2C1_Error_Handler /* 16+19: I2C1 Error Handler */ + .long PWM_Handler /* 16+20: PWM Handler */ + .long TIMER0_Handler /* 16+21: Timer 0 Handler */ + .long TIMER1_Handler /* 16+22: Timer 1 Handler */ + .long DUALTIMER_Handler /* 16+23: Dual-Timer Handler */ + .long OVER_TEMP_Handler /* 16+24: over temp Handler */ + .long WG_DRV_Handler /* 16+25: Reserved Handler */ + .long 0 /* 16+26: Reserved Handler */ + .long 0 /* 16+27: Reserved Handler */ + .long 0 /* 16+28: Reserved Handler */ + .long 0 /* 16+29: Reserved Handler */ + .long 0 /* 16+30: Reserved Handler */ + .long 0 /* 16+31: Reserved Handler */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif /* __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + /* bl SystemInit */ + ldr r0,=SystemInit + blx r0 +#endif + + bl _start + + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* System Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + +/* IRQ Handlers */ + + def_default_handler LVD_Handler + def_default_handler RTC_Handler + def_default_handler COMP0_Handler + def_default_handler COMP1_Handler + def_default_handler GPIO0_7_Handler + def_default_handler GPIO8_15_Handler + def_default_handler GPIO16_23_Handler + def_default_handler MTP_Handler + def_default_handler CHARGER_OK_Handler + def_default_handler CHARGER_END_Handler + def_default_handler ADC_Handler + def_default_handler LCD_Handler + def_default_handler UART0_Handler + def_default_handler UART1_Handler + def_default_handler SPI0_Handler + def_default_handler SPI1_Handler + def_default_handler I2C0_Event_Handler + def_default_handler I2C0_Error_Handler + def_default_handler I2C1_Event_Handler + def_default_handler I2C1_Error_Handler + def_default_handler PWM_Handler + def_default_handler TIMER0_Handler + def_default_handler TIMER1_Handler + def_default_handler DUALTIMER_Handler + def_default_handler OVER_TEMP_Handler + def_default_handler WG_DRV_Handler + /* + def_default_handler Default_Handler + .weak DEF_IRQHandler + .set DEF_IRQHandler, Default_Handler + */ + .end + diff --git a/CORE/INCLUDE/CMSDK_CM0.h b/CORE/INCLUDE/CMSDK_CM0.h new file mode 100644 index 0000000..fafc754 --- /dev/null +++ b/CORE/INCLUDE/CMSDK_CM0.h @@ -0,0 +1,1526 @@ +/**************************************************************************//** + * @file CMSDK_CM0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for + * Device CMSDK + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef CMSDK_H +#define CMSDK_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup CMSDK_Definitions CMSDK Definitions + This file defines all structures and symbols for CMSDK: + - registers and bitfields + - peripheral base address + - peripheral ID + - Peripheral definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSDK_CMSIS Device CMSIS Definitions + Configuration of the Cortex-M0 Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + +/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** CMSDK Specific Interrupt Numbers *********************************************************/ + LVD_IRQn = 0, + RTC_IRQn = 1, + COMP0_IRQn = 2, + COMP1_IRQn = 3, + GPIO0_7_IRQn = 4, + GPIO8_15_IRQn = 5, + GPIO16_23_IRQn = 6, + MTP_IRQn = 7, + CHARGER_OK_IRQn = 8, + CHARGER_END_IRQn = 9, + ADC_IRQn = 10, + LCD_IRQn = 11, + UART0_IRQn = 12, + UART1_IRQn = 13, + SPI0_IRQn = 14, + SPI1_IRQn = 15, + I2C0_Event_IRQn = 16, + I2C0_Error_IRQn = 17, + I2C1_Event_IRQn = 18, + I2C1_Error_IRQn = 19, + PWM_IRQn = 20, + TIMER0_IRQn = 21, + TIMER1_IRQn = 22, + DUALTIMER_IRQn = 23, + OVER_TEMP_IRQn = 24, + WG_DRV_IRQn = 25, +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __CM0_REV 0x0000 /*!< Core Revision r0p0 */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ + +/*@}*/ /* end of group CMSDK_CMSIS */ + + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_CMSDK_CM0.h" /* CMSDK System include file */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +/** @addtogroup CMSDK_Peripherals CMSDK Peripherals + CMSDK Device Specific Peripheral registers structures + @{ +*/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +/** @addtogroup CMSDK_UART Universal Asynchronous Receiver/Transmitter + memory mapped structure for CMSDK_UART + @{ +*/ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/) */ + __O uint32_t THR; /*!< Offset: 0x000 Transmitter Holding Register ( /W) */ + }; + __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register (R/W) */ + union { + __I uint32_t IIR; /*!< Offset: 0x008 Interrupt Identification Register (R/) */ + __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ + }; + __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ + __IO uint32_t MCR; /*!< Offset: 0x010 Modem Control Register (R/W) */ + __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/) */ + __I uint32_t MSR; /*!< Offset: 0x018 Modem Status Register (R/) */ + __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ + __IO uint32_t DLL; /*!< Offset: 0x020 Divisor LSB Latch Register (R/W) */ + __IO uint32_t DLH; /*!< Offset: 0x024 Divisor MSB Latch Register (R/W) */ + __I uint32_t FSR; /*!< Offset: 0x028 FIFO Status Register (R/) */ + __I uint32_t DBG; /*!< Offset: 0x02C Debug Signal Register (R/) */ + __IO uint32_t PMU; /*!< Offset: 0x030 Power Management Register (R/W) */ + __IO uint32_t MDR; /*!< Offset: 0x034 Mode Definition Register (R/W) */ + +} CMSDK_UART_TypeDef; + +/* CMSDK_UART Register Definitions */ +#define CMSDK_UART_IER_RLSI_EN_Pos 2 /*!< CMSDK_UART IER: RLSI_EN Position */ +#define CMSDK_UART_IER_RLSI_EN_Msk (0x01ul << CMSDK_UART_IER_RLSI_EN_Pos) /*!< CMSDK_UART IER: RLSI_EN Mask */ + +#define CMSDK_UART_IER_THRE_EN_Pos 1 /*!< CMSDK_UART IER: THRE_EN Position */ +#define CMSDK_UART_IER_THRE_EN_Msk (0x01ul << CMSDK_UART_IER_THRE_EN_Pos) /*!< CMSDK_UART IER: THRE_EN Mask */ + +#define CMSDK_UART_IER_RDAI_EN_Pos 0 /*!< CMSDK_UART IER: RDAI_EN Position */ +#define CMSDK_UART_IER_RDAI_EN_Msk (0x01ul << CMSDK_UART_IER_RDAI_EN_Pos) /*!< CMSDK_UART IER: RDAI_EN Mask */ + +#define CMSDK_UART_IIR_INT_TYPE_Pos 1 /*!< CMSDK_UART IIR: INT_TYPE Position */ +#define CMSDK_UART_IIR_INT_TYPE_Msk (0x07ul << CMSDK_UART_IIR_INT_TYPE_Pos) /*!< CMSDK_UART IIR: INT_TYPE Mask */ + +#define CMSDK_UART_FCR_RX_FIFO_TL_Pos 6 /*!< CMSDK_UART FCR: RX_FIFO_TL Position */ +#define CMSDK_UART_FCR_RX_FIFO_TL_Msk (0x03ul << CMSDK_UART_FCR_RX_FIFO_TL_Pos) /*!< CMSDK_UART FCR: RX_FIFO_TL Mask */ + +#define CMSDK_UART_FCR_DMA_EN_Pos 3 /*!< CMSDK_UART FCR: DMA_EN Position */ +#define CMSDK_UART_FCR_DMA_EN_Msk (0x01ul << CMSDK_UART_FCR_DMA_EN_Pos) /*!< CMSDK_UART FCR: DMA_EN Mask */ + +#define CMSDK_UART_FCR_FIFO_EN_Pos 0 /*!< CMSDK_UART FCR: FIFO_EN Position */ +#define CMSDK_UART_FCR_FIFO_EN_Msk (0x01ul << CMSDK_UART_FCR_FIFO_EN_Pos) /*!< CMSDK_UART FCR: FIFO_EN Mask */ + +#define CMSDK_UART_LCR_BREAK_EN_Pos 6 /*!< CMSDK_UART LCR: BREAK_EN Position */ +#define CMSDK_UART_LCR_BREAK_EN_Msk (0x01ul << CMSDK_UART_LCR_BREAK_EN_Pos) /*!< CMSDK_UART LCR: BREAK_EN Mask */ + +#define CMSDK_UART_LCR_STICK_EN_Pos 5 /*!< CMSDK_UART LCR: STICK_EN Position */ +#define CMSDK_UART_LCR_STICK_EN_Msk (0x01ul << CMSDK_UART_LCR_STICK_EN_Pos) /*!< CMSDK_UART LCR: STICK_EN Mask */ + +#define CMSDK_UART_LCR_EVEN_EN_Pos 4 /*!< CMSDK_UART LCR: EVEN_EN Position */ +#define CMSDK_UART_LCR_EVEN_EN_Msk (0x01ul << CMSDK_UART_LCR_EVEN_EN_Pos) /*!< CMSDK_UART LCR: EVEN_EN Mask */ + +#define CMSDK_UART_LCR_PARITY_EN_Pos 3 /*!< CMSDK_UART LCR: PARITY_EN Position */ +#define CMSDK_UART_LCR_PARITY_EN_Msk (0x01ul << CMSDK_UART_LCR_PARITY_EN_Pos) /*!< CMSDK_UART LCR: PARITY_EN Mask */ + +#define CMSDK_UART_LCR_STOP_LEN_Pos 2 /*!< CMSDK_UART LCR: STOP_LEN Position */ +#define CMSDK_UART_LCR_STOP_LEN_Msk (0x01ul << CMSDK_UART_LCR_STOP_LEN_Pos) /*!< CMSDK_UART LCR: STOP_LEN Mask */ + +#define CMSDK_UART_LCR_WORD_LEN_Pos 0 /*!< CMSDK_UART LCR: WORD_LEN Position */ +#define CMSDK_UART_LCR_WORD_LEN_Msk (0x03ul << CMSDK_UART_LCR_WORD_LEN_Pos) /*!< CMSDK_UART LCR: WORD_LEN Mask */ + +#define CMSDK_UART_LSR_RX_ERR_STS_Pos 7 /*!< CMSDK_UART LSR: RX_ERR_STS Position */ +#define CMSDK_UART_LSR_RX_ERR_STS_Msk (0x01ul << CMSDK_UART_LSR_RX_ERR_STS_Pos) /*!< CMSDK_UART LSR: RX_ERR_STS Mask */ + +#define CMSDK_UART_LSR_TX_EMPTY_Pos 6 /*!< CMSDK_UART LSR: TRANSMITTER_EMPTY Position */ +#define CMSDK_UART_LSR_TX_EMPTY_Msk (0x01ul << CMSDK_UART_LSR_TX_EMPTY_Pos) /*!< CMSDK_UART LSR: TRANSMITTER_EMPTY Mask */ + +#define CMSDK_UART_LSR_THR_EMPTY_Pos 5 /*!< CMSDK_UART LSR: THR_EMPTY Position */ +#define CMSDK_UART_LSR_THR_EMPTY_Msk (0x01ul << CMSDK_UART_LSR_THR_EMPTY_Pos) /*!< CMSDK_UART LSR: THR_EMPTY Mask */ + +#define CMSDK_UART_LSR_BREAK_ERR_STS_Pos 4 /*!< CMSDK_UART LSR: BREAK_ERR_STS Position */ +#define CMSDK_UART_LSR_BREAK_ERR_STS_Msk (0x01ul << CMSDK_UART_LSR_BREAK_ERR_STS_Pos) /*!< CMSDK_UART LSR: BREAK_ERR_STS Mask */ + +#define CMSDK_UART_LSR_FRAME_ERR_STS_Pos 3 /*!< CMSDK_UART LSR: FRAME_ERR_STS Position */ +#define CMSDK_UART_LSR_FRAME_ERR_STS_Msk (0x01ul << CMSDK_UART_LSR_FRAME_ERR_STS_Pos) /*!< CMSDK_UART LSR: FRAME_ERR_STS Mask */ + +#define CMSDK_UART_LSR_PARITY_ERR_STS_Pos 2 /*!< CMSDK_UART LSR: PARITY_ERR_STS Position */ +#define CMSDK_UART_LSR_PARITY_ERR_STS_Msk (0x01ul << CMSDK_UART_LSR_PARITY_ERR_STS_Pos) /*!< CMSDK_UART LSR: PARITY_ERR_STS Mask */ + +#define CMSDK_UART_LSR_OVRRUN_ERR_STS_Pos 1 /*!< CMSDK_UART LSR: OVRRUN_ERR_STS Position */ +#define CMSDK_UART_LSR_OVRRUN_ERR_STS_Msk (0x01ul << CMSDK_UART_LSR_OVRRUN_ERR_STS_Pos) /*!< CMSDK_UART LSR: OVRRUN_ERR_STS Mask */ + +#define CMSDK_UART_MCR_RTS_TRI_MODE_Pos 6 /*!< CMSDK_UART MCR: RTS_TRI_MODE Position */ +#define CMSDK_UART_MCR_RTS_TRI_MODE_Msk (0x01ul << CMSDK_UART_MCR_RTS_TRI_MODE_Pos) /*!< CMSDK_UART MCR: RTS_TRI_MODE Mask */ + +#define CMSDK_UART_MCR_AUTOFLOW_EN_Pos 5 /*!< CMSDK_UART MCR: AUTOFLOW_EN Position */ +#define CMSDK_UART_MCR_AUTOFLOW_EN_Msk (0x01ul << CMSDK_UART_MCR_AUTOFLOW_EN_Pos) /*!< CMSDK_UART MCR: AUTOFLOW_EN Mask */ + +#define CMSDK_UART_MCR_LOOPBACK_EN_Pos 4 /*!< CMSDK_UART MCR: LOOPBACK_EN Position */ +#define CMSDK_UART_MCR_LOOPBACK_EN_Msk (0x01ul << CMSDK_UART_MCR_LOOPBACK_EN_Pos) /*!< CMSDK_UART MCR: LOOPBACK_EN Mask */ + +#define CMSDK_UART_MCR_AUX2_Pos 3 /*!< CMSDK_UART MCR: AUX2 Position */ +#define CMSDK_UART_MCR_AUX2_Msk (0x01ul << CMSDK_UART_MCR_AUX2_Pos) /*!< CMSDK_UART MCR: AUX2 Mask */ + +#define CMSDK_UART_MCR_AUX1_Pos 2 /*!< CMSDK_UART MCR: AUX1 Position */ +#define CMSDK_UART_MCR_AUX1_Msk (0x01ul << CMSDK_UART_MCR_AUX1_Pos) /*!< CMSDK_UART MCR: AUX1 Mask */ + +#define CMSDK_UART_MCR_RTS_CTRL_Pos 1 /*!< CMSDK_UART MCR: RTS_CTRL Position */ +#define CMSDK_UART_MCR_RTS_CTRL_Msk (0x01ul << CMSDK_UART_MCR_RTS_CTRL_Pos) /*!< CMSDK_UART MCR: RTS_CTRL Mask */ + +#define CMSDK_UART_MCR_DTR_CTRL_Pos 0 /*!< CMSDK_UART MCR: DTR_CTRL Position */ +#define CMSDK_UART_MCR_DTR_CTRL_Msk (0x01ul << CMSDK_UART_MCR_DTR_CTRL_Pos) /*!< CMSDK_UART MCR: DTR_CTRL Mask */ + +#define CMSDK_UART_PMU_TXRST_Pos 1 /*!< CMSDK_UART PMU: TXRST Position */ +#define CMSDK_UART_PMU_TXRST_Msk (0x01ul << CMSDK_UART_PMU_TXRST_Pos) /*!< CMSDK_UART PMU: TXRST Mask */ + +#define CMSDK_UART_PMU_RXRST_Pos 0 /*!< CMSDK_UART PMU: RXRST Position */ +#define CMSDK_UART_PMU_RXRST_Msk (0x01ul << CMSDK_UART_PMU_RXRST_Pos) /*!< CMSDK_UART PMU: RXRST Mask */ + +#define CMSDK_UART_MDR_DEB_EN_Pos 1 /*!< CMSDK_UART MDR: DEB_EN Position */ +#define CMSDK_UART_MDR_DEB_EN_Msk (0x01ul << CMSDK_UART_MDR_DEB_EN_Pos) /*!< CMSDK_UART MDR: DEB_EN Mask */ + +#define CMSDK_UART_MDR_OSM_SEL_Pos 0 /*!< CMSDK_UART MDR: OSM_SEL Position */ +#define CMSDK_UART_MDR_OSM_SEL_Msk (0x01ul << CMSDK_UART_MDR_OSM_SEL_Pos) /*!< CMSDK_UART MDR: OSM_SEL Mask */ +/*@}*/ /* end of group CMSDK_UART */ + + +/*-------------------- Serial Peripheral Interface (SPI) -------------------*/ + +/** @addtogroup CMSDK_SPI SPI + @{ +*/ +typedef struct +{ + union { + __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/) */ + __O uint32_t THR; /*!< Offset: 0x000 Transmitter Holding Register ( /W) */ + }; + __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x008 Interrupt Status Register (R/) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x008 Interrupt Clear Register ( /W) */ + }; + __IO uint32_t CTRL1; /*!< Offset: 0x00C Control_1 Register (R/W) */ + __IO uint32_t CTRL2; /*!< Offset: 0x010 Control_2 Register (R/W) */ + __IO uint32_t FCR; /*!< Offset: 0x014 FIFO Control Register (R/W) */ + __I uint32_t FSR; /*!< Offset: 0x018 FIFO Status Register (R/) */ + __I uint32_t DBG; /*!< Offset: 0x01C Debug Signal Register (R/) */ + +} CMSDK_SPI_TypeDef; + + +/* CMSDK_SPI Register Definitions */ +#define CMSDK_SPI_UNDERRUN_INT_EN_Pos 4 /*!< CMSDK_SPI IER: UNDERRUN_INT_EN Position */ +#define CMSDK_SPI_UNDERRUN_INT_EN_Msk (0x01ul << CMSDK_SPI_UNDERRUN_INT_EN_Pos) /*!< CMSDK_SPI IER: UNDERRUN_INT_EN Mask */ + +#define CMSDK_SPI_UNDERRUN_INT_STS_Pos 4 /*!< CMSDK_SPI ISR: UNDERRUN_INT_STS Position */ +#define CMSDK_SPI_UNDERRUN_INT_STS_Msk (0x01ul << CMSDK_SPI_UNDERRUN_INT_STS_Pos) /*!< CMSDK_SPI ISR: UNDERRUN_INT_STS Mask */ + +#define CMSDK_SPI_OVERRUN_INT_EN_Pos 3 /*!< CMSDK_SPI IER: OVERRUN_INT_EN Position */ +#define CMSDK_SPI_OVERRUN_INT_EN_Msk (0x01ul << CMSDK_SPI_OVERRUN_INT_EN_Pos) /*!< CMSDK_SPI IER: OVERRUN_INT_EN Mask */ + +#define CMSDK_SPI_OVERRUN_INT_STS_Pos 3 /*!< CMSDK_SPI ISR: OVERRUN_INT_STS Position */ +#define CMSDK_SPI_OVERRUN_INT_STS_Msk (0x01ul << CMSDK_SPI_OVERRUN_INT_STS_Pos) /*!< CMSDK_SPI ISR: OVERRUN_INT_STS Mask */ + +#define CMSDK_SPI_CMPL_INT_EN_Pos 2 /*!< CMSDK_SPI IER: CMPL_INT_EN Position */ +#define CMSDK_SPI_CMPL_INT_EN_Msk (0x01ul << CMSDK_SPI_CMPL_INT_EN_Pos) /*!< CMSDK_SPI IER: CMPL_INT_EN Mask */ + +#define CMSDK_SPI_CMPL_INT_STS_Pos 2 /*!< CMSDK_SPI ISR: CMPL_INT_STS Position */ +#define CMSDK_SPI_CMPL_INT_STS_Msk (0x01ul << CMSDK_SPI_CMPL_INT_STS_Pos) /*!< CMSDK_SPI ISR: CMPL_INT_STS Mask */ + +#define CMSDK_SPI_TXE_INT_EN_Pos 1 /*!< CMSDK_SPI IER: TXE_INT_EN Position */ +#define CMSDK_SPI_TXE_INT_EN_Msk (0x01ul << CMSDK_SPI_TXE_INT_EN_Pos) /*!< CMSDK_SPI IER: TXE_INT_EN Mask */ + +#define CMSDK_SPI_TXE_INT_STS_Pos 1 /*!< CMSDK_SPI ISR: TXE_INT_STS Position */ +#define CMSDK_SPI_TXE_INT_STS_Msk (0x01ul << CMSDK_SPI_TXE_INT_STS_Pos) /*!< CMSDK_SPI ISR: TXE_INT_STS Mask */ + +#define CMSDK_SPI_RXNE_INT_EN_Pos 0 /*!< CMSDK_SPI IER: RXNE_INT_EN Position */ +#define CMSDK_SPI_RXNE_INT_EN_Msk (0x01ul << CMSDK_SPI_RXNE_INT_EN_Pos) /*!< CMSDK_SPI IER: RXNE_INT_EN Mask */ + +#define CMSDK_SPI_RXNE_INT_STS_Pos 0 /*!< CMSDK_SPI ISR: RXNE_INT_STS Position */ +#define CMSDK_SPI_RXNE_INT_STS_Msk (0x01ul << CMSDK_SPI_RXNE_INT_STS_Pos) /*!< CMSDK_SPI ISR: RXNE_INT_STS Mask */ + +#define CMSDK_SPI_BIDI_EN_Pos 15 /*!< CMSDK_SPI CTRL1: BIDI_EN Position */ +#define CMSDK_SPI_BIDI_EN_Msk (0x01ul << CMSDK_SPI_BIDI_EN_Pos) /*!< CMSDK_SPI CTRL1: BIDI_EN Mask */ + +#define CMSDK_SPI_BIDI_MODE_Pos 14 /*!< CMSDK_SPI CTRL1: BIDI_MODE Position */ +#define CMSDK_SPI_BIDI_MODE_Msk (0x01ul << CMSDK_SPI_BIDI_MODE_Pos) /*!< CMSDK_SPI CTRL1: BIDI_MODE Mask */ + +#define CMSDK_SPI_UNIDI_MODE_Pos 12 /*!< CMSDK_SPI CTRL1: UNIDI_MODE Position */ +#define CMSDK_SPI_UNIDI_MODE_Msk (0x03ul << CMSDK_SPI_UNIDI_MODE_Pos) /*!< CMSDK_SPI CTRL1: UNIDI_MODE Mask */ + +#define CMSDK_SPI_NSS_TOGGLE_Pos 11 /*!< CMSDK_SPI CTRL1: NSS_TOGGLE Position */ +#define CMSDK_SPI_NSS_TOGGLE_Msk (0x01ul << CMSDK_SPI_NSS_TOGGLE_Pos) /*!< CMSDK_SPI CTRL1: NSS_TOGGLE Mask */ + +#define CMSDK_SPI_LOOP_BACK_EN_Pos 10 /*!< CMSDK_SPI CTRL1: LOOP_BACK_EN Position */ +#define CMSDK_SPI_LOOP_BACK_EN_Msk (0x01ul << CMSDK_SPI_LOOP_BACK_EN_Pos) /*!< CMSDK_SPI CTRL1: LOOP_BACK_EN Mask */ + +#define CMSDK_SPI_NSS_MST_SW_Pos 9 /*!< CMSDK_SPI CTRL1: NSS_MST_SW Position */ +#define CMSDK_SPI_NSS_MST_SW_Msk (0x01ul << CMSDK_SPI_NSS_MST_SW_Pos) /*!< CMSDK_SPI CTRL1: NSS_MST_SW Mask */ + +#define CMSDK_SPI_NSS_MST_CTRL_Pos 8 /*!< CMSDK_SPI CTRL1: NSS_MST_CTRL Position */ +#define CMSDK_SPI_NSS_MST_CTRL_Msk (0x01ul << CMSDK_SPI_NSS_MST_CTRL_Pos) /*!< CMSDK_SPI CTRL1: NSS_MST_CTRL Mask */ + +#define CMSDK_SPI_LSB_SEL_Pos 7 /*!< CMSDK_SPI CTRL1: LSB_SEL Position */ +#define CMSDK_SPI_LSB_SEL_Msk (0x01ul << CMSDK_SPI_LSB_SEL_Pos) /*!< CMSDK_SPI CTRL1: LSB_SEL Mask */ + +#define CMSDK_SPI_BAUD_RATE_Pos 4 /*!< CMSDK_SPI CTRL1: BAUD_RATE Position */ +#define CMSDK_SPI_BAUD_RATE_Msk (0x07ul << CMSDK_SPI_BAUD_RATE_Pos) /*!< CMSDK_SPI CTRL1: BAUD_RATE Mask */ + +#define CMSDK_SPI_CPOL_Pos 3 /*!< CMSDK_SPI CTRL1: CPOL Position */ +#define CMSDK_SPI_CPOL_Msk (0x01ul << CMSDK_SPI_CPOL_Pos) /*!< CMSDK_SPI CTRL1: CPOL Mask */ + +#define CMSDK_SPI_CPHA_Pos 2 /*!< CMSDK_SPI CTRL1: CPHA Position */ +#define CMSDK_SPI_CPHA_Msk (0x01ul << CMSDK_SPI_CPHA_Pos) /*!< CMSDK_SPI CTRL1: CPHA Mask */ + +#define CMSDK_SPI_MST_SLV_SEL_Pos 1 /*!< CMSDK_SPI CTRL1: MST_SLV_SEL Position */ +#define CMSDK_SPI_MST_SLV_SEL_Msk (0x01ul << CMSDK_SPI_MST_SLV_SEL_Pos) /*!< CMSDK_SPI CTRL1: MST_SLV_SEL Mask */ + +#define CMSDK_SPI_EN_Pos 0 /*!< CMSDK_SPI CTRL1: SPI_EN Position */ +#define CMSDK_SPI_EN_Msk (0x01ul << CMSDK_SPI_EN_Pos) /*!< CMSDK_SPI CTRL1: SPI_EN Mask */ + +#define CMSDK_SPI_T2C_DELAY_Pos 14 /*!< CMSDK_SPI CTRL2: T2C_DELAY Position */ +#define CMSDK_SPI_T2C_DELAY_Msk (0x0003ul << CMSDK_SPI_T2C_DELAY_Pos) /*!< CMSDK_SPI CTRL2: T2C_DELAY Mask */ + +#define CMSDK_SPI_C2T_DELAY_Pos 12 /*!< CMSDK_SPI CTRL2: C2T_DELAY Position */ +#define CMSDK_SPI_C2T_DELAY_Msk (0x0003ul << CMSDK_SPI_C2T_DELAY_Pos) /*!< CMSDK_SPI CTRL2: C2T_DELAY Mask */ + +#define CMSDK_SPI_NSS3_EN_Pos 11 /*!< CMSDK_SPI CTRL2: NSS3_EN Position */ +#define CMSDK_SPI_NSS3_EN_Msk (0x01ul << CMSDK_SPI_NSS3_EN_Pos) /*!< CMSDK_SPI CTRL2: NSS3_EN Mask */ + +#define CMSDK_SPI_NSS2_EN_Pos 10 /*!< CMSDK_SPI CTRL2: NSS2_EN Position */ +#define CMSDK_SPI_NSS2_EN_Msk (0x01ul << CMSDK_SPI_NSS2_EN_Pos) /*!< CMSDK_SPI CTRL2: NSS2_EN Mask */ + +#define CMSDK_SPI_NSS1_EN_Pos 9 /*!< CMSDK_SPI CTRL2: NSS1_EN Position */ +#define CMSDK_SPI_NSS1_EN_Msk (0x01ul << CMSDK_SPI_NSS1_EN_Pos) /*!< CMSDK_SPI CTRL2: NSS1_EN Mask */ + +#define CMSDK_SPI_NSS0_EN_Pos 8 /*!< CMSDK_SPI CTRL2: NSS0_EN Position */ +#define CMSDK_SPI_NSS0_EN_Msk (0x01ul << CMSDK_SPI_NSS0_EN_Pos) /*!< CMSDK_SPI CTRL2: NSS0_EN Mask */ + +#define CMSDK_SPI_SAMP_PHASE_Pos 6 /*!< CMSDK_SPI CTRL2: SAMP_PHASE Position */ +#define CMSDK_SPI_SAMP_PHASE_Msk (0x0003ul << CMSDK_SPI_SAMP_PHASE_Pos) /*!< CMSDK_SPI CTRL2: SAMP_PHASE Mask */ + +#define CMSDK_SPI_TX_DMA_EN_Pos 5 /*!< CMSDK_SPI CTRL2: TX_DMA_EN Position */ +#define CMSDK_SPI_TX_DMA_EN_Msk (0x01ul << CMSDK_SPI_TX_DMA_EN_Pos) /*!< CMSDK_SPI CTRL2: TX_DMA_EN Mask */ + +#define CMSDK_SPI_RX_DMA_EN_Pos 4 /*!< CMSDK_SPI CTRL2: RX_DMA_EN Position */ +#define CMSDK_SPI_RX_DMA_EN_Msk (0x01ul << CMSDK_SPI_RX_DMA_EN_Pos) /*!< CMSDK_SPI CTRL2: RX_DMA_EN Mask */ + +#define CMSDK_SPI_CHAR_LEN_Pos 0 /*!< CMSDK_SPI CTRL2: CHAR_LEN Position */ +#define CMSDK_SPI_CHAR_LEN_Msk (0x000Ful << CMSDK_SPI_CHAR_LEN_Pos) /*!< CMSDK_SPI CTRL2: CHAR_LEN Mask */ + +#define CMSDK_SPI_RX_FIFO_LEN_Pos 16 /*!< CMSDK_SPI FSR: RX_FIFO_LEN Position */ +#define CMSDK_SPI_RX_FIFO_LEN_Msk (0x001Ful << CMSDK_SPI_RX_FIFO_LEN_Pos) /*!< CMSDK_SPI FSR: RX_FIFO_LEN Mask */ + +#define CMSDK_SPI_TX_FIFO_LEN_Pos 8 /*!< CMSDK_SPI FSR: TX_FIFO_LEN Position */ +#define CMSDK_SPI_TX_FIFO_LEN_Msk (0x001Ful << CMSDK_SPI_TX_FIFO_LEN_Pos) /*!< CMSDK_SPI FSR: TX_FIFO_LEN Mask */ + +#define CMSDK_SPI_BUSY_Pos 4 /*!< CMSDK_SPI FSR: SPI_BUSY Position */ +#define CMSDK_SPI_BUSY_Msk (0x01ul << CMSDK_SPI_BUSY_Pos) /*!< CMSDK_SPI FSR: SPI_BUSY Mask */ + +#define CMSDK_SPI_RX_FIFO_FULL_Pos 3 /*!< CMSDK_SPI FSR: RX_FIFO_FULL Position */ +#define CMSDK_SPI_RX_FIFO_FULL_Msk (0x01ul << CMSDK_SPI_RX_FIFO_FULL_Pos) /*!< CMSDK_SPI FSR: RX_FIFO_FULL Mask */ + +#define CMSDK_SPI_TX_FIFO_EMPTY_Pos 0 /*!< CMSDK_SPI FSR: TX_FIFO_EMPTY Position */ +#define CMSDK_SPI_TX_FIFO_EMPTY_Msk (0x01ul << CMSDK_SPI_TX_FIFO_EMPTY_Pos) /*!< CMSDK_SPI FSR: TX_FIFO_EMPTY Mask */ + +#define CMSDK_SPI_TX_FIFO_TH_Pos 9 /*!< CMSDK_SPI FCR: TX_FIFO_TH Position */ +#define CMSDK_SPI_TX_FIFO_TH_Msk (0x001Ful << CMSDK_SPI_TX_FIFO_TH_Pos) /*!< CMSDK_SPI FCR: TX_FIFO_TH Mask */ + +#define CMSDK_SPI_TX_FIFO_CLR_Pos 8 /*!< CMSDK_SPI FCR: TX_FIFO_CLR Position */ +#define CMSDK_SPI_TX_FIFO_CLR_Msk (0x01ul << CMSDK_SPI_TX_FIFO_CLR_Pos) /*!< CMSDK_SPI FCR: TX_FIFO_CLR Mask */ + +#define CMSDK_SPI_RX_FIFO_TH_Pos 2 /*!< CMSDK_SPI FCR: RX_FIFO_TH Position */ +#define CMSDK_SPI_RX_FIFO_TH_Msk (0x001Ful << CMSDK_SPI_RX_FIFO_TH_Pos) /*!< CMSDK_SPI FCR: RX_FIFO_TH Mask */ + +#define CMSDK_SPI_RX_FIFO_CLR_Pos 1 /*!< CMSDK_SPI FCR: RX_FIFO_CLR Position */ +#define CMSDK_SPI_RX_FIFO_CLR_Msk (0x01ul << CMSDK_SPI_RX_FIFO_CLR_Pos) /*!< CMSDK_SPI FCR: RX_FIFO_CLR Mask */ + +#define CMSDK_SPI_FIFO_EN_Pos 0 /*!< CMSDK_SPI FCR: FIFO_EN Position */ +#define CMSDK_SPI_FIFO_EN_Msk (0x01ul << CMSDK_SPI_FIFO_EN_Pos) /*!< CMSDK_SPI FCR: FIFO_EN Mask */ +/*@}*/ /* end of group CMSDK_SPI */ + + +/*-------------------- Inter Integrated Circuit Bus(I2C) -------------------*/ + +/** @addtogroup CMSDK_I2C I2C + @{ +*/ +typedef struct +{ + __IO uint32_t I2C_DR; /*!< Offset: 0x000 I2C Data Register (R/W) */ + __IO uint32_t I2C_OAR; /*!< Offset: 0x004 I2C Own Address Register (R/W) */ + __IO uint32_t I2C_CR1; /*!< Offset: 0x008 I2C Control Register 1 (R/W) */ + __IO uint32_t I2C_CR2; /*!< Offset: 0x00C I2C Control Register 2 (R/W) */ + union { + __I uint32_t I2C_STS; /*!< Offset: 0x010 I2C Status Register SR (R/) */ + __O uint32_t I2C_STS_CLR; /*!< Offset: 0x010 I2C Status Clear Register ( /W) */ + }; + __I uint32_t I2C_DBG; /*!< Offset: 0x014 I2C Debug data Register (R/) */ + +} CMSDK_I2C_TypeDef; + + +/* CMSDK_I2C Register Definitions */ +#define CMSDK_I2C_CR1_SWRST_Pos 15 /*!< CMSDK_I2C CR1: SWRST Position */ +#define CMSDK_I2C_CR1_SWRST_Msk (0x01ul << CMSDK_I2C_CR1_SWRST_Pos) /*!< CMSDK_I2C CR1: SWRST Mask */ + +#define CMSDK_I2C_CR1_DBYPASS_Pos 7 /*!< CMSDK_I2C CR1: DBYPASS Position */ +#define CMSDK_I2C_CR1_DBYPASS_Msk (0x01ul << CMSDK_I2C_CR1_DBYPASS_Pos) /*!< CMSDK_I2C CR1: DBYPASS Mask */ + +#define CMSDK_I2C_CR1_MULTIMASTER_Pos 6 /*!< CMSDK_I2C CR1: MULTIMASTER Position */ +#define CMSDK_I2C_CR1_MULTIMASTER_Msk (0x01ul << CMSDK_I2C_CR1_MULTIMASTER_Pos) /*!< CMSDK_I2C CR1: MULTIMASTER Mask */ + +#define CMSDK_I2C_CR1_ACK_Pos 5 /*!< CMSDK_I2C CR1: ACK Position */ +#define CMSDK_I2C_CR1_ACK_Msk (0x01ul << CMSDK_I2C_CR1_ACK_Pos) /*!< CMSDK_I2C CR1: ACK Mask */ + +#define CMSDK_I2C_CR1_STOP_Pos 4 /*!< CMSDK_I2C CR1: STOP Position */ +#define CMSDK_I2C_CR1_STOP_Msk (0x01ul << CMSDK_I2C_CR1_STOP_Pos) /*!< CMSDK_I2C CR1: STOP Mask */ + +#define CMSDK_I2C_CR1_START_Pos 3 /*!< CMSDK_I2C CR1: START Position */ +#define CMSDK_I2C_CR1_START_Msk (0x01ul << CMSDK_I2C_CR1_START_Pos) /*!< CMSDK_I2C CR1: START Mask */ + +#define CMSDK_I2C_CR1_NOSTRETCH_Pos 2 /*!< CMSDK_I2C CR1: NOSTRETCH Position */ +#define CMSDK_I2C_CR1_NOSTRETCH_Msk (0x01ul << CMSDK_I2C_CR1_NOSTRETCH_Pos) /*!< CMSDK_I2C CR1: NOSTRETCH Mask */ + +#define CMSDK_I2C_CR1_ENGC_Pos 1 /*!< CMSDK_I2C CR1: ENGC Position */ +#define CMSDK_I2C_CR1_ENGC_Msk (0x01ul << CMSDK_I2C_CR1_ENGC_Pos) /*!< CMSDK_I2C CR1: ENGC Mask */ + +#define CMSDK_I2C_CR1_PE_Pos 0 /*!< CMSDK_I2C CR1: PE Position */ +#define CMSDK_I2C_CR1_PE_Msk (0x01ul << CMSDK_I2C_CR1_PE_Pos) /*!< CMSDK_I2C CR1: PE Mask */ + +#define CMSDK_I2C_CR2_DMALAST_Pos 10 /*!< CMSDK_I2C CR2: DMALAST Position */ +#define CMSDK_I2C_CR2_DMALAST_Msk (0x01ul << CMSDK_I2C_CR2_DMALAST_Pos) /*!< CMSDK_I2C CR2: DMALAST Mask */ + +#define CMSDK_I2C_CR2_DMAEN_Pos 9 /*!< CMSDK_I2C CR2: DMAEN Position */ +#define CMSDK_I2C_CR2_DMAEN_Msk (0x01ul << CMSDK_I2C_CR2_DMAEN_Pos) /*!< CMSDK_I2C CR2: DMAEN Mask */ + +#define CMSDK_I2C_CR2_BUF_INTEN_Pos 8 /*!< CMSDK_I2C CR2: BUF_INTEN Position */ +#define CMSDK_I2C_CR2_BUF_INTEN_Msk (0x01ul << CMSDK_I2C_CR2_BUF_INTEN_Pos) /*!< CMSDK_I2C CR2: BUF_INTEN Mask */ + +#define CMSDK_I2C_CR2_EVT_INTEN_Pos 7 /*!< CMSDK_I2C CR2: EVT_INTEN Position */ +#define CMSDK_I2C_CR2_EVT_INTEN_Msk (0x01ul << CMSDK_I2C_CR2_EVT_INTEN_Pos) /*!< CMSDK_I2C CR2: EVT_INTEN Mask */ + +#define CMSDK_I2C_CR2_ERR_INTEN_Pos 6 /*!< CMSDK_I2C CR2: ERR_INTEN Position */ +#define CMSDK_I2C_CR2_ERR_INTEN_Msk (0x01ul << CMSDK_I2C_CR2_ERR_INTEN_Pos) /*!< CMSDK_I2C CR2: ERR_INTEN Mask */ + +#define CMSDK_I2C_CR2_FREQDIV_Pos 0 /*!< CMSDK_I2C CR2: FREQDIV Position */ +#define CMSDK_I2C_CR2_FREQDIV_Msk (0x003Ful << CMSDK_I2C_CR2_FREQDIV_Pos) /*!< CMSDK_I2C CR2: FREQDIV Mask */ + +#define CMSDK_I2C_SR_GENCALL_Pos 15 /*!< CMSDK_I2C SR: GENCALL Position */ +#define CMSDK_I2C_SR_GENCALL_Msk (0x01ul << CMSDK_I2C_SR_GENCALL_Pos) /*!< CMSDK_I2C SR: GENCALL Mask */ + +#define CMSDK_I2C_SR_TX_RX_Pos 14 /*!< CMSDK_I2C SR: TX_RX Position */ +#define CMSDK_I2C_SR_TX_RX_Msk (0x01ul << CMSDK_I2C_SR_TX_RX_Pos) /*!< CMSDK_I2C SR: TX_RX Mask */ + +#define CMSDK_I2C_SR_BUSY_Pos 13 /*!< CMSDK_I2C SR: BUSY Position */ +#define CMSDK_I2C_SR_BUSY_Msk (0x01ul << CMSDK_I2C_SR_BUSY_Pos) /*!< CMSDK_I2C SR: BUSY Mask */ + +#define CMSDK_I2C_SR_MSL_Pos 12 /*!< CMSDK_I2C SR: MSL Position */ +#define CMSDK_I2C_SR_MSL_Msk (0x01ul << CMSDK_I2C_SR_MSL_Pos) /*!< CMSDK_I2C SR: MSL Mask */ + +#define CMSDK_I2C_SR_OVR_Pos 11 /*!< CMSDK_I2C SR: OVR Position */ +#define CMSDK_I2C_SR_OVR_Msk (0x01ul << CMSDK_I2C_SR_OVR_Pos) /*!< CMSDK_I2C SR: OVR Mask */ + +#define CMSDK_I2C_SR_ACK_FAIL_Pos 10 /*!< CMSDK_I2C SR: ACK_FAIL Position */ +#define CMSDK_I2C_SR_ACK_FAIL_Msk (0x01ul << CMSDK_I2C_SR_ACK_FAIL_Pos) /*!< CMSDK_I2C SR: ACK_FAIL Mask */ + +#define CMSDK_I2C_SR_ARB_LOST_Pos 9 /*!< CMSDK_I2C SR: ARB_LOST Position */ +#define CMSDK_I2C_SR_ARB_LOST_Msk (0x01ul << CMSDK_I2C_SR_ARB_LOST_Pos) /*!< CMSDK_I2C SR: ARB_LOST Mask */ + +#define CMSDK_I2C_SR_BUS_ERR_Pos 8 /*!< CMSDK_I2C SR: BUS_ERR Position */ +#define CMSDK_I2C_SR_BUS_ERR_Msk (0x01ul << CMSDK_I2C_SR_BUS_ERR_Pos) /*!< CMSDK_I2C SR: BUS_ERR Mask */ + +#define CMSDK_I2C_SR_TXE_Pos 6 /*!< CMSDK_I2C SR: TXE Position */ +#define CMSDK_I2C_SR_TXE_Msk (0x01ul << CMSDK_I2C_SR_TXE_Pos) /*!< CMSDK_I2C SR: TXE Mask */ + +#define CMSDK_I2C_SR_RXNE_Pos 5 /*!< CMSDK_I2C SR: RXNE Position */ +#define CMSDK_I2C_SR_RXNE_Msk (0x01ul << CMSDK_I2C_SR_RXNE_Pos) /*!< CMSDK_I2C SR: RXNE Mask */ + +#define CMSDK_I2C_SR_STOPF_Pos 4 /*!< CMSDK_I2C SR: STOPF Position */ +#define CMSDK_I2C_SR_STOPF_Msk (0x01ul << CMSDK_I2C_SR_STOPF_Pos) /*!< CMSDK_I2C SR: STOPF Mask */ + +#define CMSDK_I2C_SR_ADD10_Pos 3 /*!< CMSDK_I2C SR: ADD10 Position */ +#define CMSDK_I2C_SR_ADD10_Msk (0x01ul << CMSDK_I2C_SR_ADD10_Pos) /*!< CMSDK_I2C SR: ADD10 Mask */ + +#define CMSDK_I2C_SR_BTF_Pos 2 /*!< CMSDK_I2C SR: BTF Position */ +#define CMSDK_I2C_SR_BTF_Msk (0x01ul << CMSDK_I2C_SR_BTF_Pos) /*!< CMSDK_I2C SR: BTF Mask */ + +#define CMSDK_I2C_SR_ADDR_Pos 1 /*!< CMSDK_I2C SR: ADDR Position */ +#define CMSDK_I2C_SR_ADDR_Msk (0x01ul << CMSDK_I2C_SR_ADDR_Pos) /*!< CMSDK_I2C SR: ADDR Mask */ + +#define CMSDK_I2C_SR_STARTBIT_Pos 0 /*!< CMSDK_I2C SR: STARTBIT Position */ +#define CMSDK_I2C_SR_STARTBIT_Msk (0x01ul << CMSDK_I2C_SR_STARTBIT_Pos) /*!< CMSDK_I2C SR: STARTBIT Mask */ +/*@}*/ /* end of group CMSDK_I2C */ + + +/*------------------- Watchdog ----------------------------------------------*/ +/** @addtogroup CMSDK_WATCHDOG Watchdog + @{ +*/ +typedef struct +{ + + __IO uint32_t LOAD; // Watchdog Load Register + __I uint32_t VALUE; // Watchdog Value Register + __IO uint32_t CTRL; // Watchdog Control Register + // RESEN: Reset enable + // INTEN: Interrupt enable + // + __O uint32_t INTCLR; // Watchdog Clear Interrupt Register + __I uint32_t RAWINTSTAT; // Watchdog Raw Interrupt Status Register + __I uint32_t MASKINTSTAT; // Watchdog Interrupt Status Register + uint32_t RESERVED0[762]; + __IO uint32_t LOCK; // Watchdog Lock Register + uint32_t RESERVED1[191]; + __IO uint32_t ITCR; // Watchdog Integration Test Control Register + __O uint32_t ITOP; // Watchdog Integration Test Output Set Register + +}CMSDK_WDT_TypeDef; + +/* CMSDK_WATCHDOG Register Definitions */ +#define CMSDK_Watchdog_LOAD_Pos 0 /*!< CMSDK_Watchdog LOAD: LOAD Position */ +#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /*!< CMSDK_Watchdog LOAD: LOAD Mask */ + +#define CMSDK_Watchdog_VALUE_Pos 0 /*!< CMSDK_Watchdog VALUE: VALUE Position */ +#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /*!< CMSDK_Watchdog VALUE: VALUE Mask */ + +#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */ +#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /*!< CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */ + +#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Position */ +#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /*!< CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */ + +#define CMSDK_Watchdog_INTCLR_Pos 0 /*!< CMSDK_Watchdog INTCLR: Int Clear Position */ +#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /*!< CMSDK_Watchdog INTCLR: Int Clear Mask */ + +#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /*!< CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /*!< CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_Watchdog_LOCK_Pos 0 /*!< CMSDK_Watchdog LOCK: LOCK Position */ +#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /*!< CMSDK_Watchdog LOCK: LOCK Mask */ + +#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */ +#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /*!< CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */ + +#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */ +#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /*!< CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */ +/*@}*/ /* end of group CMSDK_WATCHDOG */ + + +/*------------------- Pulse Width Modulator (PWM) -------------------*/ + +/** @addtogroup CMSDK_PWM PWM + @{ +*/ +typedef struct +{ + __IO uint32_t TC; /*!< Offset: 0x000 PWM Timer Counter Register (R/W) */ + __IO uint32_t TCR; /*!< Offset: 0x004 PWM Timer Control Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x008 Interrupt Status Register (R/) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x008 Interrupt Clear Register ( /W) */ + }; + __IO uint32_t PR; /*!< Offset: 0x00C PWM Prescale Register (R/W) */ + __IO uint32_t PC; /*!< Offset: 0x010 PWM Prescale Counter Register (R/W) */ + __IO uint32_t MCR; /*!< Offset: 0x014 PWM Match Control Register (R/W) */ + __IO uint32_t MR0; /*!< Offset: 0x018 PWM Match Register 0 (R/W) */ + __IO uint32_t MR1; /*!< Offset: 0x01C PWM Match Register 1 (R/W) */ + __IO uint32_t MR2; /*!< Offset: 0x020 PWM Match Register 2 (R/W) */ + __IO uint32_t MR3; /*!< Offset: 0x024 PWM Match Register 3 (R/W) */ + __IO uint32_t MR4; /*!< Offset: 0x028 PWM Match Register 4 (R/W) */ + __IO uint32_t MR5; /*!< Offset: 0x02C PWM Match Register 5 (R/W) */ + __IO uint32_t MR6; /*!< Offset: 0x030 PWM Match Register 6 (R/W) */ + __IO uint32_t PCR; /*!< Offset: 0x034 PWM Control Register (R/W) */ + __IO uint32_t LER; /*!< Offset: 0x038 PWM Load Enable Register (R/W) */ + __I uint32_t DBG; /*!< Offset: 0x03C PWM Debug Register (R/) */ + +} CMSDK_PWM_TypeDef; + + +/* CMSDK_PWM Register Definitions */ +#define CMSDK_PWM_TIMER_CNT_EN_Pos 1 /*!< CMSDK_PWM TCR: CNT_EN Position */ +#define CMSDK_PWM_TIMER_CNT_EN_Msk (0x01ul << CMSDK_PWM_TIMER_CNT_EN_Pos) /*!< CMSDK_PWM TCR: CNT_EN Mask */ + +#define CMSDK_PWM_TIMER_CNT_RET_Pos 0 /*!< CMSDK_PWM TCR: CNT_RET Position */ +#define CMSDK_PWM_TIMER_CNT_RET_Msk (0x01ul << CMSDK_PWM_TIMER_CNT_RET_Pos) /*!< CMSDK_PWM TCR: CNT_RET Mask */ + +#define CMSDK_PWM_MR6_INT_STS_Pos 6 /*!< CMSDK_PWM IR: PWMMR6_INT Position */ +#define CMSDK_PWM_MR6_INT_STS_Msk (0x01ul << CMSDK_PWM_MR6_INT_STS_Pos) /*!< CMSDK_PWM IR: PWMMR6_INT Mask */ + +#define CMSDK_PWM_MR5_INT_STS_Pos 5 /*!< CMSDK_PWM IR: PWMMR5_INT Position */ +#define CMSDK_PWM_MR5_INT_STS_Msk (0x01ul << CMSDK_PWM_MR5_INT_STS_Pos) /*!< CMSDK_PWM IR: PWMMR5_INT Mask */ + +#define CMSDK_PWM_MR4_INT_STS_Pos 4 /*!< CMSDK_PWM IR: PWMMR4_INT Position */ +#define CMSDK_PWM_MR4_INT_STS_Msk (0x01ul << CMSDK_PWM_MR4_INT_STS_Pos) /*!< CMSDK_PWM IR: PWMMR4_INT Mask */ + +#define CMSDK_PWM_MR3_INT_STS_Pos 3 /*!< CMSDK_PWM IR: PWMMR3_INT Position */ +#define CMSDK_PWM_MR3_INT_STS_Msk (0x01ul << CMSDK_PWM_MR3_INT_STS_Pos) /*!< CMSDK_PWM IR: PWMMR3_INT Mask */ + +#define CMSDK_PWM_MR2_INT_STS_Pos 2 /*!< CMSDK_PWM IR: PWMMR2_INT Position */ +#define CMSDK_PWM_MR2_INT_STS_Msk (0x01ul << CMSDK_PWM_MR2_INT_STS_Pos) /*!< CMSDK_PWM IR: PWMMR2_INT Mask */ + +#define CMSDK_PWM_MR1_INT_STS_Pos 1 /*!< CMSDK_PWM IR: PWMMR1_INT Position */ +#define CMSDK_PWM_MR1_INT_STS_Msk (0x01ul << CMSDK_PWM_MR1_INT_STS_Pos) /*!< CMSDK_PWM IR: PWMMR1_INT Mask */ + +#define CMSDK_PWM_MR0_INT_STS_Pos 0 /*!< CMSDK_PWM IR: PWMMR0_INT Position */ +#define CMSDK_PWM_MR0_INT_STS_Msk (0x01ul << CMSDK_PWM_MR0_INT_STS_Pos) /*!< CMSDK_PWM IR: PWMMR0_INT Mask */ + +#define CMSDK_PWM_MATCH_MR6_STP_Pos 20 /*!< CMSDK_PWM MCR: PWMMR6_STP Position */ +#define CMSDK_PWM_MATCH_MR6_STP_Msk (0x01ul << CMSDK_PWM_MATCH_MR6_STP_Pos) /*!< CMSDK_PWM MCR: PWMMR6_STP Mask */ + +#define CMSDK_PWM_MATCH_MR6_RET_Pos 19 /*!< CMSDK_PWM MCR: PWMMR6_RET Position */ +#define CMSDK_PWM_MATCH_MR6_RET_Msk (0x01ul << CMSDK_PWM_MATCH_MR6_RET_Pos) /*!< CMSDK_PWM MCR: PWMMR6_RET Mask */ + +#define CMSDK_PWM_MATCH_MR6_INT_Pos 18 /*!< CMSDK_PWM MCR: PWMMR6_INT Position */ +#define CMSDK_PWM_MATCH_MR6_INT_Msk (0x01ul << CMSDK_PWM_MATCH_MR6_INT_Pos) /*!< CMSDK_PWM MCR: PWMMR6_INT Mask */ + +#define CMSDK_PWM_MATCH_MR5_STP_Pos 17 /*!< CMSDK_PWM MCR: PWMMR5_STP Position */ +#define CMSDK_PWM_MATCH_MR5_STP_Msk (0x01ul << CMSDK_PWM_MATCH_MR5_STP_Pos) /*!< CMSDK_PWM MCR: PWMMR5_STP Mask */ + +#define CMSDK_PWM_MATCH_MR5_RET_Pos 16 /*!< CMSDK_PWM MCR: PWMMR5_RET Position */ +#define CMSDK_PWM_MATCH_MR5_RET_Msk (0x01ul << CMSDK_PWM_MATCH_MR5_RET_Pos) /*!< CMSDK_PWM MCR: PWMMR5_RET Mask */ + +#define CMSDK_PWM_MATCH_MR5_INT_Pos 15 /*!< CMSDK_PWM MCR: PWMMR5_INT Position */ +#define CMSDK_PWM_MATCH_MR5_INT_Msk (0x01ul << CMSDK_PWM_MATCH_MR5_INT_Pos) /*!< CMSDK_PWM MCR: PWMMR5_INT Mask */ + +#define CMSDK_PWM_MATCH_MR4_STP_Pos 14 /*!< CMSDK_PWM MCR: PWMMR4_STP Position */ +#define CMSDK_PWM_MATCH_MR4_STP_Msk (0x01ul << CMSDK_PWM_MATCH_MR4_STP_Pos) /*!< CMSDK_PWM MCR: PWMMR4_STP Mask */ + +#define CMSDK_PWM_MATCH_MR4_RET_Pos 13 /*!< CMSDK_PWM MCR: PWMMR4_RET Position */ +#define CMSDK_PWM_MATCH_MR4_RET_Msk (0x01ul << CMSDK_PWM_MATCH_MR4_RET_Pos) /*!< CMSDK_PWM MCR: PWMMR4_RET Mask */ + +#define CMSDK_PWM_MATCH_MR4_INT_Pos 12 /*!< CMSDK_PWM MCR: PWMMR4_INT Position */ +#define CMSDK_PWM_MATCH_MR4_INT_Msk (0x01ul << CMSDK_PWM_MATCH_MR4_INT_Pos) /*!< CMSDK_PWM MCR: PWMMR4_INT Mask */ + +#define CMSDK_PWM_MATCH_MR3_STP_Pos 11 /*!< CMSDK_PWM MCR: PWMMR3_STP Position */ +#define CMSDK_PWM_MATCH_MR3_STP_Msk (0x01ul << CMSDK_PWM_MATCH_MR3_STP_Pos) /*!< CMSDK_PWM MCR: PWMMR3_STP Mask */ + +#define CMSDK_PWM_MATCH_MR3_RET_Pos 10 /*!< CMSDK_PWM MCR: PWMMR3_RET Position */ +#define CMSDK_PWM_MATCH_MR3_RET_Msk (0x01ul << CMSDK_PWM_MATCH_MR3_RET_Pos) /*!< CMSDK_PWM MCR: PWMMR3_RET Mask */ + +#define CMSDK_PWM_MATCH_MR3_INT_Pos 9 /*!< CMSDK_PWM MCR: PWMMR3_INT Position */ +#define CMSDK_PWM_MATCH_MR3_INT_Msk (0x01ul << CMSDK_PWM_MATCH_MR3_INT_Pos) /*!< CMSDK_PWM MCR: PWMMR3_INT Mask */ + +#define CMSDK_PWM_MATCH_MR2_STP_Pos 8 /*!< CMSDK_PWM MCR: PWMMR2_STP Position */ +#define CMSDK_PWM_MATCH_MR2_STP_Msk (0x01ul << CMSDK_PWM_MATCH_MR2_STP_Pos) /*!< CMSDK_PWM MCR: PWMMR2_STP Mask */ + +#define CMSDK_PWM_MATCH_MR2_RET_Pos 7 /*!< CMSDK_PWM MCR: PWMMR2_RET Position */ +#define CMSDK_PWM_MATCH_MR2_RET_Msk (0x01ul << CMSDK_PWM_MATCH_MR2_RET_Pos) /*!< CMSDK_PWM MCR: PWMMR2_RET Mask */ + +#define CMSDK_PWM_MATCH_MR2_INT_Pos 6 /*!< CMSDK_PWM MCR: PWMMR2_INT Position */ +#define CMSDK_PWM_MATCH_MR2_INT_Msk (0x01ul << CMSDK_PWM_MATCH_MR2_INT_Pos) /*!< CMSDK_PWM MCR: PWMMR2_INT Mask */ + +#define CMSDK_PWM_MATCH_MR1_STP_Pos 5 /*!< CMSDK_PWM MCR: PWMMR1_STP Position */ +#define CMSDK_PWM_MATCH_MR1_STP_Msk (0x01ul << CMSDK_PWM_MATCH_MR1_STP_Pos) /*!< CMSDK_PWM MCR: PWMMR1_STP Mask */ + +#define CMSDK_PWM_MATCH_MR1_RET_Pos 4 /*!< CMSDK_PWM MCR: PWMMR1_RET Position */ +#define CMSDK_PWM_MATCH_MR1_RET_Msk (0x01ul << CMSDK_PWM_MATCH_MR1_RET_Pos) /*!< CMSDK_PWM MCR: PWMMR1_RET Mask */ + +#define CMSDK_PWM_MATCH_MR1_INT_Pos 3 /*!< CMSDK_PWM MCR: PWMMR1_INT Position */ +#define CMSDK_PWM_MATCH_MR1_INT_Msk (0x01ul << CMSDK_PWM_MATCH_MR1_INT_Pos) /*!< CMSDK_PWM MCR: PWMMR1_INT Mask */ + +#define CMSDK_PWM_MATCH_MR0_STP_Pos 2 /*!< CMSDK_PWM MCR: PWMMR0_STP Position */ +#define CMSDK_PWM_MATCH_MR0_STP_Msk (0x01ul << CMSDK_PWM_MATCH_MR0_STP_Pos) /*!< CMSDK_PWM MCR: PWMMR0_STP Mask */ + +#define CMSDK_PWM_MATCH_MR0_RET_Pos 1 /*!< CMSDK_PWM MCR: PWMMR0_RET Position */ +#define CMSDK_PWM_MATCH_MR0_RET_Msk (0x01ul << CMSDK_PWM_MATCH_MR0_RET_Pos) /*!< CMSDK_PWM MCR: PWMMR0_RET Mask */ + +#define CMSDK_PWM_MATCH_MR0_INT_Pos 0 /*!< CMSDK_PWM MCR: PWMMR0_INT Position */ +#define CMSDK_PWM_MATCH_MR0_INT_Msk (0x01ul << CMSDK_PWM_MATCH_MR0_INT_Pos) /*!< CMSDK_PWM MCR: PWMMR0_INT Mask */ + +#define CMSDK_PWM_CTRL_PWM6_EN_Pos 10 /*!< CMSDK_PWM PCR: PWMEN6 Position */ +#define CMSDK_PWM_CTRL_PWM6_EN_Msk (0x01ul << CMSDK_PWM_CTRL_PWM6_EN_Pos) /*!< CMSDK_PWM PCR: PWMEN6 Mask */ + +#define CMSDK_PWM_CTRL_PWM5_EN_Pos 9 /*!< CMSDK_PWM PCR: PWMEN5 Position */ +#define CMSDK_PWM_CTRL_PWM5_EN_Msk (0x01ul << CMSDK_PWM_CTRL_PWM5_EN_Pos) /*!< CMSDK_PWM PCR: PWMEN5 Mask */ + +#define CMSDK_PWM_CTRL_PWM4_EN_Pos 8 /*!< CMSDK_PWM PCR: PWMEN4 Position */ +#define CMSDK_PWM_CTRL_PWM4_EN_Msk (0x01ul << CMSDK_PWM_CTRL_PWM4_EN_Pos) /*!< CMSDK_PWM PCR: PWMEN4 Mask */ + +#define CMSDK_PWM_CTRL_PWM3_EN_Pos 7 /*!< CMSDK_PWM PCR: PWMEN3 Position */ +#define CMSDK_PWM_CTRL_PWM3_EN_Msk (0x01ul << CMSDK_PWM_CTRL_PWM3_EN_Pos) /*!< CMSDK_PWM PCR: PWMEN3 Mask */ + +#define CMSDK_PWM_CTRL_PWM2_EN_Pos 6 /*!< CMSDK_PWM PCR: PWMEN2 Position */ +#define CMSDK_PWM_CTRL_PWM2_EN_Msk (0x01ul << CMSDK_PWM_CTRL_PWM2_EN_Pos) /*!< CMSDK_PWM PCR: PWMEN2 Mask */ + +#define CMSDK_PWM_CTRL_PWM1_EN_Pos 5 /*!< CMSDK_PWM PCR: PWMEN1 Position */ +#define CMSDK_PWM_CTRL_PWM1_EN_Msk (0x01ul << CMSDK_PWM_CTRL_PWM1_EN_Pos) /*!< CMSDK_PWM PCR: PWMEN1 Mask */ + +#define CMSDK_PWM_CTRL_PWM6_SEL_Pos 4 /*!< CMSDK_PWM PCR: PWMSEL6 Position */ +#define CMSDK_PWM_CTRL_PWM6_SEL_Msk (0x01ul << CMSDK_PWM_CTRL_PWM6_SEL_Pos) /*!< CMSDK_PWM PCR: PWMSEL6 Mask */ + +#define CMSDK_PWM_CTRL_PWM5_SEL_Pos 3 /*!< CMSDK_PWM PCR: PWMSEL5 Position */ +#define CMSDK_PWM_CTRL_PWM5_SEL_Msk (0x01ul << CMSDK_PWM_CTRL_PWM5_SEL_Pos) /*!< CMSDK_PWM PCR: PWMSEL5 Mask */ + +#define CMSDK_PWM_CTRL_PWM4_SEL_Pos 2 /*!< CMSDK_PWM PCR: PWMSEL4 Position */ +#define CMSDK_PWM_CTRL_PWM4_SEL_Msk (0x01ul << CMSDK_PWM_CTRL_PWM4_SEL_Pos) /*!< CMSDK_PWM PCR: PWMSEL4 Mask */ + +#define CMSDK_PWM_CTRL_PWM3_SEL_Pos 1 /*!< CMSDK_PWM PCR: PWMSEL3 Position */ +#define CMSDK_PWM_CTRL_PWM3_SEL_Msk (0x01ul << CMSDK_PWM_CTRL_PWM3_SEL_Pos) /*!< CMSDK_PWM PCR: PWMSEL3 Mask */ + +#define CMSDK_PWM_CTRL_PWM2_SEL_Pos 0 /*!< CMSDK_PWM PCR: PWMSEL2 Position */ +#define CMSDK_PWM_CTRL_PWM2_SEL_Msk (0x01ul << CMSDK_PWM_CTRL_PWM2_SEL_Pos) /*!< CMSDK_PWM PCR: PWMSEL2 Mask */ + +#define CMSDK_PWM_LOAD_ML6_EN_Pos 6 /*!< CMSDK_PWM LER: PWMML6_EN Position */ +#define CMSDK_PWM_LOAD_ML6_EN_Msk (0x01ul << CMSDK_PWM_LOAD_ML6_EN_Pos) /*!< CMSDK_PWM LER: PWMML6_EN Mask */ + +#define CMSDK_PWM_LOAD_ML5_EN_Pos 5 /*!< CMSDK_PWM LER: PWMML5_EN Position */ +#define CMSDK_PWM_LOAD_ML5_EN_Msk (0x01ul << CMSDK_PWM_LOAD_ML5_EN_Pos) /*!< CMSDK_PWM LER: PWMML5_EN Mask */ + +#define CMSDK_PWM_LOAD_ML4_EN_Pos 4 /*!< CMSDK_PWM LER: PWMML4_EN Position */ +#define CMSDK_PWM_LOAD_ML4_EN_Msk (0x01ul << CMSDK_PWM_LOAD_ML4_EN_Pos) /*!< CMSDK_PWM LER: PWMML4_EN Mask */ + +#define CMSDK_PWM_LOAD_ML3_EN_Pos 3 /*!< CMSDK_PWM LER: PWMML3_EN Position */ +#define CMSDK_PWM_LOAD_ML3_EN_Msk (0x01ul << CMSDK_PWM_LOAD_ML3_EN_Pos) /*!< CMSDK_PWM LER: PWMML3_EN Mask */ + +#define CMSDK_PWM_LOAD_ML2_EN_Pos 2 /*!< CMSDK_PWM LER: PWMML2_EN Position */ +#define CMSDK_PWM_LOAD_ML2_EN_Msk (0x01ul << CMSDK_PWM_LOAD_ML2_EN_Pos) /*!< CMSDK_PWM LER: PWMML2_EN Mask */ + +#define CMSDK_PWM_LOAD_ML1_EN_Pos 1 /*!< CMSDK_PWM LER: PWMML1_EN Position */ +#define CMSDK_PWM_LOAD_ML1_EN_Msk (0x01ul << CMSDK_PWM_LOAD_ML1_EN_Pos) /*!< CMSDK_PWM LER: PWMML1_EN Mask */ + +#define CMSDK_PWM_LOAD_ML0_EN_Pos 0 /*!< CMSDK_PWM LER: PWMML0_EN Position */ +#define CMSDK_PWM_LOAD_ML0_EN_Msk (0x01ul << CMSDK_PWM_LOAD_ML0_EN_Pos) /*!< CMSDK_PWM LER: PWMML0_EN Mask */ +/*@}*/ /* end of group CMSDK_PWM */ + + +/*----------------------------- Timer (TIMER) -------------------------------*/ +/** @addtogroup CMSDK_TIMER CMSDK Timer + @{ +*/ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */ + __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */ + __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ + }; + +} CMSDK_TIMER_TypeDef; + +/* CMSDK_TIMER CTRL Register Definitions */ + +#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /*!< CMSDK_TIMER CTRL: IRQEN Position */ +#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /*!< CMSDK_TIMER CTRL: IRQEN Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /*!< CMSDK_TIMER CTRL: SELEXTCLK Position */ +#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /*!< CMSDK_TIMER CTRL: SELEXTCLK Mask */ + +#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /*!< CMSDK_TIMER CTRL: SELEXTEN Position */ +#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /*!< CMSDK_TIMER CTRL: SELEXTEN Mask */ + +#define CMSDK_TIMER_CTRL_EN_Pos 0 /*!< CMSDK_TIMER CTRL: EN Position */ +#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /*!< CMSDK_TIMER CTRL: EN Mask */ + +#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /*!< CMSDK_TIMER VALUE: CURRENT Position */ +#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /*!< CMSDK_TIMER VALUE: CURRENT Mask */ + +#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /*!< CMSDK_TIMER RELOAD: RELOAD Position */ +#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /*!< CMSDK_TIMER RELOAD: RELOAD Mask */ + +#define CMSDK_TIMER_INTSTATUS_Pos 0 /*!< CMSDK_TIMER INTSTATUS: INTSTATUSPosition */ +#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /*!< CMSDK_TIMER INTSTATUS: INTSTATUSMask */ + +#define CMSDK_TIMER_INTCLEAR_Pos 0 /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Position */ +#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /*!< CMSDK_TIMER INTCLEAR: INTCLEAR Mask */ + +/*@}*/ /* end of group CMSDK_TIMER */ + + +/*----------------------------- Dual Timer (DUALTIMER) -------------------------------*/ +/** @addtogroup CMSDK_DUALTIMER Dual Timer + @{ +*/ +typedef struct +{ + __IO uint32_t TimerLoad; /*!< Offset: 0x000 Timer1 load Register (R/W) */ + __I uint32_t TimerValue; /*!< Offset: 0x004 Timer1 Current Value Register (R/) */ + __IO uint32_t TimerControl; /*!< Offset: 0x008 Timer1 Control Register (R/W) */ + __O uint32_t TimerIntClr; /*!< Offset: 0x00C Timer1 Interrupt Clear Register (/W) */ + __I uint32_t TimerRIS; /*!< Offset: 0x010 Timer1 Raw Interrupt Status Register (R/) */ + __I uint32_t TimerMIS; /*!< Offset: 0x014 Timer1 Masked Interrupt Status Register (R/) */ + __IO uint32_t TimerBGLoad; /*!< Offset: 0x018 Timer1 Background load Register (R/W) */ + +} CMSDK_DUALTIMER_TypeDef; + +/* CMSDK_DUALTIMER Register Definitions */ +#define CMSDK_DUALTIMER_LOAD_Pos 0 /*!< CMSDK_DUALTIMER LOAD: LOAD Position */ +#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /*!< CMSDK_DUALTIMER LOAD: LOAD Mask */ + +#define CMSDK_DUALTIMER_VALUE_Pos 0 /*!< CMSDK_DUALTIMER VALUE: VALUE Position */ +#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /*!< CMSDK_DUALTIMER VALUE: VALUE Mask */ + +#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */ +#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /*!< CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */ +#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /*!< CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */ + +#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */ +#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /*!< CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */ + +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */ +#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /*!< CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */ + +#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */ +#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /*!< CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */ + +#define CMSDK_DUALTIMER_CTRL_ONESHOT_Pos 0 /*!< CMSDK_DUALTIMER CTRL_ONESHOT: CTRL ONESHOT Position */ +#define CMSDK_DUALTIMER_CTRL_ONESHOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOT_Pos) /*!< CMSDK_DUALTIMER CTRL_ONESHOT: CTRL ONESHOT Mask */ + +#define CMSDK_DUALTIMER_INTCLR_Pos 0 /*!< CMSDK_DUALTIMER INTCLR: INT Clear Position */ +#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /*!< CMSDK_DUALTIMER INTCLR: INT Clear Mask */ + +#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */ +#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /*!< CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */ + +#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */ +#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /*!< CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */ + +#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /*!< CMSDK_DUALTIMER BGLOAD: Background Load Position */ +#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /*!< CMSDK_DUALTIMER BGLOAD: Background Load Mask */ +/*@}*/ /* end of group CMSDK_DUALTIMER */ + + +/*-------------------- Real Time Clock (RTC) -------------------*/ + +/** @addtogroup CMSDK_RTC RTC + @{ +*/ +typedef struct +{ + __IO uint32_t TR; /*!< Offset: 0x000 RTC Time Register (R/W) */ + __IO uint32_t DR; /*!< Offset: 0x004 RTC Date Register (R/W) */ + __IO uint32_t TAR; /*!< Offset: 0x008 RTC Time Alarm Register (R/W) */ + __IO uint32_t DAR; /*!< Offset: 0x00C RTC Date Alarm Register (R/W) */ + __IO uint32_t IER; /*!< Offset: 0x010 Interrupt Enable Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x014 Interrupt Status Register (R/) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x014 Interrupt Clear Register ( /W) */ + }; + __IO uint32_t CR; /*!< Offset: 0x018 RTC Control Register (R/W) */ + __IO uint32_t PR; /*!< Offset: 0x01C RTC Prescaler Register (R/W) */ + __IO uint32_t WTR; /*!< Offset: 0x020 RTC Wakeup Timer Register (R/W) */ + __IO uint32_t WPR; /*!< Offset: 0x024 RTC Wakeup Prescaler Register (R/W) */ + __I uint32_t SR; /*!< Offset: 0x028 RTC Status Register (R/) */ + +} CMSDK_RTC_TypeDef; + + +/* CMSDK_RTC Register Definitions */ +#define CMSDK_RTC_WUT_CLK_EN_Pos 5 /*!< CMSDK_RTC CR: WUT_CLK_EN Position */ +#define CMSDK_RTC_WUT_CLK_EN_Msk (0x01ul << CMSDK_RTC_WUT_CLK_EN_Pos) /*!< CMSDK_RTC CR: WUT_CLK_EN Mask */ + +#define CMSDK_RTC_WUT_EN_Pos 4 /*!< CMSDK_RTC CR: WUT_EN Position */ +#define CMSDK_RTC_WUT_EN_Msk (0x01ul << CMSDK_RTC_WUT_EN_Pos) /*!< CMSDK_RTC CR: WUT_EN Mask */ + +#define CMSDK_RTC_ALARM_EN_Pos 3 /*!< CMSDK_RTC CR: ALARM_EN Position */ +#define CMSDK_RTC_ALARM_EN_Msk (0x01ul << CMSDK_RTC_ALARM_EN_Pos) /*!< CMSDK_RTC CR: ALARM_EN Mask */ + +#define CMSDK_RTC_DATA_MODE_Pos 2 /*!< CMSDK_RTC CR: DATA_MODE Position */ +#define CMSDK_RTC_DATA_MODE_Msk (0x01ul << CMSDK_RTC_DATA_MODE_Pos) /*!< CMSDK_RTC CR: DATA_MODE Mask */ + +#define CMSDK_RTC_HOUR_MODE_Pos 1 /*!< CMSDK_RTC CR: HOUR_MODE Position */ +#define CMSDK_RTC_HOUR_MODE_Msk (0x01ul << CMSDK_RTC_HOUR_MODE_Pos) /*!< CMSDK_RTC CR: HOUR_MODE Mask */ + +#define CMSDK_RTC_INIT_EN_Pos 0 /*!< CMSDK_RTC CR: INIT_EN Position */ +#define CMSDK_RTC_INIT_EN_Msk (0x01ul << CMSDK_RTC_INIT_EN_Pos) /*!< CMSDK_RTC CR: INIT_EN Mask */ + +#define CMSDK_RTC_WUT_IE_Pos 1 /*!< CMSDK_RTC IER: WUT_IE Position */ +#define CMSDK_RTC_WUT_IE_Msk (0x01ul << CMSDK_RTC_WUT_IE_Pos) /*!< CMSDK_RTC IER: WUT_IE Mask */ + +#define CMSDK_RTC_ALARM_IE_Pos 0 /*!< CMSDK_RTC IER: ALARM_IE Position */ +#define CMSDK_RTC_ALARM_IE_Msk (0x01ul << CMSDK_RTC_ALARM_IE_Pos) /*!< CMSDK_RTC IER: ALARM_IE Mask */ + +#define CMSDK_RTC_WUT_VAL_SYNC_READY_Pos 3 /*!< CMSDK_RTC SR: WUT_VAL_SYNC_READY Position */ +#define CMSDK_RTC_WUT_VAL_SYNC_READY_Msk (0x01ul << CMSDK_RTC_WUT_VAL_SYNC_READY_Pos) /*!< CMSDK_RTC SR: WUT_VAL_SYNC_READY Mask */ + +#define CMSDK_RTC_WUT_PRES_SYNC_READY_Pos 2 /*!< CMSDK_RTC SR: WUT_PRES_SYNC_READY Position */ +#define CMSDK_RTC_WUT_PRES_SYNC_READY_Msk (0x01ul << CMSDK_RTC_WUT_PRES_SYNC_READY_Pos) /*!< CMSDK_RTC SR: WUT_PRES_SYNC_READY Mask */ + +#define CMSDK_RTC_PRES_SYNC_READY_Pos 1 /*!< CMSDK_RTC SR: RTC PRES_SYNC_READY Position */ +#define CMSDK_RTC_PRES_SYNC_READY_Msk (0x01ul << CMSDK_RTC_PRES_SYNC_READY_Pos) /*!< CMSDK_RTC SR: RTC PRES_SYNC_READY Mask */ + +#define CMSDK_RTC_INIT_SYNC_READY_Pos 0 /*!< CMSDK_RTC SR: INIT_SYNC_READY Position */ +#define CMSDK_RTC_INIT_SYNC_READY_Msk (0x01ul << CMSDK_RTC_INIT_SYNC_READY_Pos) /*!< CMSDK_RTC SR: INIT_SYNC_READY Mask */ +/*@}*/ /* end of group CMSDK_RTC */ + + +/*-------------------- General Purpose Input Output (GPIO) -------------------*/ + +/** @addtogroup CMSDK_GPIO CMSDK GPIO + @{ +*/ +typedef struct +{ + __I uint32_t DATAIN; /*!< Offset: 0x000 Data input Register (R/) */ + __IO uint32_t DATAOUT; /*!< Offset: 0x004 Data Output Register (R/W) */ + __IO uint32_t BITSET; /*!< Offset: 0x008 DataOut Bit Set Register (R/W) */ + __IO uint32_t BITCLR; /*!< Offset: 0x00C DataOut Bit Clear Register (R/W) */ + __IO uint32_t OE; /*!< Offset: 0x010 Output Enable Register (R/W) */ + __IO uint32_t IE; /*!< Offset: 0x014 Input Enable Register (R/W) */ + __IO uint32_t PU; /*!< Offset: 0x018 Pull Up Register (R/W) */ + __IO uint32_t PD; /*!< Offset: 0x01C Pull Down Register (R/W) */ + __IO uint32_t CS; /*!< Offset: 0x020 CMOS/Schmitt Input Type Register (R/W) */ + __IO uint32_t SL; /*!< Offset: 0x024 Slew Rate Register (R/W) */ + __IO uint32_t OPDRV0; /*!< Offset: 0x028 Output Drive Strength 0 Register (R/W) */ + __IO uint32_t OPDRV1; /*!< Offset: 0x02C Output Drive Strength 1 Register (R/W) */ + __IO uint32_t ODEN; /*!< Offset: 0x030 Open drain Enable Register (R/W) */ + __IO uint32_t ALTFL; /*!< Offset: 0x034 Alternate function select Register (R/W) */ + __IO uint32_t ALTFH; /*!< Offset: 0x038 Alternate function select Register (R/W) */ + __IO uint32_t ANAEN; /*!< Offset: 0x03C Analog Channel Enable Register (R/W) */ +} CMSDK_GPIO_TypeDef; + +#define CMSDK_GPIO_DATA_Pos 0 /*!< CMSDK_GPIO DATAIN: DATAIN Position */ +#define CMSDK_GPIO_DATA_Msk (0xFFFFFFul << CMSDK_GPIO_DATA_Pos) /*!< CMSDK_GPIO DATAIN: DATAIN Mask */ + +#define CMSDK_GPIO_DATAOUT_Pos 0 /*!< CMSDK_GPIO DATAOUT: DATAOUT Position */ +#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFFFul << CMSDK_GPIO_DATAOUT_Pos) /*!< CMSDK_GPIO DATAOUT: DATAOUT Mask */ + + +/*@}*/ /* end of group CMSDK_GPIO */ + + +/*------------- System Control (SYSCON) --------------------------------------*/ +/** @addtogroup CMSDK_SYSCON CMSDK System Control + @{ +*/ +typedef struct +{ + __IO uint32_t CLK_CFG; /*!< Offset: 0x000 Clock Configuration Register (R/W) */ + __IO uint32_t HSI_CTRL; /*!< Offset: 0x004 HSI Control Register (R/W) */ + __IO uint32_t LSI_CTRL; /*!< Offset: 0x008 LSI Control Register (R/W) */ + __IO uint32_t LSE_CTRL; /*!< Offset: 0x00C LSE Control Register (R/W) */ + __IO uint32_t AHB_CLKEN; /*!< Offset: 0x010 AHB Peripheral Clock Enable Register (R/W) */ + __IO uint32_t APB_CLKEN; /*!< Offset: 0x014 APB Peripheral Clock Enable Register (R/W) */ + __IO uint32_t PERI_CLKEN; /*!< Offset: 0x018 Peripheral Working Clock Enable Register (R/W) */ + __IO uint32_t SLP_PCLKEN; /*!< Offset: 0x01C APB Peripheral Clock Enable in Sleep/Stop mode Register (R/W) */ + __IO uint32_t RST_CTRL; /*!< Offset: 0x020 Reset Control Register (R/W) */ + union { + __I uint32_t RST_FLAG_STS; /*!< Offset: 0x024 Reset Flag Status Register (R/) */ + __O uint32_t RST_FLAG_CLR; /*!< Offset: 0x024 Reset Flag Clear Register (/W) */ + }; + __O uint32_t PRST_KEY; /*!< Offset: 0x028 Peripheral Reset Enable Key Register (/W) */ + __IO uint32_t AHB_RST; /*!< Offset: 0x02C AHB Peripheral Reset Register (R/W) */ + __IO uint32_t APB_RST; /*!< Offset: 0x030 APB Peripheral Reset Register (R/W) */ + __IO uint32_t SYS_CFG; /*!< Offset: 0x034 System Configuration Register (R/W) */ + __IO uint32_t PMU_CTRL; /*!< Offset: 0x038 PMU Control Register (R/W) */ +} CMSDK_SYSCON_TypeDef; + +#define CMSDK_SYSCON_SYSCLK_SEL_Pos 0 +#define CMSDK_SYSCON_SYSCLK_SEL_Msk (0x03ul << CMSDK_SYSCON_SYSCLK_SEL_Pos) /*!< CMSDK_SYSCON CLK_CFG: SYSCLK_SEL Mask */ + +#define CMSDK_SYSCON_SYSCLK_SWSTS_Pos 2 +#define CMSDK_SYSCON_SYSCLK_SWSTS_Msk (0x03ul << CMSDK_SYSCON_SYSCLK_SWSTS_Pos) /*!< CMSDK_SYSCON CLK_CFG: SYSCLK_SWSTS Mask */ + +#define CMSDK_SYSCON_LFCLK_SEL_Pos 4 +#define CMSDK_SYSCON_LFCLK_SEL_Msk (0x01ul << CMSDK_SYSCON_LFCLK_SEL_Pos) /*!< CMSDK_SYSCON CLK_CFG: LFCLK_SEL Mask */ + +#define CMSDK_SYSCON_LFCLK_SWSTS_Pos 5 +#define CMSDK_SYSCON_LFCLK_SWSTS_Msk (0x01ul << CMSDK_SYSCON_LFCLK_SWSTS_Pos) /*!< CMSDK_SYSCON CLK_CFG: LFCLK_SWSTS Mask */ + +#define CMSDK_SYSCON_AHB_PRES_Pos 8 +#define CMSDK_SYSCON_AHB_PRES_Msk (0x07ul << CMSDK_SYSCON_AHB_PRES_Pos) /*!< CMSDK_SYSCON CLK_CFG: AHB_PRES Mask */ + +#define CMSDK_SYSCON_APB_PRES_Pos 12 +#define CMSDK_SYSCON_APB_PRES_Msk (0x07ul << CMSDK_SYSCON_APB_PRES_Pos) /*!< CMSDK_SYSCON CLK_CFG: APB_PRES Mask */ + +#define CMSDK_SYSCON_MCO_SEL_Pos 16 +#define CMSDK_SYSCON_MCO_SEL_Msk (0x03ul << CMSDK_SYSCON_MCO_SEL_Pos) /*!< CMSDK_SYSCON CLK_CFG: MCO_SEL Mask */ + +#define CMSDK_SYSCON_HSI_EN_Pos 0 +#define CMSDK_SYSCON_HSI_EN_Msk (0x01ul << CMSDK_SYSCON_HSI_EN_Pos) /*!< CMSDK_SYSCON HSI_CTRL: HSI_FREQ Mask */ + +#define CMSDK_SYSCON_HSI_FREQ_Pos 4 +#define CMSDK_SYSCON_HSI_FREQ_Msk (0x03ul << CMSDK_SYSCON_HSI_FREQ_Pos) /*!< CMSDK_SYSCON HSI_CTRL: HSI_FREQ Mask */ + +#define CMSDK_SYSCON_LSI_EN_Pos 0 +#define CMSDK_SYSCON_LSI_EN_Msk (0x01ul << CMSDK_SYSCON_LSI_EN_Pos) /*!< CMSDK_SYSCON LSI_CTRL: LSI_EN Mask */ + +#define CMSDK_SYSCON_LSE_EN_Pos 0 +#define CMSDK_SYSCON_LSE_EN_Msk (0x03ul << CMSDK_SYSCON_LSE_EN_Pos) /*!< CMSDK_SYSCON LSE_CTRL: LSE_EN Mask */ + +#define CMSDK_SYSCON_AHB_PORT_CLKEN_Pos 0 +#define CMSDK_SYSCON_AHB_PORT_CLKEN_Msk (0x07ul << CMSDK_SYSCON_AHB_PORT_CLKEN_Pos) /*!< CMSDK_SYSCON AHB Peri CLK_EN : AHB_PORT_CLKCEN */ + +#define CMSDK_SYSCON_APB_PORT_CLKEN_Pos 0 +#define CMSDK_SYSCON_APB_PORT_CLKEN_Msk (0xFFul << CMSDK_SYSCON_APB_PORT_CLKEN_Pos) /*!< CMSDK_SYSCON APB Peri CLK_EN: APB_PORT_CLKEN */ + +#define CMSDK_SYSCON_RTC_CLKEN_Pos 0 +#define CMSDK_SYSCON_RTC_CLKEN_Msk (0x01ul << CMSDK_SYSCON_RTC_CLKEN_Pos) /*!< CMSDK_SYSCON Peri Working CLK_EN: RTC_CLKEN Mask */ + +#define CMSDK_SYSCON_APB_SLP_CLKEN_Pos 0 +#define CMSDK_SYSCON_APB_SLP_CLKEN_Msk (0xFFul << CMSDK_SYSCON_APB_SLP_CLKEN_Pos) /*!< CMSDK_SYSCON Peri APB CLK_EN in sleep/stop mode: APB_SLP_CLKEN Mask */ + +#define CMSDK_SYSCON_LOCKUP_RESETEN_Pos 0 +#define CMSDK_SYSCON_LOCKUP_RESETEN_Msk (0x01ul << CMSDK_SYSCON_LOCKUP_RESETEN_Pos) /*!< CMSDK_SYSCON RST_CTRL: LOCKUP_RESETN Mask */ + +#define CMSDK_SYSCON_PORRST_FLAG_Pos 0 +#define CMSDK_SYSCON_PORRST_FLAG_Msk (0x01ul << CMSDK_SYSCON_PORRST_FLAG_Pos) /*!< CMSDK_SYSCON RST_FLAG_STS: PORRST_FLAG Mask */ + +#define CMSDK_SYSCON_WDTRST_FLAG_Pos 2 +#define CMSDK_SYSCON_WDTRST_FLAG_Msk (0x01ul << CMSDK_SYSCON_WDTRST_FLAG_Pos) /*!< CMSDK_SYSCON RST_FLAG_STS: WDTRST_FLAG Mask */ + +#define CMSDK_SYSCON_SOFTRST_FLAG_Pos 1 +#define CMSDK_SYSCON_SOFTRST_FLAG_Msk (0x01ul << CMSDK_SYSCON_SOFTRST_FLAG_Pos) /*!< CMSDK_SYSCON RST_FLAG_STS: SOFTRST_FLAG Mask */ + +#define CMSDK_SYSCON_LOCKUPRST_FLAG_Pos 3 +#define CMSDK_SYSCON_LOCKUPRST_FLAG_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_FLAG_Pos) /*!< CMSDK_SYSCON RST_FLAG_STS: LOCKUPRST_FLAG Mask */ + +#define CMSDK_SYSCON_PINRST_FLAG_Pos 4 +#define CMSDK_SYSCON_PINRST_FLAG_Msk (0x01ul << CMSDK_SYSCON_PINRST_FLAG_Pos) /*!< CMSDK_SYSCON RST_FLAG_STS: PINRST_FLAG Mask */ + +#define CMSDK_SYSCON_PINTEST_FLAG_Pos 5 +#define CMSDK_SYSCON_PINTEST_FLAG_Msk (0x01ul << CMSDK_SYSCON_PINTEST_FLAG_Pos) /*!< CMSDK_SYSCON RST_FLAG_STS: PINTEST_FLAG Mask */ + +#define CMSDK_SYSCON_PRST_KEY_Pos 0 +#define CMSDK_SYSCON_PRST_KEY_Msk (0xFFFFul << CMSDK_SYSCON_PRST_KEY_Pos) /*!< CMSDK_SYSCON Peri RST_ENKEY: PRST_KEY Mask */ + +#define CMSDK_SYSCON_AHB_PORT_RST_Pos 0 +#define CMSDK_SYSCON_AHB_PORT_RST_Msk (0x07ul << CMSDK_SYSCON_AHB_PORT_RST_Pos) /*!< CMSDK_SYSCON AHB Peri RST_Reg: AHB_PORT_RST Mask */ + +#define CMSDK_SYSCON_APB_PORT_RST_Pos 0 +#define CMSDK_SYSCON_APB_PORT_RST_Msk (0xFFul << CMSDK_SYSCON_APB_PORT_RST_Pos) /*!< CMSDK_SYSCON APB Peri RST_Reg: APB_PORT_RST Mask */ + +#define CMSDK_SYSCON_BOOT_MODE_Pos 8 +#define CMSDK_SYSCON_BOOT_MODE_Msk (0x03ul << CMSDK_SYSCON_BOOT_MODE_Pos) /*!< CMSDK_SYSCON SYS_CFG: BOOT_MODE Mask */ + +#define CMSDK_SYSCON_REMAP_Pos 0 +#define CMSDK_SYSCON_REMAP_Msk (0x03ul << CMSDK_SYSCON_REMAP_Pos) /*!< CMSDK_SYSCON SYS_CFG: REMAP Mask */ + +//#define CMSDK_SYSCON_BG_STPDIS_Pos 0 +//#define CMSDK_SYSCON_BG_STPDIS_Msk (0x01ul << CMSDK_SYSCON_BG_STPDIS_Pos) /*!< CMSDK_SYSCON PMU_CTRL: BG_STPDI Mask */ + +#define CMSDK_SYSCON_WKFREQ_SEL_Pos 0 +#define CMSDK_SYSCON_WKFREQ_SEL_Msk (0x01ul << CMSDK_SYSCON_WKFREQ_SEL_Pos) /*!< CMSDK_SYSCON PMU_CTRL: WKFREQ_SEL Mask */ + +#define CMSDK_SYSCON_WKUP_DLY_Pos 4 +#define CMSDK_SYSCON_WKUP_DLY_Msk (0x03ul << CMSDK_SYSCON_WKUP_DLY_Pos) /*!< CMSDK_SYSCON PMU_CTRL: WKUP_DLY Mask */ + + +/*@}*/ /* end of group CMSDK_SYSCON */ + +/*------------ Extended Interrupt and Event Controller (EXTI) --------------------------------------*/ +/** @addtogroup CMSDK_EXTI + @{ +*/ +typedef struct +{ + __IO uint32_t RTSR; /*!< Offset: 0x000 Rising Trigger Selection Register (R/W) */ + __IO uint32_t FTSR; /*!< Offset: 0x004 Falling Trigger Selection Register (R/W) */ + __O uint32_t SWIER; /*!< Offset: 0x008 Software Interrupt Event Register (/W) */ + union { + __I uint32_t RISE_PEND_STS; /*!< Offset: 0x00C Rising Edge Pending Status Register (R/) */ + __O uint32_t RISE_PEND_CLR; /*!< Offset: 0x00C Rising Edge Pending Clear Register (/W) */ + }; + union { + __I uint32_t FALL_PEND_STS; /*!< Offset: 0x010 Falling Edge Pending Status Register (R/) */ + __O uint32_t FALL_PEND_CLR; /*!< Offset: 0x010 Falling Edge Pending Clear Register (/W) */ + }; + __IO uint32_t IMR; /*!< Offset: 0x014 CPU Wakeup with Interrupt Mask Register (R/W) */ + __IO uint32_t EMR; /*!< Offset: 0x018 CPU Wakeup with Event Mask Register (R/W) */ +} CMSDK_EXTI_TypeDef; + + +/*@}*/ /* end of group CMSDK_EXTI */ + +/*------------ MTP Controller (MTP) --------------------------------------*/ +/** @addtogroup CMSDK_MTP + @{ +*/ +typedef struct +{ + __IO uint32_t MTP_CR; /*!< Offset: 0x000 MTP Controller Control register (R/W) */ + union { + __I uint32_t MTP_SR; /*!< Offset: 0x004 MTP Controller Status Register (R/) */ + __O uint32_t MTP_CLR; /*!< Offset: 0x004 MTP Controller clear Register (/W) */ + }; + __IO uint32_t MTP_ACLR; /*!< Offset: 0x008 MTP Controller Application Code Lock Register (R/W) */ + __O uint32_t MTP_KEYR; /*!< Offset: 0x00C MTP Controller Key Register(/W) */ + __IO uint32_t MTP_IER; /*!< Offset: 0x010 MTP Controller Interrupt Enable register (R/W) */ + __I uint32_t MTP_UCR; /*!< Offset: 0x014 MTP User Configuration register (R/) */ + __IO uint32_t MTP_INF_EPM_ADR; /*!< Offset: 0x018 MTP Information EEPROM Address register (R/W) */ + __IO uint32_t MTP_INF_EPM_WDATA; /*!< Offset: 0x01C MTP Information EEPROM Writing Data register (R/W) */ + __I uint32_t MTP_INF_EPM_RDATA; /*!< Offset: 0x020 MTP Information EEPROM Reading Data register (R/) */ + __I uint32_t MTP_DBG; /*!< Offset: 0x024 MTP Debug Data register (R/) */ + __I uint32_t MTP_DEVICE_ID1; /*!< Offset: 0x028 MTP Device ID1 register (R/) */ + __I uint32_t MTP_DEVICE_ID2; /*!< Offset: 0x02C MTP Device ID2 register (R/) */ + __I uint32_t MTP_DEVICE_ID3; /*!< Offset: 0x030 MTP Device ID3 register (R/) */ + __IO uint32_t MTP_OSCA_FT; /*!< Offset: 0x034 MTP OSCA_FT Trim register (R/W) */ + __IO uint32_t MTP_OSC32K_RTTRIM; /*!< Offset: 0x038 MTP OSC32K_RTTRIM Trim register (R/W) */ + __IO uint32_t MTP_BG_TRIM; /*!< Offset: 0x03C MTP BG Trim register (R/W) */ +} CMSDK_MTPREG_TypeDef; + +#define CMSDK_MTPREG_MTP_INF_EPM_RDATA_Pos 0 +#define CMSDK_MTPREG_MTP_INF_EPM_RDATA_Msk (0x100ul << CMSDK_MTPREG_MTP_INF_EPM_RDATA_Pos) /*!< CMSDK_MTPREG MTP_INF_EPM_RDATA: MTP_INF_EPM_RDATA Mask */ + +#define CMSDK_MTPREG_MTP_SR_KEY_STA_Pos 7 +#define CMSDK_MTPREG_MTP_SR_KEY_STA_Msk (0x03ul << CMSDK_MTPREG_MTP_INF_EPM_RDATA_Pos) /*!< CMSDK_MTPREG MTP_INF_EPM_RDATA: MTP_INF_EPM_RDATA Mask */ + + +/*@}*/ /* end of group CMSDK_MTPREG */ + +/*------------ LCD Controller (LCD) --------------------------------------*/ +/** @addtogroup CMSDK_LCD + @{ +*/ +typedef struct +{ + __IO uint32_t LCD_CR; /*!< Offset: 0x000 LCD Controller LCD Control Register (R/W) */ + __IO uint32_t COM0_SEG; /*!< Offset: 0x004 LCD Controller LCD data buffer Registers(COM0) (R/W) */ + __IO uint32_t COM1_SEG; /*!< Offset: 0x008 LCD Controller LCD data buffer Registers(COM1) (R/W) */ + __IO uint32_t COM2_SEG; /*!< Offset: 0x00C LCD Controller LCD data buffer Registers(COM2) (R/W) */ + __IO uint32_t COM3_SEG; /*!< Offset: 0x010 LCD Controller LCD data buffer Registers(COM3) (R/W) */ + __IO uint32_t LCD_FCR; /*!< Offset: 0x014 LCD Controller LCD Frequency Control Register (R/W) */ + __IO uint32_t LCD_FLKT; /*!< Offset: 0x018 LCD Controller LCD Flick Time Register (R/W) */ + __IO uint32_t LCD_COM_EN; /*!< Offset: 0x01C LCD Controller LCD COM Enable Register (R/W) */ + __IO uint32_t LCD_SEG_EN; /*!< Offset: 0x020 LCD Controller LCD SEG Enable Register (R/W) */ + __IO uint32_t LCD_IER; /*!< Offset: 0x024 LCD Controller LCD Interrupt Enable Register (R/W) */ + union { + __I uint32_t LCD_ISR; /*!< Offset: 0x028 LCD Controller LCD Interrupt Status Register (R) */ + __O uint32_t LCD_INT_CLR; /*!< Offset: 0x028 LCD Controller LCD Interrupt Status Register (W) */ + }; + __IO uint32_t LCD_BIAS; /*!< Offset: 0x02C LCD Controller LCD BIAS Register */ +} CMSDK_LCD_TypeDef; + +#define CMSDK_LCD_ENABLE_Pos 2 +#define CMSDK_LCD_ENABLE_Msk (0x01ul << CMSDK_LCD_ENABLE_Pos) /*!< CMSDK_LCD_CR REG LCD_ENABLE: LCD ENABLE Mask */ + +#define CMSDK_LCD_FLICK_ENABLE_Pos 14 +#define CMSDK_LCD_FLICK_ENABLE_Msk (0x01ul << CMSDK_LCD_FLICK_ENABLE_Pos) /*!< CMSDK_LCD_CR REG FLICK_ENABLE: LCD FLICK_ENABLE Mask */ + +#define CMSDK_LCD_FCR_DF_Pos 0 +#define CMSDK_LCD_FCR_DF_Msk (0xFFul << CMSDK_LCD_FCR_DF_Pos) /*!< CMSDK_LCD_FCR REG Display FREQ: LCD DISPLAY FREQ Mask */ + +#define CMSDK_LCD_FLKT_TON_Pos 0 +#define CMSDK_LCD_FLKT_TON_Msk (0xFFul << CMSDK_LCD_FLKT_TON_Pos) /*!< CMSDK_LCD_FLKT REG TON(display on time): CMSDK_LCD_FLK_TON Mask */ + +#define CMSDK_LCD_FLKT_TOFF_Pos 8 +#define CMSDK_LCD_FLKT_TOFF_Msk (0xFFul << CMSDK_LCD_FLKT_TOFF_Pos) /*!< CMSDK_LCD_FLKT REG TOFF(display off time): CMSDK_LCD_FLK_TOFF Mask */ + +#define CMSDK_LCD_IER_DONIE_Pos 1 +#define CMSDK_LCD_IER_DONIE_Msk (0x01ul << CMSDK_LCD_IER_DONIE_Pos) /*!< CMSDK_LCD_IER REG DONIE(DISP ON INTR EN): CMSDK_LCD_IER_DONIE Mask */ + +#define CMSDK_LCD_IER_DOFFIE_Pos 0 +#define CMSDK_LCD_IER_DOFFIE_Msk (0x01ul << CMSDK_LCD_IER_DOFFIE_Pos) /*!< CMSDK_LCD_IER REG DOFFIE(DISP OFF INTR EN): CMSDK_LCD_IER_DOFFIE Mask */ + +#define CMSDK_LCD_ISR_DOFFIF_Pos 0 +#define CMSDK_LCD_ISR_DOFFIF_Msk (0x01ul << CMSDK_LCD_ISR_DOFFIF_Pos) /*!< CMSDK_LCD_ISR REG DOFFIF(DISP OFF INTR FLAG): CMSDK_LCD_ISR_DOFFIF Mask */ + +#define CMSDK_LCD_ISR_DONIF_Pos 1 +#define CMSDK_LCD_ISR_DONIF_Msk (0x01ul << CMSDK_LCD_ISR_DONIF_Pos) /*!< CMSDK_LCD_ISR REG DONIF(DISP ON INTR FLAG): CMSDK_LCD_ISR_DONIF Mask */ + +#define CMSDK_LCD_DATA_Pos 0 +#define CMSDK_LCD_DATA_Msk (0xFFFFul << CMSDK_LCD_DATA_Pos) /*!< CMSDK_LCD_DATAx Buffer Register: CMSDK_LCD_DATA Mask */ + +#define CMSDK_LCD_COM_EN0_Pos 0 +#define CMSDK_LCD_COM_EN0_Msk (0x01ul << CMSDK_LCD_COM_EN0_Pos) /*!< CMSDK_LCD_COM_EN REG COM_EN0: CMSDK_LCD_COM_EN0 Mask */ + +#define CMSDK_LCD_COM_EN1_Pos 1 +#define CMSDK_LCD_COM_EN1_Msk (0x01ul << CMSDK_LCD_COM_EN1_Pos) /*!< CMSDK_LCD_COM_EN REG COM_EN1: CMSDK_LCD_COM_EN1 Mask */ + +#define CMSDK_LCD_COM_EN2_Pos 2 +#define CMSDK_LCD_COM_EN2_Msk (0x01ul << CMSDK_LCD_COM_EN2_Pos) /*!< CMSDK_LCD_COM_EN REG COM_EN2: CMSDK_LCD_COM_EN2 Mask */ + +#define CMSDK_LCD_COM_EN3_Pos 3 +#define CMSDK_LCD_COM_EN3_Msk (0x01ul << CMSDK_LCD_COM_EN3_Pos) /*!< CMSDK_LCD_COM_EN REG COM_EN3: CMSDK_LCD_COM_EN3 Mask */ + +#define CMSDK_LCD_SEG_EN0_Pos 0 +#define CMSDK_LCD_SEG_EN0_Msk (0x01ul << CMSDK_LCD_SEG_EN0_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN0: CMSDK_LCD_SEG_EN0 Mask */ + +#define CMSDK_LCD_SEG_EN1_Pos 1 +#define CMSDK_LCD_SEG_EN1_Msk (0x01ul << CMSDK_LCD_SEG_EN1_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN1: CMSDK_LCD_SEG_EN1 Mask */ + +#define CMSDK_LCD_SEG_EN2_Pos 2 +#define CMSDK_LCD_SEG_EN2_Msk (0x01ul << CMSDK_LCD_SEG_EN2_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN2: CMSDK_LCD_SEG_EN2 Mask */ + +#define CMSDK_LCD_SEG_EN3_Pos 3 +#define CMSDK_LCD_SEG_EN3_Msk (0x01ul << CMSDK_LCD_SEG_EN3_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN3: CMSDK_LCD_SEG_EN3 Mask */ + +#define CMSDK_LCD_SEG_EN4_Pos 4 +#define CMSDK_LCD_SEG_EN4_Msk (0x01ul << CMSDK_LCD_SEG_EN4_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN4: CMSDK_LCD_SEG_EN4 Mask */ + +#define CMSDK_LCD_SEG_EN5_Pos 5 +#define CMSDK_LCD_SEG_EN5_Msk (0x01ul << CMSDK_LCD_SEG_EN5_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN5: CMSDK_LCD_SEG_EN5 Mask */ + +#define CMSDK_LCD_SEG_EN6_Pos 6 +#define CMSDK_LCD_SEG_EN6_Msk (0x01ul << CMSDK_LCD_SEG_EN6_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN6: CMSDK_LCD_SEG_EN6 Mask */ + +#define CMSDK_LCD_SEG_EN7_Pos 7 +#define CMSDK_LCD_SEG_EN7_Msk (0x01ul << CMSDK_LCD_SEG_EN7_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN7: CMSDK_LCD_SEG_EN7 Mask */ + +#define CMSDK_LCD_SEG_EN8_Pos 8 +#define CMSDK_LCD_SEG_EN8_Msk (0x01ul << CMSDK_LCD_SEG_EN8_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN8: CMSDK_LCD_SEG_EN8 Mask */ + +#define CMSDK_LCD_SEG_EN9_Pos 9 +#define CMSDK_LCD_SEG_EN9_Msk (0x01ul << CMSDK_LCD_SEG_EN9_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN9: CMSDK_LCD_SEG_EN9 Mask */ + +#define CMSDK_LCD_SEG_EN10_Pos 10 +#define CMSDK_LCD_SEG_EN10_Msk (0x01ul << CMSDK_LCD_SEG_EN10_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN10: CMSDK_LCD_SEG_EN10 Mask */ + +#define CMSDK_LCD_SEG_EN11_Pos 11 +#define CMSDK_LCD_SEG_EN11_Msk (0x01ul << CMSDK_LCD_SEG_EN11_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN11: CMSDK_LCD_SEG_EN11 Mask */ + +#define CMSDK_LCD_SEG_EN12_Pos 12 +#define CMSDK_LCD_SEG_EN12_Msk (0x01ul << CMSDK_LCD_SEG_EN12_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN12: CMSDK_LCD_SEG_EN12 Mask */ + +#define CMSDK_LCD_SEG_EN13_Pos 13 +#define CMSDK_LCD_SEG_EN13_Msk (0x01ul << CMSDK_LCD_SEG_EN13_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN13: CMSDK_LCD_SEG_EN13 Mask */ + +#define CMSDK_LCD_SEG_EN14_Pos 14 +#define CMSDK_LCD_SEG_EN14_Msk (0x01ul << CMSDK_LCD_SEG_EN14_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN14: CMSDK_LCD_SEG_EN14 Mask */ + +#define CMSDK_LCD_SEG_EN15_Pos 15 +#define CMSDK_LCD_SEG_EN15_Msk (0x01ul << CMSDK_LCD_SEG_EN15_Pos) /*!< CMSDK_LCD_SEG_EN REG SEG_EN15: CMSDK_LCD_SEG_EN15 Mask */ + +/*@}*/ /* end of group CMSDK_LCD */ + +/*------------ ADC Controller (ADC) --------------------------------------*/ +/** @addtogroup CMSDK_ADC + @{ +*/ +typedef struct +{ + __IO uint32_t ADC_CONFG; /*!< Offset: 0x000 ADC Controller ADC Configuration Register (R/W) */ + __IO uint32_t ADC_CTRL; /*!< Offset: 0x004 ADC Controller ADC Control Register (R/W) */ + __IO uint32_t ADC_IER; /*!< Offset: 0x008 ADC Controller ADC Interrupt Enable Register (R/W) */ + union { + __I uint32_t ADC_ISR; /*!< Offset: 0x00C ADC Controller ADC Interrupt Status Register (R/) */ + __O uint32_t ADC_INT_CLR; /*!< Offset: 0x00C ADC Controller ADC Interrupt Clear Register (/W) */ + }; + __I uint32_t ADC_SR; /*!< Offset: 0x010 ADC Controller ADC Status Register (R) */ + __IO uint32_t ADC_CLK_DIV; /*!< Offset: 0x014 ADC Controller ADC Clock Divider Register (R/W) */ + __IO uint32_t ADC_SAMP_TIME; /*!< Offset: 0x018 ADC Controller ADC Sampling Time register (R/W) */ + __IO uint32_t ADC_DATA; /*!< Offset: 0x01C ADC Controller ADC Data Register (R/W) */ + __IO uint32_t ADC_CH_SEL; /*!< Offset: 0x020 ADC Controller ADC Channel Selection Register (R/W) */ + __IO uint32_t ADC_EOC_CONFG; /*!< Offset: 0x024 ADC Controller ADC EOC_Configuration_Register (R/W) */ + } CMSDK_ADC_TypeDef; + +#define CMSDK_ADC_COV_MODE_Pos 0 +#define CMSDK_ADC_COV_MODE_Msk (0x01ul << CMSDK_ADC_COV_MODE_Pos) /*!< CMSDK_ADC_CONFIG REG ADC conversion mode: ADC conversion mode Mask */ + +#define CMSDK_ADC_OVERRUN_MODE_Pos 1 +#define CMSDK_ADC_OVERRUN_MODE_Msk (0x01ul << CMSDK_ADC_OVERRUN_MODE_Pos) /*!< CMSDK_ADC_CONFIG REG ADC overrun mode enable: ADC overrun mode enable Mask */ + +#define CMSDK_WAIT_MODE_EN_Pos 2 +#define CMSDK_WAIT_MODE_EN_Msk (0x01ul << CMSDK_WAIT_MODE_EN_Pos) /*!< CMSDK_ADC_CONFIG REG ADC WAIT mode enable: ADC WAIT mode enable Mask */ + +#define CMSDK_ADC_EN_Pos 0 +#define CMSDK_ADC_EN_Msk (0x01ul << CMSDK_ADC_EN_Pos) /*!< CMSDK_ADC_CTRL REG ADC enable: ADC enable Mask */ + +#define CMSDK_ADC_START_Pos 8 +#define CMSDK_ADC_START_Msk (0x01ul << CMSDK_ADC_START_Pos) /*!< CMSDK_ADC_CTRL REG ADC start: ADC start Mask */ + +#define CMSDK_ADC_EOC_INT_EN_Pos 0 +#define CMSDK_ADC_EOC_INT_EN_Msk (0x01ul << CMSDK_ADC_EOC_INT_EN_Pos) /*!< CMSDK_ADC_INT_EN REG ADC End of Conversion Interrupt enable bit: ADC End of Conversion Interrupt enable bit Mask */ + +#define CMSDK_ADC_OVERRUN_INT_EN_Pos 1 +#define CMSDK_ADC_OVERRUN_INT_EN_Msk (0x01ul << CMSDK_ADC_EOC_INT_EN_Pos) /*!< CMSDK_ADC_INT_EN REG ADC Overrun interrupt enable bit: ADC Overrun interrupt enable bit Mask */ + +#define CMSDK_ADC_EOC_INT_STS_Pos 0 +#define CMSDK_ADC_EOC_INT_STS_Msk (0x01ul << CMSDK_ADC_EOC_INT_STS_Pos) /*!< CMSDK_ADC_INT_STS REG ADC_interrupt at the end of EOC: ADC_interrupt at the end of EOC Mask */ + +#define CMSDK_ADC_OVERRUN_INT_STS_Pos 1 +#define CMSDK_ADC_OVERRUN_INT_STS_Msk (0x01ul << CMSDK_ADC_EOC_INT_EN_Pos) /*!< CMSDK_ADC_INT_STS REG ADC overrun interrupt: ADC overrun interrupt Mask */ + +#define CMSDK_ADC_EOC_FLAG_Pos 0 +#define CMSDK_ADC_EOC_FLAG_Msk (0x01ul << CMSDK_ADC_EOC_FLAG_Pos) /*!< CMSDK_ADC_STS REG ADC EOC FLAG Status: ADC EOC FLAG Status Mask */ + +#define CMSDK_ADC_STATUS_Pos 1 +#define CMSDK_ADC_STATUS_Msk (0x01ul << CMSDK_ADC_EOC_FLAG_Pos) /*!< CMSDK_ADC_STS REG ADC Status(idle&busy): ADC Status Mask */ + +#define CMSDK_ADC_CLK_DIV_Pos 0 +#define CMSDK_ADC_CLK_DIV_Msk (0x07ul << CMSDK_ADC_EOC_FLAG_Pos) /*!< CMSDK_ADC_CLK_DIV REG ADC Clock Divider: ADC Clock Divider Mask */ + +#define CMSDK_ADC_SAMPLING_TIME_Pos 0 +#define CMSDK_ADC_SAMPLING_TIME_Msk (0x03ul << CMSDK_ADC_SAMPLING_TIME_Pos) /*!< CMSDK_ADC_CLK_SAMP_TIME REG ADC_SAMPLING TIME: ADC_SAMPLING TIME Mask */ + +#define CMSDK_ADC_DATA_Pos 0 +#define CMSDK_ADC_DATA_Msk (0x0FFFul << CMSDK_ADC_DATA_Pos) /*!< CMSDK_ADC_DATA REG ADC_SAMPLING TIME: ADC_ADC_DATA Mask */ + +#define CMSDK_ADC_CHANNEL_SEL_Pos 0 +#define CMSDK_ADC_CHANNEL_SEL_Msk (0x07ul << CMSDK_ADC_DATA_Pos) /*!< CMSDK_CHANNEL_SEL REG ADC_CHANNEL SEL: ADC_CHANNEL SEL Mask */ + +#define CMSDK_ADC_CONVERSION_INC_EOC_Pos 0 +#define CMSDK_ADC_CONVERSION_INC_EOC_Msk (0x01ul << CMSDK_ADC_CONVERSION_INC_EOC_Pos) /*!< CMSDK_ADC_EOC_CONFIG REG start next conversion with/without receiving EOC: ADC start next conversion with/without receiving EOC Mask */ + +/*@}*/ /* end of group CMSDK_ADC */ + +/*------------ Analog Control (ANAC) --------------------------------------*/ +/** @addtogroup CMSDK_ANAC + @{ +*/ +typedef struct +{ + __IO uint32_t COMP0_CTRL; /*!< Offset: 0x000 Analog Comparator 0 Control Register (R/W) */ + __IO uint32_t COMP1_CTRL; /*!< Offset: 0x004 Analog Comparator 1 Control Register (R/W) */ + __IO uint32_t PGA_CTRL; /*!< Offset: 0x008 Analog PGA Control Register (R/W) */ + __IO uint32_t CHARGE_CTRL; /*!< Offset: 0x00C Analog Charge Control Register (R) */ + __IO uint32_t PMU_CTRL; /*!< Offset: 0x010 Analog PMU Control Register (R/W) */ + __IO uint32_t BOOST_CTRL; /*!< Offset: 0x014 Analog Boost Control register (R/W) */ + __IO uint32_t ANA_BIST; /*!< Offset: 0x018 Analog BIST Select Register (R/W) */ + } CMSDK_ANAC_TypeDef; + +#define CMSDK_ANAC_BOOST_SELV_SEL_Pos 8 +#define CMSDK_ANAC_BOOST_SELV_SEL_Msk (0x0002ul << CMSDK_ANAC_BOOST_SELV_SEL_Pos) /*!< */ + +#define CMSDK_ANAC_BOOST_PRES_Pos 16 +#define CMSDK_ANAC_BOOST_PRES_Msk (0x00ul << CMSDK_ANAC_BOOST_PRES_Pos) /*!< CMSDK_ANAC BOOST_CTRL REG : BOOST_PRES Mask */ + +#define CMSDK_ANAC_BOOST_DUTY_Pos 19 +#define CMSDK_ANAC_BOOST_DUTY_Msk (0x00ul << CMSDK_ANAC_BOOST_DUTY_Pos) /*!< CMSDK_ANAC BOOST_CTRL REG : BOOST_DUTY Mask */ + +#define CMSDK_ANAC_BOOST_DUTY_SEL_Pos 20 +#define CMSDK_ANAC_BOOST_DUTY_SEL_Msk (0x01ul << CMSDK_ANAC_BOOST_DUTY_SEL_Pos) /*!< CMSDK_ANAC BOOST_CTRL REG : BOOST_DUTY_SEL Mask */ + +#define CMSDK_ANAC_BOOST_EXMODE_EN_Pos 2 +#define CMSDK_ANAC_BOOST_EXMODE_EN_Msk (0x01ul << CMSDK_ANAC_BOOST_EXMODE_EN_Pos) /*!< CMSDK_ANAC BOOST_CTRL REG : BOOST_EXMODE_EN Mask */ + +#define CMSDK_ANAC_BOOST_STANDBY_EN_Pos 1 +#define CMSDK_ANAC_BOOST_STANDBY_EN_Msk (0x01ul << CMSDK_ANAC_BOOST_STANDBY_EN_Pos) /*!< CMSDK_ANAC BOOST_CTRL REG : BOOST_STANDBY_EN Mask */ + +#define CMSDK_ANAC_BOOST_EN_Pos 0 +#define CMSDK_ANAC_BOOST_EN_Msk (0x01ul << CMSDK_ANAC_BOOST_EN_Pos) /*!< CMSDK_ANAC BOOST_CTRL REG : BOOST_EN Mask */ +/*@}*/ /* end of group CMSDK_ANAC */ + +/*------------ WAVEFORM GENERATOR (WAVE_GEN) --------------------------------------*/ +/** @addtogroup CMSDK_WAVE_GEN + @{ +*/ +typedef struct +{ + __IO uint32_t WAVE_GEN_DRV_CONFIG_REG; + __IO uint32_t WAVE_GEN_DRV_CTRL_REG; + __O uint32_t WAVE_GEN_DRV_REST_T_REG; + __O uint32_t WAVE_GEN_DRV_SILENT_T_REG; + __O uint32_t WAVE_GEN_DRV_HLF_WAVE_PRD_REG; + __O uint32_t WAVE_GEN_DRV_NEG_HLF_WAVE_PRD_REG; + __O uint32_t WAVE_GEN_DRV_CLK_FREQ_REG; + __O uint32_t WAVE_GEN_DRV_IN_WAVE_ADDR_REG; + __O uint32_t WAVE_GEN_DRV_IN_WAVE_REG; + __O uint32_t WAVE_GEN_DRV_ALT_LIM_REG; + __O uint32_t WAVE_GEN_DRV_ALT_SILENT_LIM_REG; + __O uint32_t WAVE_GEN_DRV_DELAY_LIM_REG; + __O uint32_t WAVE_GEN_DRV_NEG_SCALE_REG; + __O uint32_t WAVE_GEN_DRV_NEG_OFFSET_REG; + __IO uint32_t WAVE_GEN_DRV_INT_REG; + __O uint32_t WAVE_GEN_DRV_ISEL_REG; + __O uint32_t WAVE_GEN_DRV_SW_CONFIG_REG; + + } CMSDK_WAVE_GEN_TypeDef; + +#define CMSDK_WAVE_GEN_DRV_INT_EN_Pos 0 +#define CMSDK_WAVE_GEN_DRV_INT_EN_Msk (0x01ul << CMSDK_WAVE_GEN_DRV_INT_EN_Pos) /*!< WAVE_GEN_DRV_INT_REG Enable interrupt Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Pos 1 +#define CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Msk (0x01ul << CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Pos) /*!< WAVE_GEN_DRV_INT_REG Clear 1st ADDRESS interrupt Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_CLR_Pos 2 +#define CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_CLR_Msk (0x01ul << CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_CLR_Pos) /*!< WAVE_GEN_DRV_INT_REG Clear 2nd ADDRESS interrupt Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_STS_Pos 9 +#define CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_STS_Msk (0x01ul << CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_STS_Pos) /*!< WAVE_GEN_DRV_INT_REG Status 1st ADDRESS interrupt Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_STS_Pos 10 +#define CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_STS_Msk (0x01ul << CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_STS_Pos) /*!< WAVE_GEN_DRV_INT_REG Status 2nd ADDRESS interrupt Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Pos 8 +#define CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Msk (0xFFul << CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Pos) /*!< WAVE_GEN_DRV_INT_REG 1st ADDRESS Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Pos 16 +#define CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Msk (0xFFul << CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Pos) /*!< WAVE_GEN_DRV_INT_REG 2nd ADDRESS Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Pos 16 +#define CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Msk (0xFFul << CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Pos) /*!< WAVE_GEN_DRV_INT_REG Reporting 1st ADDRESS Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_READ_SECOND_ADDR_Pos 24 +#define CMSDK_WAVE_GEN_DRV_INT_READ_SECOND_ADDR_Msk (0xFFul << CMSDK_WAVE_GEN_DRV_INT_READ_SECOND_ADDR_Pos) /*!< WAVE_GEN_DRV_INT_REG Reporting 2nd ADDRESS Mask */ + +#define CMSDK_WAVE_GEN_DRV_INT_READ_DRIVER_NUM_Pos 0 +#define CMSDK_WAVE_GEN_DRV_INT_READ_DRIVER_NUM_Msk (0xFFul << CMSDK_WAVE_GEN_DRV_INT_READ_DRIVER_NUM_Pos) /*!< WAVE_GEN_DRV_INT_REG Wavegen driver number Mask */ +/*@}*/ /* end of group CMSDK_WAVE_GEN */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/*@}*/ /* end of group CMSDK_Peripherals */ + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/** @addtogroup CMSDK_MemoryMap CMSDK Memory Mapping + @{ +*/ + +/* Peripheral and SRAM base address */ +#define CMSDK_CODE_BASE (0x00000000UL) /*!< (CODE ) Base Address based on remap*/ +#define CMSDK_MTP_BASE (0x10000000UL) /*!< (MTP ) Base Address */ +#define CMSDK_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define CMSDK_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ + +#define CMSDK_RAM_BASE (0x20000000UL) +#define CMSDK_APB_BASE (0x40000000UL) +#define CMSDK_AHB_BASE (0x40020000UL) + +/* APB peripherals */ +#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x0000UL) +#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x1000UL) +#define CMSDK_SPI0_BASE (CMSDK_APB_BASE + 0x2000UL) +#define CMSDK_SPI1_BASE (CMSDK_APB_BASE + 0x3000UL) +#define CMSDK_I2C0_BASE (CMSDK_APB_BASE + 0x4000UL) +#define CMSDK_I2C1_BASE (CMSDK_APB_BASE + 0x5000UL) +#define CMSDK_WDT_BASE (CMSDK_APB_BASE + 0x6000UL) +#define CMSDK_PWM_BASE (CMSDK_APB_BASE + 0x7000UL) +#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x8000UL) +#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x9000UL) +#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0xA000UL) +#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) +#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) +#define CMSDK_LCD_BASE (CMSDK_APB_BASE + 0xB000UL) +#define CMSDK_WAVE_GEN_BASE (CMSDK_APB_BASE + 0xC000UL) +#define CMSDK_ADC_BASE (CMSDK_APB_BASE + 0xD000UL) +#define CMSDK_ANAC_BASE (CMSDK_APB_BASE + 0xE000UL) +#define CMSDK_RTC_BASE (CMSDK_APB_BASE + 0xF000UL) + + + + +/* AHB peripherals */ +#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0x0000UL) +#define CMSDK_GPIO_BASE (CMSDK_AHB_BASE + 0x1000UL) +#define CMSDK_EXTI_BASE (CMSDK_AHB_BASE + 0x2000UL) +#define CMSDK_MTPREG_BASE (CMSDK_AHB_BASE + 0x3000UL) +/*@}*/ /* end of group CMSDK_MemoryMap */ + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/** @addtogroup CMSDK_PeripheralDecl CMSDK Peripheral Declaration + @{ +*/ + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) +#define CMSDK_SPI0 ((CMSDK_SPI_TypeDef *) CMSDK_SPI0_BASE ) +#define CMSDK_SPI1 ((CMSDK_SPI_TypeDef *) CMSDK_SPI1_BASE ) +#define CMSDK_I2C0 ((CMSDK_I2C_TypeDef *) CMSDK_I2C0_BASE ) +#define CMSDK_I2C1 ((CMSDK_I2C_TypeDef *) CMSDK_I2C1_BASE ) +#define CMSDK_WATCHDOG ((CMSDK_WDT_TypeDef *) CMSDK_WDT_BASE ) +#define CMSDK_PWM ((CMSDK_PWM_TypeDef *) CMSDK_PWM_BASE ) +#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE ) +#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE ) +#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_TypeDef *) CMSDK_DUALTIMER_1_BASE ) +#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_TypeDef *) CMSDK_DUALTIMER_2_BASE ) +#define CMSDK_LCD ((CMSDK_LCD_TypeDef *) CMSDK_LCD_BASE ) +//#define CMSDK_WAVE_GEN ((CMSDK_WAVE_GEN_TypeDef *) CMSDK_WAVE_GEN_BASE ) +#define WAVE_GEN_DRVA_BLK0 ((CMSDK_WAVE_GEN_TypeDef *) CMSDK_WAVE_GEN_BASE ) +#define WAVE_GEN_DRVA_BLK1 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C044UL ) +#define WAVE_GEN_DRVA_BLK2 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C088UL ) +#define WAVE_GEN_DRVA_BLK3 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C0CCUL ) + +#define WAVE_GEN_DRVB_BLK4 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C110UL ) + +#define WAVE_GEN_DRVC_BLK5 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C154UL ) +#define WAVE_GEN_DRVC_BLK6 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C198UL ) +#define WAVE_GEN_DRVC_BLK7 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C1DCUL ) +#define WAVE_GEN_DRVC_BLK8 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C220UL ) +#define WAVE_GEN_DRVC_BLK9 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C264UL ) +#define WAVE_GEN_DRVC_BLK10 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C2A8UL ) +#define WAVE_GEN_DRVC_BLK11 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C2ECUL ) +#define WAVE_GEN_DRVC_BLK12 ((CMSDK_WAVE_GEN_TypeDef *) 0x4000C330UL ) + +#define CMSDK_ADC ((CMSDK_ADC_TypeDef *) CMSDK_ADC_BASE ) +#define CMSDK_ANAC ((CMSDK_ANAC_TypeDef *) CMSDK_ANAC_BASE ) +#define CMSDK_RTC ((CMSDK_RTC_TypeDef *) CMSDK_RTC_BASE ) + +#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) +#define CMSDK_GPIO ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO_BASE ) +#define CMSDK_EXTI ((CMSDK_EXTI_TypeDef *) CMSDK_EXTI_BASE ) +#define CMSDK_MTPREG ((CMSDK_MTPREG_TypeDef *) CMSDK_MTPREG_BASE ) +/*@}*/ /* end of group CMSDK_PeripheralDecl */ + +/*@}*/ /* end of group CMSDK_Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* CMSDK_H */ diff --git a/CORE/INCLUDE/core_cm0.h b/CORE/INCLUDE/core_cm0.h new file mode 100644 index 0000000..ab31de0 --- /dev/null +++ b/CORE/INCLUDE/core_cm0.h @@ -0,0 +1,682 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/CORE/INCLUDE/core_cm0plus.h b/CORE/INCLUDE/core_cm0plus.h new file mode 100644 index 0000000..5cea74e --- /dev/null +++ b/CORE/INCLUDE/core_cm0plus.h @@ -0,0 +1,793 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/CORE/INCLUDE/core_cmFunc.h b/CORE/INCLUDE/core_cmFunc.h new file mode 100644 index 0000000..0a18faf --- /dev/null +++ b/CORE/INCLUDE/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/CORE/INCLUDE/core_cmInstr.h b/CORE/INCLUDE/core_cmInstr.h new file mode 100644 index 0000000..ab3a010 --- /dev/null +++ b/CORE/INCLUDE/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/CORE/INCLUDE/system_CMSDK_CM0.h b/CORE/INCLUDE/system_CMSDK_CM0.h new file mode 100644 index 0000000..9e74cf3 --- /dev/null +++ b/CORE/INCLUDE/system_CMSDK_CM0.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file system_CMSDK_CM0.h + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File for + * Device + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef SYSTEM_CMSDK_CM0_H +#define SYSTEM_CMSDK_CM0_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_CMSDK_CM0_H */ diff --git a/CORE/system_CMSDK_CM0.c b/CORE/system_CMSDK_CM0.c new file mode 100644 index 0000000..9056bf4 --- /dev/null +++ b/CORE/system_CMSDK_CM0.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_CMSDK_CM0.c + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for + * Device CMSDK + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include +#include "CMSDK_CM0.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +#define XTAL (100000000UL) /* Oscillator frequency */ + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemFrequency = XTAL; /*!< System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = XTAL; /*!< Processor Clock Frequency */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + SystemCoreClock = XTAL; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + SystemCoreClock = XTAL; +} diff --git a/ENS001_BASIC_PRJ.uvguix.26971 b/ENS001_BASIC_PRJ.uvguix.26971 new file mode 100644 index 0000000..ef97a00 --- /dev/null +++ b/ENS001_BASIC_PRJ.uvguix.26971 @@ -0,0 +1,1968 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ENS001_BASIC_PRJ + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + / + + + 0 + JL2CM3 + -U941000024 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC2000 -FN1 -FF0NNC_ENS1_0x000_0x5F00 -FS010000000 -FL05F00 + + + 0 + UL2CM3 + -U-O14 -O14 -S0 -C0 -P00 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC2000 -FN1 -FF0NNC_ENS1 -FS010000000 -FL06F00 + + + + + 0 + 0 + 39 + 1 +
0
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+ 0 + 0 + 0 + 0 + 0 + 1 + C:\Users\admin\Desktop\---瀹搞儰缍旀稉?--\0閵嗕線鍣哥憰浣稿敶鐎圭櫢绱癊NS妞瑰崬濮╁鈧崣?缂佸牏澧20231124\1閵嗕笒NS_GPIO_DEMO\FWLIB\source\ENS1_UART.c + + \\ENS001_BASIC_PRJ\FWLIB/source/ENS1_UART.c\283 + + + 2 + 0 + 36 + 1 +
268444878
+ 0 + 0 + 0 + 0 + 0 + 1 + C:\Users\admin\Desktop\---瀹搞儰缍旀稉?--\0閵嗕線鍣哥憰浣稿敶鐎圭櫢绱癊NS妞瑰崬濮╁鈧崣?缂佸牏澧20231124\1閵嗕笒NS_GPIO_DEMO\USER\mian.c + + \\ENS001_BASIC_PRJ\USER/mian.c\36 + + + + + 0 + 1 + unit_t + + + 1 + 1 + isel_t,0x0A + + + 2 + 1 + wavePara_type + + + + + 0 + 2 + FT_CURRENT_SAVE[4] + + + + + 1 + 0 + 0X10006F00 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + USER + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\USER\mian.c + mian.c + 0 + 0 + + + + + FWLIB + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 1 + 0 + 0 + .\FWLIB\source\ENS1_UART.c + ENS1_UART.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + .\FWLIB\source\ENS1_GPIO.c + ENS1_GPIO.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + .\FWLIB\source\ENS1_MTP.c + ENS1_MTP.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + .\FWLIB\source\ENS1_CLOCK.c + ENS1_CLOCK.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + .\FWLIB\source\retarget.c + retarget.c + 0 + 0 + + + 2 + 7 + 1 + 1 + 0 + 0 + .\FWLIB\source\ENS1_TIMER.c + ENS1_TIMER.c + 0 + 0 + + + + + HARDWARE + 0 + 0 + 0 + 0 + + + + SYSTEM + 0 + 0 + 0 + 0 + + + + CORE + 1 + 0 + 0 + 0 + + 5 + 8 + 1 + 0 + 0 + 0 + .\CORE\system_CMSDK_CM0.c + system_CMSDK_CM0.c + 0 + 0 + + + 5 + 9 + 2 + 0 + 0 + 0 + .\CORE\ARM\startup_CMSDK_CM0.s + startup_CMSDK_CM0.s + 0 + 0 + + + + diff --git a/ENS001_BASIC_PRJ.uvprojx b/ENS001_BASIC_PRJ.uvprojx new file mode 100644 index 0000000..e37a901 --- /dev/null +++ b/ENS001_BASIC_PRJ.uvprojx @@ -0,0 +1,470 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ENS001_BASIC_PRJ + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARM_Compiler_5.06u7 + 5060750::V5.06 update 6 (build 750)::.\ARM_Compiler_5.06u7 + 8 + + + ARMCM0 + ARM + ARM.Cortex_DFP.1.1.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + $$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + ENS001_BASIC_PRJ + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + $K\ARM\ARMCC\bin\fromelf.exe --bin --output=Bin\@L.bin !L + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10000000 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + .\CORE\INCLUDE;.\USER;.\FWLIB\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + USER + + + mian.c + 1 + .\USER\mian.c + + + + + FWLIB + + + ENS1_UART.c + 1 + .\FWLIB\source\ENS1_UART.c + + + ENS1_GPIO.c + 1 + .\FWLIB\source\ENS1_GPIO.c + + + ENS1_MTP.c + 1 + .\FWLIB\source\ENS1_MTP.c + + + ENS1_CLOCK.c + 1 + .\FWLIB\source\ENS1_CLOCK.c + + + retarget.c + 1 + .\FWLIB\source\retarget.c + + + ENS1_TIMER.c + 1 + .\FWLIB\source\ENS1_TIMER.c + + + + + HARDWARE + + + SYSTEM + + + CORE + + + system_CMSDK_CM0.c + 1 + .\CORE\system_CMSDK_CM0.c + + + startup_CMSDK_CM0.s + 2 + .\CORE\ARM\startup_CMSDK_CM0.s + + + + + + + + + + + + + + + + + ENS001_BASIC_PRJ + 1 + + + + + diff --git a/EventRecorderStub.scvd b/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/FWLIB/include/ENS1_ADC.h b/FWLIB/include/ENS1_ADC.h new file mode 100644 index 0000000..61992cd --- /dev/null +++ b/FWLIB/include/ENS1_ADC.h @@ -0,0 +1,114 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_ADC.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: +1.V1.0 +Date: +Author: +Modification: 初版 +*/ + +#ifndef ENS1_ADC_H +#define ENS1_ADC_H +#include "my_header.h" + +/* +GPIO21 --- ADC 1 +GPIO22 --- ADC 2 +GPIO23 --- ADC 3 + +*/ +extern uint16_t save_data; +extern uint8_t ADC_UART_BYTE_LOW ; +extern uint8_t ADC_UART_BYTE_HIGH ; +typedef enum { ENS1_PGA_TO_ADC = 0 ,ENS1_ADC_CHANNEL1 = 1,ENS1_ADC_CHANNEL2 = 2,ENS1_ADC_CHANNEL3 = 3}ENS_ADC_SEL; +//typedef enum { SINGLE_ADC_MODE = 0, CONTINUOUS_ADC_MODE = 1}ENS_ADC_COV_MODE; +//typedef enum { NOOVERRUN_ADC_MODE = 0, OVERRUN_ADC_MODE = 1}ENS_ADC_OVERRUN_MODE; +//typedef enum { NOWAIT_ADC_MODE = 0, WAIT_ADC_MODE = 1}WAIT_MODE; +typedef enum { NCOV_WITHOUT_RCV_EOC = 0 , COV_RCV_EOC = 1}ENS_ADC_COV_INC_EOC; + +/*模式分类： MODE_SEL + 单次采集 + 连续采集 + OVERRUN + 关闭OVERRUN + 等待模式开启 + 等待模式关闭 +*/ +#define SINGLE_ADC_MODE 0 +#define CONTINUOUS_ADC_MODE (1) +#define OVERRUN_ADC_MODE (1<<1) +#define WAIT_ADC_MODE (1<<2) + +/*中断模式选择 INT_MODE_SEL */ +#define DISABLE_INT (0) +#define ENABLE_EOC_INT (1) +#define ENABLE_OVERRUN_INT (1<<1) + +/* +ADC读取状态 +*/ +#define ADC_READ_DATA_IS_WAITING 0x00 +#define ADC_READ_DATA_IS_READY 0x01 + +/* +SIMLING_TIME +*/ +#define ADC_SampleTime_2ADC_Clk ((uint8_t)0x00) +#define ADC_SampleTime_3ADC_Clk ((uint8_t)0x01) +#define ADC_SampleTime_4ADC_Clk ((uint8_t)0x02) +#define ADC_SampleTime_5ADC_Clk ((uint8_t)0x03) + + +/* + +*/ +#define ADC_CLK_base2div ((uint8_t)0x00) +#define ADC_CLK_base4div ((uint8_t)0x01) +#define ADC_CLK_base6div ((uint8_t)0x02) +#define ADC_CLK_base8div ((uint8_t)0x03) +#define ADC_CLK_base10div ((uint8_t)0x04) +#define ADC_CLK_base12div ((uint8_t)0x05) +#define ADC_CLK_base16div ((uint8_t)0x06) +#define ADC_CLK_base32div ((uint8_t)0x07) + + +/* + +*/ +#define single_mode_without_overrun_without_wait 0 +#define single_mode_without_overrun_with_wait 4 +#define single_mode_with_overrun_without_wait 2 +#define single_mode_with_overrun_with_wait 6 +#define continious_mode_without_overrun_without_wait 1 +#define continious_mode_with_overrun_without_wait 3 +#define Continious_mode_without_overun_with_wait 5 +#define continious_mode_with_overrun_with_wait 7 + + + +/* +声明 ADC相关函数 +*/ +extern uint8_t ENS1_ADCCLKConfig(uint8_t ADC_CLK_div); +extern uint8_t ENS1_ADC_CONFIG(ENS_ADC_SEL channelx , + uint8_t MODE_SEL, + ENS_ADC_COV_INC_EOC EOC_CONFIG , + uint8_t SIMLING_TIME, + uint8_t INT_MODE_SEL); +extern uint8_t ENS1_ADC_START(ENS_ADC_SEL channelx); +extern uint8_t ENS1_ADC_STOP(ENS_ADC_SEL channelx); +extern uint16_t ADC_READ_DATA(void); + + + + + +#endif + diff --git a/FWLIB/include/ENS1_ANAC.h b/FWLIB/include/ENS1_ANAC.h new file mode 100644 index 0000000..67ff7dc --- /dev/null +++ b/FWLIB/include/ENS1_ANAC.h @@ -0,0 +1,176 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_ANAC.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#ifndef ENS1_ANAC_H +#define ENS1_ANAC_H + +#include +#include "CMSDK_CM0.h" +#include "my_header.h" +#include "ENS1_GPIO.h" +/*-------------------boost------------------------*/ +extern uint8_t Boost_Voltage_Sel(uint8_t VOLTAGE_XV); +#define VOLTAGE_11V 0x0 +#define VOLTAGE_15V 0x1 +#define VOLTAGE_26V 0x2 +#define VOLTAGE_45V 0x3 +#define VOLTAGE_55V 0x4 + + +/*-------------------比较器------------------------*/ +/* +比较器IO复用说明 + +GPIO12 -- COMP1_VIP0 +GPIO13 -- COMP1_VIP1 +GPIO14 -- COMP1_VIN0 +GPIO15 -- COMP1_VIN1 +GPIO21 -- COMP1_OUT + +GPIO8 -- COMP0_VIP0 +GPIO9 -- COMP0_VIP1 +GPIO10 -- COMP0_VIN0 +GPIO11 -- COMP0_VIN1 +GPIO20 -- COMP0_OUT +*/ + +#define COMP_VREF_VOLTAGE_0_3v (uint8_t)(0x0) +#define COMP_VREF_VOLTAGE_0_6v (uint8_t)(0x1) +#define COMP_VREF_VOLTAGE_0_9v (uint8_t)(0x2) +#define COMP_VREF_VOLTAGE_1_2v (uint8_t)(0x3) +#define COMP_VREF_VOLTAGE_1_5v (uint8_t)(0x4) +#define COMP_VREF_VOLTAGE_1_8v (uint8_t)(0x5) +#define COMP_VREF_VOLTAGE_2_1v (uint8_t)(0x6) +#define COMP_VREF_VOLTAGE_2_4v (uint8_t)(0x7) + +#define COMP_NEG_INPUT_VIN0 (uint8_t)(0x0) +#define COMP_NEG_INPUT_VIN1 (uint8_t)(0x1) +#define COMP_NEG_INPUT_VREF (uint8_t)(0x2) + +#define COMP_POS_INPUT_VIP0 (uint8_t)(0x1) +#define COMP_POS_INPUT_VIP1 (uint8_t)(0x2) + +typedef enum{COMP0=0, COMP1}COMP_NUM; +typedef struct COMPConfig +{ + COMP_NUM COMPARATOR_NUM; + uint8_t COMP_VREF_SEL; + uint8_t COMP_SIGSEL_NEGATIVE_INPUT_SEL; + uint8_t COMP_SIGSEL_POSITIVE_INPUT_SEL; +}COMP_ConfigStructure; + + +/*比较器的输出设置*/ +extern void CompInitSet(COMP_ConfigStructure* COMPCONFIG); + +/*读比较结果*/ +extern uint8_t Read_Comp_Output(COMP_NUM NUM); + +/*开启/关闭比较器*/ +extern void CompControl(COMP_NUM NUM ,FunctionalState Newstate); + + +/*-----------------------------PGA------------------------------*/ + +/* +PGA IO复用说明 +GPIO16 -- PGA_VIP0 //输入信号直连 +GPIO18 -- PGA_VIN0 //需要接入电阻 + +GPIO17 -- PGA_VIP1 //输入信号直连 +GPIO19 -- PGA_VIN1 //需要接入电阻 + +GPIO20 -- PGA_EXVCM + +GPIO4 -- PGA_OUT + +*/ + +//#define PGA_POSITIVE_INPUT_VBAT (uint8_t)(0x3) +//#define PGA_POSITIVE_INPUT_AVDD1P8 (uint8_t)(0x4) +//#define PGA_POSITIVE_INPUT_VLCD0 (uint8_t)(0x5) +//#define PGA_POSITIVE_INPUT_V_TEMP (uint8_t)(0x7) + + +//PGA放大倍数选择 ，对于反相模式： 1-8 倍， 同相模式2-9倍 +#define PGA_GAIN_1X_2X (uint8_t)(0x0) +#define PGA_GAIN_2X_3X (uint8_t)(0x1) +#define PGA_GAIN_3X_4X (uint8_t)(0x2) +#define PGA_GAIN_4X_5X (uint8_t)(0x3) +#define PGA_GAIN_5X_6X (uint8_t)(0x4) +#define PGA_GAIN_6X_7X (uint8_t)(0x5) +#define PGA_GAIN_7X_8X (uint8_t)(0x6) +#define PGA_GAIN_8X_9X (uint8_t)(0x7) + + +typedef enum{PGA_NEGATIVE_INPUT_PGA_VIN0 = 0,PGA_NEGATIVE_INPUT_PGA_VIN1, PGA_NEGATIVE_INPUT_INTERNAL_VCM,PGA_NEGATIVE_INPUT_EXTERNAL_VCM}PGA_NEG_SEL; +typedef enum{PGA_POSITIVE_INPUT_PGA_VIP0 = 0,PGA_POSITIVE_INPUT_PGA_VIP1=1,PGA_POSITIVE_INPUT_INTERNAL_VCM=2,PGA_POSITIVE_INPUT_VREF1_2V=6}PGA_POS_SEL; +typedef enum{PGA_TO_GPIO4=0 , PGA_TO_ADC=1}PGA_OUTPUT_SEL; +typedef struct PGAConfig +{ + PGA_NEG_SEL PGA_NEG_SELx ; + PGA_POS_SEL PGA_POS_SELx ; + uint8_t PGA_GAIN_SEL ; + PGA_OUTPUT_SEL PGA_OUT ; +}PGA_ConfigStructure; + +//初始化 +extern void PGAInitSet(PGA_ConfigStructure* PGACONFIG ); + +//PGA开关控制 +extern void PGAControl(FunctionalState Newstate); + + +/*--------------------------低电压与芯片过温检测-------------------------*/ +void PMU_TEMP150C_TRIGControl(FunctionalState Newstate); //过温检测功能开启与关闭 + +//返回温度是否超过150度的状态值 +int8_t TEMP_150C_TRIG_SIGNAL(void); + + + +#define LVD_4P2V (uint8_t)(0x0) +#define LVD_3P9V (uint8_t)(0x1) +#define LVD_3P6V (uint8_t)(0x2) +#define LVD_3P3V (uint8_t)(0x3) +#define LVD_3P0V (uint8_t)(0x4) +#define LVD_2P7V (uint8_t)(0x5) +#define LVD_2P4V (uint8_t)(0x6) +#define LVD_2P1V (uint8_t)(0x7) +//低电压告警 +//设置阈值电压 +void LVD_InitSet(uint8_t Threshold_voltage); +//打开或关闭此功能 +void PMU_LVD_Control(FunctionalState Newstate); +//读取低电压状态 +uint8_t Read_LVD_Signal(void); + +/*-------------------------带隙BUFFER启用或关闭-------------------------*/ +void PMU_BANDGAP_CONTROL(FunctionalState Newstate); + + + +#endif + + + + + + + + + + diff --git a/FWLIB/include/ENS1_BOOST.h b/FWLIB/include/ENS1_BOOST.h new file mode 100644 index 0000000..5b0563d --- /dev/null +++ b/FWLIB/include/ENS1_BOOST.h @@ -0,0 +1,21 @@ +#ifndef ENS1_BOOST_H +#define ENS1_BOOST_H + + +#include "my_header.h" + +extern uint8_t Boost_Voltage_Sel(uint8_t VOLTAGE_XV); + +#define VOLTAGE_11V 0x0 +#define VOLTAGE_15V 0x1 +#define VOLTAGE_26V 0x2 +#define VOLTAGE_45V 0x3 +#define VOLTAGE_55V 0x4 + + + + + + + +#endif \ No newline at end of file diff --git a/FWLIB/include/ENS1_CLOCK.h b/FWLIB/include/ENS1_CLOCK.h new file mode 100644 index 0000000..ed9f6af --- /dev/null +++ b/FWLIB/include/ENS1_CLOCK.h @@ -0,0 +1,92 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_CLOCK.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + 1 uint32_t ClockInitSet(Clock_ConfigStructure* CLOCKCONFIG); + 2 void ClockInit(void); + 3 uint8_t PCLK_Enable(uint8_t APB_CLKEN_POS); + 4 uint8_t PCLK_Disable(uint8_t APB_CLKEN_POS); +History: +1.V1.0 +Date: +Author: +Modification: 初版 +*/ + + +#ifndef ENS1_CLOCK_H +#define ENS1_CLOCK_H +#include "my_header.h" +#include "CMSDK_CM0.h" + +/* +时钟树结构 +低速（LSI RC / LSE OSC） --> LFCLK --> RTC / LCD +高速 (HSI RC / HSE ) --> SYSCLK --> 分频（AHB Prescaler）-----> SYSC / PMU / HCLK /SCLK /DCLK + | + | + | + ---->分频（APB Prescaler） --> PCLK +*/ +extern uint32_t APB_Clock_Freq; +//分频选择 +//APB +#define ENS1_APB_PCLK_DIV_1 0x0 +#define ENS1_APB_PCLK_DIV_2 0x4 +#define ENS1_APB_PCLK_DIV_4 0x5 +#define ENS1_APB_PCLK_DIV_8 0x6 +#define ENS1_APB_PCLK_DIV_16 0x7 +//AHB +#define ENS1_AHB_HCLK_DIV_1 0X0 +#define ENS1_AHB_HCLK_DIV_2 0X4 +#define ENS1_AHB_HCLK_DIV_4 0X5 +#define ENS1_AHB_HCLK_DIV_8 0X6 +#define ENS1_AHB_HCLK_DIV_16 0X7 + +typedef enum{HSI_4MHZ =0 , HSI_8MHZ=1 , HS_16MHZ=2 , HSI_32MHZ=3}HSI_FREQ_SEL; +typedef enum{MCO_HSI=0, MCO_HSE ,MCO_LSI,MCO_LSE}MCU_CLOCK_OUTPUT_SEL; //mcu时钟输出选择 +typedef enum{LSI_AS_LFCLK =0, LSE_AS_LFCLK }LFCLK_SWITCH_SEL; //LFCLK输入源选择 +typedef enum{HSI_SYSCLK = 0 ,HSE_SYSCLK , LFCLK_SYSCLK}SYSTEM_CLOCK_SEL; //选择系统时钟源，在离开stop模式时，系统会强制设置为00 + +/*--------时钟初始化配置结构体----------*/ +typedef struct ClockConfig +{ + MCU_CLOCK_OUTPUT_SEL MCO_SEL; //输入 + HSI_FREQ_SEL HSI_FREQ; //内部高速RC频率选择 + uint8_t HSE_OSC_FREQ; //外部高速晶振实际频率（单位MHZ） + uint16_t LSE_OSC_FREQ; //外部低速晶振实际频率（单位1） + SYSTEM_CLOCK_SEL SYSCLK_SEL; //系统时钟源的选择 + uint8_t ENS1_APB_PCLK_DIV_x; //PCLK分频选择 + uint8_t ENS1_AHB_PCLK_DIV_x; //HCLK分频选择 + LFCLK_SWITCH_SEL LFCLK_SW_SEL; //选择lfclk的输入源,为RTC的时钟输入 + +}Clock_ConfigStructure; + +extern uint32_t ClockInitSet(Clock_ConfigStructure* CLOCKCONFIG); +extern void ClockInit(void); +//PCLK 的时钟位 +#define UART0_PCLK_EN 0 +#define UART1_PCLK_EN 1 +#define SPI0_PCLK_EN 2 +#define SPI1_PCLK_EN 3 +#define I2C0_PCLK_EN 4 +#define I2C1_PCLK_EN 5 +#define WDT_PCLK_EN 6 +#define PWM_PCLK_EN 7 +#define TIMER0_PCLK_EN 8 +#define TIMER1_PCLK_EN 9 +#define DUAL_TIMER_PCLK_EN 10 +#define LCD_PCLK_EN 11 +#define WAVE_GEN_PCLK_EN 12 +#define ADC_PCLK_EN 13 +#define ANALOG_PCLK_EN 14 +#define RTC_PCLK_EN 15 +extern uint8_t PCLK_Enable(uint8_t APB_CLKEN_POS); +extern uint8_t PCLK_Disable(uint8_t APB_CLKEN_POS); +void HSE_ClockInit(uint32_t Clock_Freq); +#endif + diff --git a/FWLIB/include/ENS1_EXTI.h b/FWLIB/include/ENS1_EXTI.h new file mode 100644 index 0000000..a870840 --- /dev/null +++ b/FWLIB/include/ENS1_EXTI.h @@ -0,0 +1,93 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_EXTI.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#ifndef ENS1_EXTI_H +#define ENS1_EXTI_H +#include "my_header.h" +/* +0-23 : GPIO +24 : LVD output +25 : COMP0 output +26 : COMP1 output +27 : charge_ok +28 : charge_end +29 : over temperature +30 : rtc_alarm +31 : rtc_wut +*/ +typedef enum { + EXTI_GPIO0=0, + EXTI_GPIO1=1, + EXTI_GPIO2=2, + EXTI_GPIO3=3, + EXTI_GPIO4=4, + EXTI_GPIO5=5, + EXTI_GPIO6=6, + EXTI_GPIO7=7, + EXTI_GPIO8=8, + EXTI_GPIO9=9, + EXTI_GPIO10=10, + EXTI_GPIO11=11, + EXTI_GPIO12=12, + EXTI_GPIO13=13, + EXTI_GPIO14=14, + EXTI_GPIO15=15, + EXTI_GPIO16=16, + EXTI_GPIO17=17, + EXTI_GPIO18=18, + EXTI_GPIO19=19, + EXTI_GPIO20=20, + EXTI_GPIO21=21, + EXTI_GPIO22=22, + EXTI_GPIO23=23, + EXTI_LVDOUTPUT=24, + EXTI_COMP0=25, + EXTI_COMP1=26, + EXTI_CHARGE_OK=27, + EXTI_CHARGE_END=28, + EXTI_OVER_TEMP=29, +}EXTI_NUM; + +/* +寄存器： +EXTI_RTSR: 上升沿触发选择寄存器 +EXTI_FTSR: 下降沿触发选择寄存器 +EXTI_SWIER: 软件中断事件 +EXTI_RPR: 上升沿挂起寄存器 +EXTI_FPR: 下降沿挂起寄存器 +EXTI_IMR: 带中断掩码的CPU唤醒寄存器 +EXTI_EMR: 带有事件掩码的CPU唤醒寄存器 +*/ + +/*每一位在相应的线路上使能/失能事件或中断的上升沿触发 0-29*/ +void EXTI_RisingTriggerSelect(EXTI_NUM NUM , FunctionalState newstate); +/*每一位在相应的线路上使能/失能事件或中断的下降沿触发 0-29*/ +void EXTI_FallingTriggerSelect(EXTI_NUM NUM ,FunctionalState newstate); +/*软件中断设置：通过软件设置某一位的上升沿发生从而导致上升沿中断（软件中断）发生，仅仅可写 0-29*/ +void EXTI_SoftwareInterruptEventSet(EXTI_NUM NUM); +/*读取上升沿触发请求数据（用于判断上升沿事件发生）*/ +bool Read_EXTI_RisingEdgePending(EXTI_NUM NUM); +/*读取下降沿触发请求数据（用于判断下降沿事件发生）*/ +bool Read_EXTI_FallingEdgePending(EXTI_NUM NUM); +/*清除/屏蔽 唤醒CPU的中断线（0：用被屏蔽的中断唤醒 1：用未被屏蔽的中断唤醒）0-31*/ +void EXTI_INT_MASK(uint8_t NUM); +/*设置/清除 事件生成唤醒CPU */ +void EXTI_EVENT_MASK(uint8_t NUM); + + + +#endif + diff --git a/FWLIB/include/ENS1_GPIO.h b/FWLIB/include/ENS1_GPIO.h new file mode 100644 index 0000000..9c8b1b8 --- /dev/null +++ b/FWLIB/include/ENS1_GPIO.h @@ -0,0 +1,43 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_GPIO.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + 1 uint8_t GPIO_AltFunction(GPIO_NUM GPIO_X , GPIO_AltFuncSel GPIO_AltFuncSelx); + 2 int8_t GPIO_IO_Select(GPIO_NUM GPIO_X, I_O_SELECT INorOUT ,FunctionalState ENABLEorNOT); + 3 uint8_t GPIO_GetInputValue(GPIO_NUM GPIO_X); + 4 uint8_t GPIO_GetOutputValue(GPIO_NUM GPIO_X); + 5 void GPIO_Output(GPIO_NUM GPIO_X,LEVELStatus HIGHorLOW); + 6 void GPIO_SetOutput(GPIO_NUM GPIO_X); + 7 void GPIO_ResetOutput(GPIO_NUM GPIO_X); + 8 void GPIO_Overturn(GPIO_NUM GPIO_X); + 9 void GPIO_AnalogChannel_Control(GPIO_NUM GPIO_X ,FunctionalState ENABLEorNOT ); +History: +1.V1.0 +Date: +Author: +Modification: 初版 +*/ +#ifndef ENS1_GPIO_H +#define ENS1_GPIO_H +#include "my_header.h" +#include "CMSDK_CM0.h" +extern uint8_t GPIO_AltFunction(GPIO_NUM GPIO_X , GPIO_AltFuncSel GPIO_AltFuncSelx); +extern int8_t GPIO_IO_Select(GPIO_NUM GPIO_X, I_O_SELECT INorOUT ,FunctionalState ENABLEorNOT); +extern uint8_t GPIO_GetInputValue(GPIO_NUM GPIO_X); +extern uint8_t GPIO_GetOutputValue(GPIO_NUM GPIO_X); +extern void GPIO_Output(GPIO_NUM GPIO_X,LEVELStatus HIGHorLOW); +extern void GPIO_SetOutput(GPIO_NUM GPIO_X); +extern void GPIO_ResetOutput(GPIO_NUM GPIO_X); +extern void GPIO_Overturn(GPIO_NUM GPIO_X); +extern void GPIO_AnalogChannel_Control(GPIO_NUM GPIO_X ,FunctionalState ENABLEorNOT ); + + + +#endif + + + diff --git a/FWLIB/include/ENS1_IIC.h b/FWLIB/include/ENS1_IIC.h new file mode 100644 index 0000000..e804bc8 --- /dev/null +++ b/FWLIB/include/ENS1_IIC.h @@ -0,0 +1,153 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_I2C.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#ifndef ENS1_IIC_H +#define ENS1_IIC_H +#include "my_header.h" +#include "ens1_uart.h" +#include "ENS1_GPIO.h" +/* +一、引脚关系： +ALT Function1 +IIC0 SCL --- GPIO6 +IIC0 SDA --- GPIO7 + +ALT Function2 +IIC1 SCL --- GPIO8 +IIC1 SDA --- GPIO9 + +ENS1 IIC ： +1、标准模式100khz 快速模式 400khz +2、DMA +3、主机模式下通过软件发出启停信号 +4、从机模式下，接口可以识别自己的地址和一般呼叫地址，一般呼叫地址监测可以通过软件使能或失能 +5、数据和地址的传输以8位，大端模式，开始后的字节包含地址信息，（7bit地址模式是一字节，10bit地址模式是2字节） + 地址总时在主机模式下传输。 +6、在一个字节传输的8个时钟周期后的第九个时钟，接收端必须发送一个应答位给传输端 + 应答可以被软件使能或者失能，可以通过软件选择地址是7位还是10位的。 + +特性说明： +1、可做主、从端 +2、半双工通讯（仅发送或接收） +3、7位 / 10位的寻址或检测 +4、支持不同传输速率： 100k 400k +5、模拟噪声滤波器 +6、状态标志： + （1）传输/接收模式标志 + （2）字节结束传输标志 + （3）IIC 繁忙标志 +7、数据总是大端模式 +8、错误标志： +（1）主模式下:仲裁丢失状态 +（2）地址 / 数据传输后应答失败 +（3）错位启动或停止 状态的检测 +9、1字节缓冲带有DMA功能 +*/ + +/* +错误状态（会造成通讯失败） +1 总线错误 BUS ERROR +2 应答错误 AD +3 仲裁 +4 溢出/下溢 错误 +*/ + +/*IIC 速度选择*/ +#define IIC_STARDARD_MODE_10K 0x0 +#define IIC_STARDARD_MODE_20K 0x1 +#define IIC_STARDARD_MODE_100K 0x9 + +#define IIC_FAST_MODE_110K 0xA +#define IIC_FAST_MODE_120K 0xB +#define IIC_FAST_MODE_400K 0x27 + +#define IIC_HIGH_MODE_500K 0x28 +#define IIC_HIGH_MODE_600K 0x29 +#define IIC_HIGH_MODE_1500K 0x2E + +/*中断使能*/ +#define IIC_ITERREN (1<<6) //error 使能 +#define IIC_ITEVTEN (1<<7) //事件中断使能 +#define IIC_ITBUFEN (1<<8) //缓冲区中断使能 +#define IIC_DMAEN (1<<9) //DMA使能 + + + + +typedef enum{IIC_MASTER=0, IIC_SLAVE=1}IIC_MODE ; + +typedef struct IIC_Config_Struct +{ + IIC_MODE MODE; + uint32_t OWN_ADDRESS; + bool ACK_EN; + uint8_t IIC_SPEED; +}IIC_ConfigStructure; + +extern IIC_ConfigStructure IIC0_Config; +extern IIC_ConfigStructure IIC1_Config; + +//bus error 判断（ITERREN使能） +extern bool IIC_BUS_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//应答错误判断 +extern bool IIC_ACK_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//仲裁 +extern bool IIC_ARBITRAT_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//溢出/下溢错误 +extern bool IIC_OVERRUN_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx); + +//ITEVFEN使能后有如下事件 +//起始状态，起始位发送（主机模式） +extern bool IIC_SB_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//地址发送（主机模式） / 地址匹配（从机事件） +extern bool IIC_ADDR_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//主机模式下，主机已发送10bit地址数据的第一个字节！！！ +extern bool IIC_ADD10_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//从机模式下，停止条件被接收到 +extern bool IIC_STOPF_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//数据字节传输成功 +extern bool IIC_BTF_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx); + +//ITEVFEN 且 ITBUFEN 使能后，有如下事件 +//数据寄存器非空（接受器读到数据） +extern bool IIC_RxNE_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//数据寄存器空（传输完数据） +extern bool IIC_TxE_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx); + +//总线状态：繁忙与否 +extern uint8_t IIC_Bus_BUSY(CMSDK_I2C_TypeDef* CMSDK_I2Cx); + +//模式确认 +extern bool IIC_MASTER_MODE(CMSDK_I2C_TypeDef* CMSDK_I2Cx); + + + +//IIC配置初始化 +extern uint8_t IIC_Config_init(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,IIC_ConfigStructure* IIC_Para ); +//使能与失能IIC +extern void IIC_Cmd(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,FunctionalState NewState) ; +//应答选择 +extern void IIC_Ackconfig(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,FunctionalState NewState ); +//生成START 信号 +extern void IIC_GenerateSTART(CMSDK_I2C_TypeDef* CMSDK_I2Cx); +//生成STOP信号 +extern void IIC_GenerateSTOP(CMSDK_I2C_TypeDef* CMSDK_I2Cx); + +//IIC发送数据 +extern void IIC_SendData(CMSDK_I2C_TypeDef* CMSDK_I2Cx , uint8_t data); + +extern void IIC_ITConfig(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,uint16_t IIC_IT_SEL ,FunctionalState NewState); +#endif diff --git a/FWLIB/include/ENS1_MTP.h b/FWLIB/include/ENS1_MTP.h new file mode 100644 index 0000000..2964cd1 --- /dev/null +++ b/FWLIB/include/ENS1_MTP.h @@ -0,0 +1,62 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_MTP.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + 1 uint8_t MTP_init(void); + 2 void MTP_TRIM(STRUCT_MTP_TRIM TRIM); + 3 void flash_read(uint32_t start_addr,uint16_t *test_i); + 4 int8_t flash_buff_write(uint32_t start_addr, uint16_t *buff); + 5 int8_t flash_write_ctrl(uint16_t *buff , uint32_t start_addr); + 6 int8_t write_data(void); +History: +1.V1.0 +Date: +Author: +Modification: 初版 +*/ + + +#ifndef ENS1_MTP_H +#define ENS1_MTP_H +#include "CMSDK_CM0.h" +#include +#include +#include "my_header.h" +#define MTP_BASE_ADDR CMSDK_MTP_BASE //0x10000000 +#define MTP_SIZE 0x8000 //32KBytes +#define HW32_REG(ADDRESS) (*((volatile unsigned int *)(ADDRESS))) +#define HW16_REG(ADDRESS) (*((volatile uint16_t *)(ADDRESS))) +#define DATA_SAVE_ADDR (MTP_BASE_ADDR + 0x6F00) //第0x1BC0块 + +typedef struct STRUCT_MTP_TRIM +{ + __I uint32_t DEV_ID1:32; + __I uint32_t DEV_ID2:32; + __I uint32_t DEV_ID3:32; + __IO uint8_t OSCA_FT:5; + __IO uint8_t OSC32K_RTRIM:5; + __IO uint8_t BG_TRIM:8; +}STRUCT_MTP_TRIM; + + + + + +extern uint8_t MTP_init(void); +extern void MTP_TRIM(STRUCT_MTP_TRIM TRIM); +extern void flash_read(uint32_t start_addr,uint16_t *test_i); +extern int8_t flash_buff_write(uint32_t start_addr, uint16_t *buff); +extern int8_t flash_write_ctrl(uint16_t *buff , uint32_t start_addr); +extern int8_t write_data(void); + + + + + + + +#endif diff --git a/FWLIB/include/ENS1_PWM.h b/FWLIB/include/ENS1_PWM.h new file mode 100644 index 0000000..6528b16 --- /dev/null +++ b/FWLIB/include/ENS1_PWM.h @@ -0,0 +1,83 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_PWM.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ +#ifndef ENS1_PWM_H +#define ENS1_PWM_H +#include "my_header.h" +#include "ENS1_CLOCK.h" + +#define PRESCALE_PWM 1 +/* +复用引脚 +GPIO16 PWM1 +GPIO17 PWM2 +GPIO18 PWM3 +GPIO19 PWM4 +GPIO20 PWM5 +GPIO21 PWM6 +*/ +typedef enum +{ + IO16_PWM1 = 1 , + IO17_PWM2 = 2 , + IO18_PWM3 = 3 , + IO19_PWM4 = 4 , + IO20_PWM5 = 5 , + IO21_PWM6 = 6 +}ENS1_PWM_CHANNEL; + + +/* +ENS1 PWM 功能特性 +1、6个单边沿 和 3个双边沿控制输出 或 1个两种类型的混合 +2、脉冲周期和宽度可以是任意定时器计数值 +3、双边沿控制PWM输出可以被编程为正极或负极输出 +4、匹配寄存器更新与脉冲输出同步以避免产生错误脉冲 +5、如不启用PWM功能可作为标准定时器 +6、一个有着32位预分频器的32位计时器 +*/ + +/* +PWM使用说明： +1、2个匹配寄存器用于单边沿PWM输出控制，其中PWMMR0控制PWM周期速率，另一个匹配寄存器控制边沿位置（即控制脉宽） +2、3个匹配寄存器可用于双边沿PWM输出控制，其中PWMMR0控制PWM周期速率，另两个匹配控制寄存器控制双边位置 +3、使用双边沿PWM的控制可以生成正向和负向脉冲 +*/ + + +/*------------------------------------------------函数声明---------------------------------------------*/ +/*PWM初始化*/ +typedef enum {pwm_single_mode = 0,pwm_double_positive_mode , pwm_double_negtive_mode } PWM_EDGE_MODE; + +typedef struct ENS1_PWM_Para +{ + PWM_EDGE_MODE mode; + uint32_t pwm_freq; + uint8_t pwm_Duty_cycle ; + + +}PWM_ParaStructrue; + + +void PWM_init(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue* PWM_Para , bool pwmEnable) ; +void PWM_SetFreq(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue * PWM_Para ); +void PWM_SetDutyCycle_SingleMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle); +void PWM_SetDutyCycle_DoublePositiveMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle); +void PWM_SetDutyCycle_DoubleNegtiveMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle); +void PWM_OutputDisable(ENS1_PWM_CHANNEL PWMx); +void PWM_OutputEnable(ENS1_PWM_CHANNEL PWMx); + + +#endif diff --git a/FWLIB/include/ENS1_SPI.h b/FWLIB/include/ENS1_SPI.h new file mode 100644 index 0000000..baa46e3 --- /dev/null +++ b/FWLIB/include/ENS1_SPI.h @@ -0,0 +1,207 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_SPI.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + 1 uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx) + 2 uint8_t CLR_TX_FIFO(CMSDK_SPI_TypeDef* SPIx) + 3 uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx) + 4 uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx) + 5 uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx) + 6 SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx) + 7 uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) + 8 uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) + 9 uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) + 10 uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) + 11 uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx) + 12 uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx ) + 13 uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx ) + 14 uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET) + 15 uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS) + 16 uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , struct SPI_ModeConfig_Struct SPI_Config ,struct SPI_FIFO_Struct FIFO_Struct) + 17 uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx) + 18 uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx) + 19 uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx ) + 20 void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data) + 21 uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET) +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#ifndef ENS1_SPI_H +#define ENS1_SPI_H +#include "my_header.h" + +/* +一、引脚关系： +ALT Function2 +SPI1_SCK --- GPIO16 +SPI1_MOSI --- GPIO17 +SPI1_MISO --- GPIO18 +SPI1_NSS0 --- GPIO19 +SPI1_NSS1 --- GPIO2 +SPI1_NSS2 --- GPIO3 +SPI1_NSS3 --- GPIO4 + +ALT Function2 +SPI0_SCK --- GPIO8 +SPI0_MOSI --- GPIO9 +SPI0_MISO --- GPIO10 +SPI0_NSS0 --- GPIO11 +SPI0_NSS1 --- GPIO13 +SPI0_NSS2 --- GPIO14 +SPI0_NSS3 --- GPIO15 + +二、SPI功能列表说明： +三条线路上的全双工同步传输 +双线半双工同步传输 +两线单工同步传输（带单向数据线） +16*16bits FIFO 收发缓冲区 +4-16位数据大小选择 +主模式波特率发生器高达Fpclk/2 +从模式波特率发生器高达Fpclk/4 +软件或硬件管理 NSS +可编程时钟极性和相位 +可编程的数据顺序与MSB或LSB移位 +DMA事件支持 +中断支持 + +*/ + + + +typedef enum {MASTER = 1 ,SLAVE= 0}MASTER_SLAVE_SEL; +typedef enum {NSS0= 8 ,NSS1 ,NSS2 ,NSS3}NSS_CHANNEL_SEL ; +typedef enum {NOTBUSY = 0, BUSY}SPI_BUSY_STATE ; +typedef enum {EMPTY=0,FULL}FIFO_FULL_EMPTY_STATE; + +struct SPI_ModeConfig_Struct +{ + uint8_t BAUD_FPCLKdivx ; //波特率分频系数 + uint8_t SPI_MODE ; //SPI工作模式 + uint8_t SPI_TRANS_MODE; //传输模式选择 + MASTER_SLAVE_SEL MS_SEL; //主从模式选择 + uint16_t CHAR_LEN ; //设置传输长度 （4 - 16 bit） + NSS_CHANNEL_SEL NSSx ; + uint8_t SAMP_PHASE ; + +}; +struct SPI_FIFO_Struct //设置FIFO及DMA传输 +{ + uint8_t TX_FIFO_TH; // 0 - 16 char + uint8_t RX_FIFO_TH; // 0 - 16 char + bool FIFO_ENABLE_SET; + bool TXDMA_SET; //选择是否启动DMA(fifo开启的前提下) + bool RXDMA_SET; +}; + +/* 中断类型使能结构体 +1、发送部分有 下溢 中断（发送数据没有啦） +2、接收部分有 溢出 中断（接满啦） +3、收发完成中断？ +4、发送缓冲区空 中断 +5、接收缓冲区非空 中断 +*/ +//中断使能 +#define UNDERRUN_INT_EN (uint8_t)0x10 +#define OVERRUN_INT_EN (uint8_t)0x8 +#define CMPL_INT_EN (uint8_t)0x4 +#define TXE_INT_EN (uint8_t)0x2 +#define RXNE_INT_EN (uint8_t)0x1 + +//判断是否检测到对应的中断 +#define UNDERRUN_INT (uint8_t)0x10 +#define OVERRUN_INT (uint8_t)0x8 +#define CMPL_INT (uint8_t)0x4 +#define TXE_INT (uint8_t)0x2 +#define RXNE_INT (uint8_t)0x1 + + +/*模式： | 接线方式： 主机 从机 +全双工 | MISO/MOSI MISO/MOSI +半双工 | MOSI MISO +主机仅发送，从机仅接收模式 | MOSI MOSI +主机仅接收，从机仅发送模式 | MISO MISO + + SPI_TRANS_MODE 传输模式选择： + 2线单向 / 1线双向 + 收+发 / 仅发 /仅收/ 单向仅发送 / 仅接收 +*/ +#define L2_UniDirect_TandR (uint8_t)0x0 //BIT[15:12] 0 0 00 +#define L2_UniDirect_T (uint8_t)0x1 //BIT[15:12] 0 0 01 +#define L2_UniDirect_R (uint8_t)0x2 //BIT[15:12] 0 0 10 +#define L1_BiDirect_T (uint8_t)0x8 //BIT[15:12] 1 0 00 +#define L1_BiDirect_R (uint8_t)0xc//BIT[15:12] 1 1 00 + +/*NSS相关设置*/ +#define NSS_PULSE 1 //有nss +#define NO_NSS_PULSE 0 //没有nss +#define NSS_ASSERTED 0 // +#define NSS_DEASSERYED 1 //软件发出nss信号 +#define NSS_CTRL_HW 0 //设置为硬件生成NSS +#define NSS_CTRL_SW 1 //设置为软件生成NSS + +/*波特率设置*/ +#define BAUD_FPCLKdiv2 (uint8_t)0x0 +#define BAUD_FPCLKdiv4 (uint8_t)0x1 +#define BAUD_FPCLKdiv8 (uint8_t)0x2 +#define BAUD_FPCLKdiv16 (uint8_t)0x3 +#define BAUD_FPCLKdiv32 (uint8_t)0x4 +#define BAUD_FPCLKdiv64 (uint8_t)0x5 +#define BAUD_FPCLKdiv128 (uint8_t)0x6 +#define BAUD_FPCLKdiv256 (uint8_t)0x7 + +/*SPI_MODE 工作模式选择*/ +#define SPI_MODE0 (uint8_t)0x0 //bit[3:2] 00 +#define SPI_MODE1 (uint8_t)0x1 // 01 +#define SPI_MODE2 (uint8_t)0x2 // 10 +#define SPI_MODE3 (uint8_t)0x3 // 11 + + +/*SAMP_PHASE 选项*/ +#define PRE_1_PCLK_PERIOD (uint8_t)0X0 +#define SAMP_PHASE_NORMAL (uint8_t)0X1 +#define DELAY_1_PCLK_PERIOD (uint8_t)0X2 +#define DELAY_2_PCLK_PERIOD (uint8_t)0X3 + +/*****************************声明 和 定义***************************/ +#define SPI0_CS_SET GPIO_SetOutput(GPIO_11) +#define SPI0_CS_RESET GPIO_ResetOutput(GPIO_11) +#define SPI1_CS_SET GPIO_SetOutput(GPIO_19) +#define SPI1_CS_RESET GPIO_ResetOutput(GPIO_19) + + +//读SPI当前设置的模式 +extern uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx); +/*清除FIFO和计数清0*/ +extern uint8_t CLR_TX_FIFO(CMSDK_SPI_TypeDef* SPIx); +extern uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx) ; +/*FIFO 状态读取*/ +extern uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx); //读取当前接收FIFO数据长度 +extern uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx) ; //读取当前发送FIFO数据长度 +extern SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx) ; //读取当前SPI是否繁忙 +extern uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) ; //当前读取FIFO是否为满？ +extern uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) ; //当前读取FIFO是否为空？ +extern uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) ;//当前发送FIFO是否为满？ +extern uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) ; //当前发送FIFO是否为空？ +extern uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx); +extern uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx ); //FIFO功能使能 +extern uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx ); //FIFO功能失能 +extern uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET); //DMA设置 +extern uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS); //nss通道选择 +extern uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , struct SPI_ModeConfig_Struct SPI_Config ,struct SPI_FIFO_Struct FIFO_Struct); //spi的初始配置 +extern uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx); +extern uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx); +//读被接收的数据 最多16bits +extern uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx ); +//写数据 +extern void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data); +extern uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET); + +#endif diff --git a/FWLIB/include/ENS1_TIMER.h b/FWLIB/include/ENS1_TIMER.h new file mode 100644 index 0000000..f2ed538 --- /dev/null +++ b/FWLIB/include/ENS1_TIMER.h @@ -0,0 +1,43 @@ +#ifndef ENS1_TIMER_H +#define ENS1_TIMER_H +#include "CMSDK_CM0.h" +#include "my_header.h" +typedef enum {TOTAL_TIME_MODE = 0 , TRIGGER_TIME_MODE=1}TIME_COUNT_MODE; //选择为总时间或有效运行时间 +extern void TIMER0_Init(uint32_t Int_Period); +extern void TIMER1_Init(uint32_t Int_Period); +extern volatile uint32_t CHANNEL_TIME_COUNT[4]; +extern volatile uint32_t TRIGGER_TIME_COUNT[4]; +extern volatile uint32_t TOTAL_TIME_THRESHOLD_VALUE[4]; +extern volatile uint32_t TRIGGER_TIME_THRESHOLD_VALUE[4]; +extern volatile uint8_t TRIGGER_TIME_COUNT_FLAG; +extern void CMSDK_timer_EnableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER); +extern void CMSDK_timer_DisableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER); +extern void CMSDK_timer_StartTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER); +extern void CMSDK_timer_StopTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER); +extern uint32_t CMSDK_timer_GetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER); +extern void CMSDK_timer_SetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value); +extern uint32_t CMSDK_timer_GetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER); +extern void CMSDK_timer_SetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value); +extern void CMSDK_timer_ClearIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER); +extern uint32_t CMSDK_timer_StatusIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER); +extern void CMSDK_timer_Init(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload, uint8_t irq_en); +extern void CMSDK_timer_Init_ExtClock(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,uint32_t irq_en); +extern void CMSDK_timer_Init_ExtEnable(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,uint32_t irq_en); +extern void CMSDK_dualtimer_start(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx); +extern void CMSDK_dualtimer_stop(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx); +extern void CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx); +extern void CMSDK_dualtimer_setup_freerunning(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx, + unsigned int cycle, unsigned int prescale, + unsigned int interrupt, unsigned int size); +extern void CMSDK_dualtimer_setup_periodic(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx, + unsigned int cycle, unsigned int prescale, + unsigned int interrupt, unsigned int size); +extern void CMSDK_dualtimer_setup_oneshot(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx, + unsigned int cycle, unsigned int prescale, + unsigned int interrupt, unsigned int size); +extern void CMSDK_RTC_Init_Calender(uint16_t prescaler, uint8_t data_mode, uint8_t hour_mode, uint32_t init_time, uint32_t init_date); +extern void CMSDK_RTC_Config_Alarm(uint16_t prescaler, uint8_t data_mode, uint8_t hour_mode, uint32_t init_time, uint32_t init_date, uint32_t alarm_time, uint32_t alarm_date) ; +extern void CMSDK_RTC_Config_PeriodWake(uint8_t clock_sel, uint16_t prescaler, uint16_t period_time); + +#endif + diff --git a/FWLIB/include/ENS1_UART.h b/FWLIB/include/ENS1_UART.h new file mode 100644 index 0000000..de5e53d --- /dev/null +++ b/FWLIB/include/ENS1_UART.h @@ -0,0 +1,147 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_UART.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: +1 void UART_Init(CMSDK_UART_TypeDef *CMSDK_UART, UART_InitStructure* uart_paraX); +2 void UART_ITConfig(CMSDK_UART_TypeDef *CMSDK_UART, UART_ITStructure* uart_paraX); +3 unsigned char UartPutc(CMSDK_UART_TypeDef *CMSDK_UART ,unsigned char my_ch); + +History: +1.V1.0 +Date: +Author: +Modification: 初版 +*/ +#ifndef _ENS1_UART_H_ +#define _ENS1_UART_H_ + +#include "MY_HEADER.h" +#include "CMSDK_CM0.h" +#include "ENS1_CLOCK.h" +#include "math.h" + +#define UART0_RX GPIO_2 +#define UART0_TX GPIO_3 +#define UART0_RTS GPIO_4 +#define UART0_CTS GPIO_5 +#define UART1_RX GPIO_12 +#define UART1_TX GPIO_13 +#define UART1_RTS GPIO_14 +#define UART1_CTS GPIO_15 + +#define InterruptDisable __disable_irq +#define InterruptEnable __enable_irq +typedef enum uartRcvfifoTrigger{byte_1=0 , bytes_4=1,bytes_8=2,bytes_14=3}uartRcvTrigger; +typedef enum {OverSamp_16 = 0,OverSamp_13}UART_OverSamp; +/*uart参数设置结构体*/ + +typedef struct uart_fifo{ + uartRcvTrigger level; + uint8_t DMA_Enable ; + uint8_t FIFO_Enable ; +}UART_FifoStructrue; + +typedef struct uart_para{ + uint8_t UART_OverSampMode; + uint32_t UART_BaudRate; + uint8_t UART_HardwareFlowControl; //硬件流控是否开启 + UART_FifoStructrue* FifoSetting ; +}UART_InitStructure; + +extern UART_FifoStructrue UART0_Fifo; +extern UART_InitStructure UART0_Init; +extern UART_FifoStructrue UART1_Fifo; +extern UART_InitStructure UART1_Init; + +/* +中断资源说明： +1、THREINT THR发送寄存器或发送FIFO空 +2、RDAINT 接收寄存器数据可用 ，FIFO模式下触发接收阈值 +3、RTOINT FIFO模式下接收超时：在最后四个字节时间内没有字节移除或者输入，在这个时间内至少有一个字节在接收FIFO中 +4、RLSINT 接收线路状态：发生了溢出错误，校验错误，帧错误或者中断 +5、MSIINT 调制解调器状态：CTS更改状态（禁用autoflow），DSR/RI/DCD更改状态 +*/ +/*中断使能*/ +#define MSI_EN (uint8_t)0X8 +#define RLSI_EN (uint8_t)0X4 +#define THRE_EN (uint8_t)0X2 +#define RDAI_EN (uint8_t)0X1 +/*中断信息*/ +#define INT_MODEM_STATUS (uint8_t)0X0 +#define INT_THR_EMPTY (uint8_t)0X1 +#define INT_RCV_DATA_AVAILABLE (uint8_t)0X2 +#define INT_RCV_LINE_STATUS (uint8_t)0X3 +#define INT_CHAR_TIMEOUT_INDICATION (uint8_t)0X6 + +typedef struct uart_it_para{ + uint8_t UartIntModel ; //选择中断的模式 + uint8_t UartDMAEnable; //选择是否开启DMA +}UART_ITStructure; + +extern UART_ITStructure UART0_ITSet; +extern UART_ITStructure UART1_ITSet; + +#define UART_WordLength_5b ((uint8_t)0x00) +#define UART_WordLength_6b ((uint8_t)0x01) +#define UART_WordLength_7b ((uint8_t)0x02) +#define UART_WordLength_8b ((uint8_t)0x03) + +#define UART_NO_PARITY ((uint8_t)0x00 & 0xff) +#define UART_LOGIC_1_ODD_NUM ((uint8_t)0x08 & 0xff) //逻辑1奇数个 +#define UART_LOGIC_1_EVEN_NUM ((uint8_t)0x18 & 0xff) //逻辑1偶数个 +#define UART_STICK_PARITY_AS1 ((uint8_t)0x28 & 0xff) //固定奇偶校验为1 +#define UART_STICK_PARITY_AS0 ((uint8_t)0x38 & 0xff) + + +/*中断信息读取*/ +/*中断挂起*/ +uint8_t UART_INT_PEND(CMSDK_UART_TypeDef* UARTx); //为0时有UART的中断挂起 +/*中断状态判断*/ +uint8_t UART_INT_TYPE(CMSDK_UART_TypeDef* UARTx); +/*fifo 使用指示器*/ +uint8_t UART_FIFO_USE(CMSDK_UART_TypeDef* UARTx); //0:非fifo模式 1：fifo 使能 +/*清除传输FIFO*/ +void UART_TXCLR(CMSDK_UART_TypeDef* UARTx); +/*清除接收FIFO*/ +void UART_RXCLR(CMSDK_UART_TypeDef* UARTx); +/*FIFO使能*/ +void UART_FIFOEnable(CMSDK_UART_TypeDef* UARTx); +/*FIFO关闭*/ +void UART_FIFODisable(CMSDK_UART_TypeDef* UARTx); + +/*接收数据*/ +uint8_t READ_UART_RCVBuff(CMSDK_UART_TypeDef* UARTx ); +/*发送数据*/ +void WRITE_UART_THRBuff(CMSDK_UART_TypeDef* UARTx ,uint8_t data); + +/*FIFO状态获取*/ +uint8_t UART_RX_FIFO_LEN(CMSDK_UART_TypeDef* UARTx) ; +uint8_t UART_TX_FIFO_LEN(CMSDK_UART_TypeDef* UARTx) ; +uint8_t UART_RX_FIFO_FULL(CMSDK_UART_TypeDef* UARTx) ; +uint8_t UART_RX_FIFO_EMPTY(CMSDK_UART_TypeDef* UARTx) ; +uint8_t UART_TX_FIFO_FULL(CMSDK_UART_TypeDef* UARTx) ; +uint8_t UART_TX_FIFO_EMPTY(CMSDK_UART_TypeDef* UARTx) ; + +/*收发线状态获取*/ +uint8_t UARTLine_RCVError(CMSDK_UART_TypeDef* UARTx); + +/*判断发送缓存是否为空*/ +uint8_t UARTLine_TRANSEmpty(CMSDK_UART_TypeDef* UARTx); + +/*判断THR是否为空*/ +uint8_t UARTLine_THREmpty(CMSDK_UART_TypeDef* UARTx); + +/*UART初始化*/ +void UART_Init(CMSDK_UART_TypeDef *CMSDK_UART, UART_InitStructure* uart_paraX); +void UART_ITConfig(CMSDK_UART_TypeDef *CMSDK_UART, UART_ITStructure* uart_paraX); +unsigned char UartPutc(CMSDK_UART_TypeDef *CMSDK_UART ,unsigned char my_ch); + + + + +#endif + diff --git a/FWLIB/include/ENS1_WATCHDOG.h b/FWLIB/include/ENS1_WATCHDOG.h new file mode 100644 index 0000000..0a3c6cc --- /dev/null +++ b/FWLIB/include/ENS1_WATCHDOG.h @@ -0,0 +1,43 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_WATCHDOG.h +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#ifndef ENS1_WATCHDOG_H +#define ENS1_WATCHDOG_H +#include "CMSDK_CM0.h" +#include "ENS1_CLOCK.h" +#include "my_header.h" +/* +1、watchdog寄存器有写锁，在写入watchdog的寄存器前需要对 WDOGLOCK 寄存器写入 0x1ACCE551 +2、watchdog的技术加载值： WDOGLOAD = interval(us) * pclk(MHZ) +3、计数重加载位置： WDOGVALUE +4、写1到 WDOGCONTROL 的 INTEN 位 ，使能看门狗和预警中断，当WDT计数到0，则触发一次中断 + 中断状态被知识通过设置 WDOGMIS位，如果 WDOGINTCLR 寄存器写入任意值（比如按照惯例，写1） + 此时WDOGMIS 位被清0 ，如果RESEN位是 0 ，watchdog定时器将重载。 +5、以上步骤设置完成后，写一个任意数据（除了0x1ACCE551）到WDOGLOCK寄存器 +6、如果WDT当前计数值没有重载， 计数到达0时 WDT 将触发一个早期预警中断 + 因此，在中断触发前需要重载 WDOGLOAD寄存器 +*/ +typedef enum{UNLOCK = 0,LOCK=1}WdogLockState; + +extern void WatchDogLoad(uint32_t loadvalue_us); +extern uint32_t Read_WDOGVALUE(void); +extern void WatchDog_Control(FunctionalState newstate); +extern void WatchDog_IntClear(void); +extern uint8_t WatchDog_LOCK_RegSet(WdogLockState newstate); +#endif + + + diff --git a/FWLIB/include/ENS_CURRENT_CALIBRATION.h b/FWLIB/include/ENS_CURRENT_CALIBRATION.h new file mode 100644 index 0000000..77e870a --- /dev/null +++ b/FWLIB/include/ENS_CURRENT_CALIBRATION.h @@ -0,0 +1,97 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_CURRENT_CALIBRATION.H +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#ifndef ENS_CURRENT_CALIBRATION_H +#define ENS_CURRENT_CALIBRATION_H + +#include "my_header.h" +#include "ENS1_TIMER.h" +#define PI 3.1415 +extern volatile uint8_t statics_config; //通道状态标志，[3:0] 每一位对应一个通道的状态 0：关闭中 1：开启状态 +extern uint8_t unit_current[4]; +extern volatile uint32_t NUM_OF_PULSES_THRESHOLD[4]; +extern volatile uint32_t wave_gen_irq_occurred[4]; +/* --------------------------电刺激有关的参数以及通道状态--------------------------- */ +/* +1、基本参数： +·基础波形类型 +·正向脉宽： +·负向脉宽： +·波形频率： +·电流大小： +·延迟输出时间 +2、复杂波形参数 +·中断点设置（每次可以设置两个点，且第1点需要小于第2点） +·交替波形频率： +·总输出时间设置 +·脉冲群中的脉冲个数 +·脉冲群与脉冲群的间隔发生时间 +*/ +typedef enum {SQUARE_WAVE = 0 ,SINE_WAVE = 1, TRIANGULAR_WAVE = 2 }BasicWaveformType; + +typedef struct COMPLEX_WAVEFORM_PARA +{ + uint16_t AlternatingFreq_HZ; + uint32_t TotalOutputTime_S; + uint32_t NumOfPulseGroups; + uint32_t TimeOfPulseGroups_MS; +}STRUCT_COMPLEX_WAVEFORM_PARA; + +typedef struct WAVEFORM_PARA +{ + BasicWaveformType Type; + uint32_t PositivePulseWidth; + uint32_t NegativePulseWidth; + //uint32_t WaveformFreq; + uint32_t ClientTime; + uint8_t DeadTime; + uint32_t DelayOutputTime_US; + STRUCT_COMPLEX_WAVEFORM_PARA OtherWaveformPara; +}STRUCT_WAVEFORM_PARA; + +extern STRUCT_WAVEFORM_PARA ParaSet_waveform[4]; + +/* ------------------------------------------------------------------------- */ + +/*--------------------------------波形设置的函数-----------------------------*/ +typedef enum ENS_DRV_CONFIG +{ + DISABLE_ALL_BIT = -1, + REST_BIT = 1, + NEGATIVE_BIT =2, + SILENT_BIT =4, + SOURCE_B_BIT = 8, + ALTERNATING_POSITIVE_BIT =16, + CONTINUE_REPEATING_BIT = 32, + MULTI_ELECTRODE_BIT = 64 , + ENABLE_ALL_BIT = 0X7F +}DRV_CONFIG; + +/*获取到FT测试后的实际测量单元电流值 */ +extern uint8_t GET_FT_CURRENT(void); +/*波形参数的设置*/ +extern uint32_t StimulatorInit(CHANNEL_NUM CHANNEL_X); +/*输出电流 / 频率*/ +extern uint8_t CURRENT_AMPLITUDE_MODIFY(CHANNEL_NUM CHANNEL_X , float mA); +extern uint32_t CURRENT_FREQ_MODIFY(CHANNEL_NUM CHANNEL_X , uint32_t freq); +/*电刺激时间*/ +extern uint32_t StimuTimeCount_S(CHANNEL_NUM CHANNEL_X , TIME_COUNT_MODE MODE); +/*启动停止*/ +void StartStimulatorOut(CHANNEL_NUM CHANNEL_X); +void StopStimulatorOut(CHANNEL_NUM CHANNEL_X); + + +#endif diff --git a/FWLIB/source/ENS1_ANAC.c b/FWLIB/source/ENS1_ANAC.c new file mode 100644 index 0000000..209d816 --- /dev/null +++ b/FWLIB/source/ENS1_ANAC.c @@ -0,0 +1,197 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_ANAC.c +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#include "ens1_anac.h" +#include "ENS1_CLOCK.h" +#include "ENS1_ADC.h" + +/*----------------------------------------------------COMP----------------------------------------------------------------*/ + +/*比较器的输出设置*/ +void CompInitSet(COMP_ConfigStructure* COMPCONFIG) +{ + if(COMPCONFIG->COMPARATOR_NUM == COMP0) + { + //IO复用 + GPIO_AltFunction(GPIO_8 , ALT_FUNC3); + GPIO_AltFunction(GPIO_9 , ALT_FUNC3); + GPIO_AltFunction(GPIO_10 , ALT_FUNC3); + GPIO_AltFunction(GPIO_11 , ALT_FUNC3); + GPIO_AltFunction(GPIO_20 , ALT_FUNC2); + CMSDK_ANAC->COMP0_CTRL |= ( COMPCONFIG->COMP_VREF_SEL << 4 ); + CMSDK_ANAC->COMP0_CTRL |= ( COMPCONFIG->COMP_SIGSEL_NEGATIVE_INPUT_SEL << 2 ); + CMSDK_ANAC->COMP0_CTRL |= ( COMPCONFIG->COMP_SIGSEL_POSITIVE_INPUT_SEL << 1 ); + } + else if(COMPCONFIG->COMPARATOR_NUM == COMP1) + { + GPIO_AltFunction(GPIO_12 , ALT_FUNC3); + GPIO_AltFunction(GPIO_13 , ALT_FUNC3); + GPIO_AltFunction(GPIO_14 , ALT_FUNC3); + GPIO_AltFunction(GPIO_15 , ALT_FUNC3); + GPIO_AltFunction(GPIO_21 , ALT_FUNC2); + CMSDK_ANAC->COMP1_CTRL |= ( COMPCONFIG->COMP_VREF_SEL << 4 ); + CMSDK_ANAC->COMP1_CTRL |= ( COMPCONFIG->COMP_SIGSEL_NEGATIVE_INPUT_SEL << 2 ); + CMSDK_ANAC->COMP1_CTRL |= ( COMPCONFIG->COMP_SIGSEL_POSITIVE_INPUT_SEL << 1 ); + } + else + return ; +} + +uint8_t Read_Comp_Output(COMP_NUM NUM) +{ + if(NUM == COMP0) + return (uint8_t)((CMSDK_ANAC->COMP0_CTRL >> 8)&0X1); + else + return (uint8_t)((CMSDK_ANAC->COMP1_CTRL >> 8)&0X1); +} + +void CompControl(COMP_NUM NUM ,FunctionalState Newstate) +{ + if(NUM == COMP0) + (Newstate == ENABLE)? (CMSDK_ANAC->COMP0_CTRL |= (1) ): ( CMSDK_ANAC->COMP0_CTRL &=~ (1)); + else + (Newstate == ENABLE)? (CMSDK_ANAC->COMP1_CTRL |= (1) ): ( CMSDK_ANAC->COMP1_CTRL &=~ (1)); +} + +/*--------------------------------------------------------PGA---------------------------------------------------------------*/ +//初始化 +void PGAInitSet(PGA_ConfigStructure* PGACONFIG) +{ + + if(PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN0) //PGA0 + { + GPIO_AltFunction(GPIO_16 , ALT_FUNC3); + GPIO_AltFunction(GPIO_18 , ALT_FUNC3); + GPIO_AnalogChannel_Control(GPIO_16 ,ENABLE ); + GPIO_AnalogChannel_Control(GPIO_18 ,ENABLE ); + } + + else if(PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN1) //PGA1 + { + GPIO_AltFunction(GPIO_17 , ALT_FUNC3); + GPIO_AltFunction(GPIO_19 , ALT_FUNC3); + GPIO_AnalogChannel_Control(GPIO_17 ,ENABLE ); + GPIO_AnalogChannel_Control(GPIO_19 ,ENABLE ); + } + + else if((PGACONFIG->PGA_NEG_SELx ==PGA_NEGATIVE_INPUT_INTERNAL_VCM) && ((PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_PGA_VIP0 )||(PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_PGA_VIP1))) //内部参考电压+0/1 + { + GPIO_AltFunction((GPIO_NUM)(GPIO_16+PGACONFIG->PGA_POS_SELx), ALT_FUNC3); + GPIO_AnalogChannel_Control((GPIO_NUM)(GPIO_16+PGACONFIG->PGA_POS_SELx) ,ENABLE ); + } + + else if((PGACONFIG->PGA_NEG_SELx ==PGA_NEGATIVE_INPUT_EXTERNAL_VCM) && ((PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_PGA_VIP0 )||(PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_PGA_VIP1))) //内部参考电压+0/1 + { + GPIO_AltFunction((GPIO_NUM)(GPIO_16+PGACONFIG->PGA_POS_SELx), ALT_FUNC3); + GPIO_AltFunction(GPIO_20, ALT_FUNC3); + GPIO_AnalogChannel_Control((GPIO_NUM)(GPIO_16+PGACONFIG->PGA_POS_SELx) ,ENABLE ); + GPIO_AnalogChannel_Control(GPIO_20 ,ENABLE ); + } + + else if((PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_INTERNAL_VCM) && ((PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN0)||(PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN1))) + { + GPIO_AltFunction((GPIO_NUM)(GPIO_18+PGACONFIG->PGA_POS_SELx), ALT_FUNC3); + GPIO_AnalogChannel_Control((GPIO_NUM)(GPIO_18+PGACONFIG->PGA_POS_SELx) ,ENABLE ); + } + else if((PGACONFIG->PGA_POS_SELx == PGA_POSITIVE_INPUT_VREF1_2V) && ((PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN0)||(PGACONFIG->PGA_NEG_SELx == PGA_NEGATIVE_INPUT_PGA_VIN1))) + { + GPIO_AltFunction((GPIO_NUM)(GPIO_18+PGACONFIG->PGA_POS_SELx), ALT_FUNC3); + GPIO_AnalogChannel_Control((GPIO_NUM)(GPIO_18+PGACONFIG->PGA_POS_SELx) ,ENABLE ); + } + else + { + return ; + } + + if(PGACONFIG->PGA_OUT == PGA_TO_GPIO4) + { + CMSDK_ADC->ADC_CH_SEL &=~ (0x7); + CMSDK_ADC->ADC_CH_SEL = 4; + GPIO_AltFunction(GPIO_4, ALT_FUNC3); + GPIO_AnalogChannel_Control(GPIO_4 ,ENABLE ); + ENS1_ADC_STOP(ENS1_PGA_TO_ADC); + } + else if(PGACONFIG->PGA_OUT == PGA_TO_ADC) + { + ENS1_ADCCLKConfig(ADC_CLK_base32div); + CMSDK_ADC->ADC_CH_SEL &=~ (0x7); + CMSDK_ADC->ADC_CH_SEL = 0; + ENS1_ADC_CONFIG(ENS1_PGA_TO_ADC , + CONTINUOUS_ADC_MODE, + COV_RCV_EOC , + ADC_SampleTime_5ADC_Clk, + ENABLE_EOC_INT); + ENS1_ADC_START(ENS1_PGA_TO_ADC); + } + else + { + return ; + } + CMSDK_ANAC->PGA_CTRL |= ( PGACONFIG->PGA_GAIN_SEL << 4 ); +} + +//PGA开关控制 +void PGAControl(FunctionalState Newstate) +{ + (Newstate == ENABLE) ? (CMSDK_ANAC->PGA_CTRL |= (0X3) ) : (CMSDK_ANAC->PGA_CTRL &=~ (0X3)) ; +} + + +/*----------------------------低电压与芯片过温检测--------------------------*/ +void PMU_TEMP150C_TRIGControl(FunctionalState Newstate) //过温检测功能开启与关闭 +{ + (Newstate==ENABLE) ? (CMSDK_ANAC->PMU_CTRL |= (1<<5) ) : (CMSDK_ANAC->PMU_CTRL &=~ (1<<5)); +} + +//返回温度是否超过150度的状态值 +int8_t TEMP_150C_TRIG_SIGNAL(void) +{ + if((CMSDK_ANAC->PMU_CTRL >> 5) & 0x1) + return ((CMSDK_ANAC->PMU_CTRL >> 7) & 0x1); + else + { + PMU_TEMP150C_TRIGControl(ENABLE); + return ((CMSDK_ANAC->PMU_CTRL >> 7) & 0x1); + } +} + +//低电压告警 +//设置阈值电压 +void LVD_InitSet(uint8_t Threshold_voltage) +{ + CMSDK_ANAC->PMU_CTRL |= (Threshold_voltage << 1); +} +//打开或关闭此功能 +void PMU_LVD_Control(FunctionalState Newstate) +{ + (Newstate == ENABLE) ? (CMSDK_ANAC->PMU_CTRL|= (1) ) : (CMSDK_ANAC->PMU_CTRL &=~ (1)) ; +} +//读取低电压状态 +uint8_t Read_LVD_Signal(void) +{ + return ((CMSDK_ANAC->PMU_CTRL >> 6) & 0x1); +} +/*------------------------带隙BUFFER启用或关闭-----------------------------------*/ +void PMU_BANDGAP_CONTROL(FunctionalState Newstate) +{ + (Newstate == ENABLE) ? (CMSDK_ANAC->PMU_CTRL |= (1<<4)) : (CMSDK_ANAC->PMU_CTRL &=~ (1<<4)) ; +} + + + + + + diff --git a/FWLIB/source/ENS1_BOOST.c b/FWLIB/source/ENS1_BOOST.c new file mode 100644 index 0000000..0d4f930 --- /dev/null +++ b/FWLIB/source/ENS1_BOOST.c @@ -0,0 +1,38 @@ +#include "ENS1_BOOST.h" +#include "ENS1_CLOCK.h" + + + +/*--------------------内部BOOST_SET-----------------------*/ +uint8_t Boost_Voltage_Sel(uint8_t VOLTAGE_XV) +{ + PCLK_Enable(ANALOG_PCLK_EN); + switch (VOLTAGE_XV){ + case VOLTAGE_11V : + CMSDK_ANAC->BOOST_CTRL =0x71013;//内部boost + CMSDK_ANAC->PMU_CTRL = 0x10; + break; + + case VOLTAGE_15V : + CMSDK_ANAC->BOOST_CTRL =0x71113;//内部boost + CMSDK_ANAC->PMU_CTRL = 0x10; + break; + case VOLTAGE_26V : + CMSDK_ANAC->BOOST_CTRL =0x71213;//内部boost + CMSDK_ANAC->PMU_CTRL = 0x10; + break; + case VOLTAGE_45V : + CMSDK_ANAC->BOOST_CTRL =0xc1413;// + CMSDK_ANAC->PMU_CTRL = 0x10; + break; + case VOLTAGE_55V : + CMSDK_ANAC->BOOST_CTRL =0xc1713;//内部boost + CMSDK_ANAC->PMU_CTRL = 0x10; + break; + default: + CMSDK_ANAC->BOOST_CTRL =0x71013;//内部boost + CMSDK_ANAC->PMU_CTRL = 0x10; + break; + } + return 0; +} diff --git a/FWLIB/source/ENS1_CLOCK.c b/FWLIB/source/ENS1_CLOCK.c new file mode 100644 index 0000000..156c67d --- /dev/null +++ b/FWLIB/source/ENS1_CLOCK.c @@ -0,0 +1,103 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_CLOCK.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: +1.V1.0 +Date: +Author: +Modification: 初版 +*/ + + +#include "ENS1_CLOCK.h" + +uint32_t APB_Clock_Freq =0; +//设置后的时钟频率请查看时钟树计算 +Clock_ConfigStructure CLOCKCFG= +{ + .MCO_SEL = MCO_HSI , + .HSI_FREQ = HSI_32MHZ , + .HSE_OSC_FREQ = 0, + .LSE_OSC_FREQ = 0, + .SYSCLK_SEL = HSI_SYSCLK , + .ENS1_APB_PCLK_DIV_x = ENS1_APB_PCLK_DIV_1, + .ENS1_AHB_PCLK_DIV_x = ENS1_AHB_HCLK_DIV_1, + .LFCLK_SW_SEL = LSI_AS_LFCLK , +}; + +uint32_t ClockInitSet(Clock_ConfigStructure* CLOCKCONFIG) +{ + uint32_t clockfreq = 0; + //配置系统各时钟初始化 + //1 确定输入频率 + CMSDK_SYSCON->CLK_CFG |= (CLOCKCONFIG->MCO_SEL<<16); + if(CLOCKCONFIG->MCO_SEL == MCO_HSI) + { + CMSDK_SYSCON->HSI_CTRL |= (CLOCKCONFIG->HSI_FREQ << 4); + clockfreq = (uint8_t)pow(2,CLOCKCONFIG->HSI_FREQ+2)*1000000; + } + else if(CLOCKCONFIG->MCO_SEL == MCO_HSE) + { + clockfreq = CLOCKCONFIG->HSE_OSC_FREQ * 1000000; + } + else if(CLOCKCONFIG->MCO_SEL == MCO_LSI) + { + clockfreq = 32768 ; + } + else if(CLOCKCONFIG->MCO_SEL == MCO_LSE) + { + clockfreq = CLOCKCONFIG->LSE_OSC_FREQ ; + } + else + { + CMSDK_SYSCON->HSI_CTRL |= (CLOCKCONFIG->HSI_FREQ << 4); + clockfreq = (uint8_t)pow(2,CLOCKCONFIG->HSI_FREQ+2); + } + //2 选择系统的时钟源 + CMSDK_SYSCON->CLK_CFG |= (CLOCKCONFIG->SYSCLK_SEL); + while((CMSDK_SYSCON->CLK_CFG >> 2 ) & 0x1); + //3 基于系统时钟源的频率设置分频系数 + CMSDK_SYSCON->CLK_CFG |= (CLOCKCONFIG->ENS1_AHB_PCLK_DIV_x << 8); + CMSDK_SYSCON->CLK_CFG |= (CLOCKCONFIG->ENS1_APB_PCLK_DIV_x << 12); + if(CLOCKCONFIG->ENS1_AHB_PCLK_DIV_x > 0) + clockfreq = (uint32_t)(clockfreq / pow(2,CLOCKCONFIG->ENS1_AHB_PCLK_DIV_x-3)); + if(CLOCKCONFIG->ENS1_APB_PCLK_DIV_x > 0) + clockfreq = (uint32_t)(clockfreq / pow(2,CLOCKCONFIG->ENS1_APB_PCLK_DIV_x-3)); + return clockfreq; //返回时钟频率（分频后的APB上的时钟频率） +} + +void ClockInit(void) +{ + APB_Clock_Freq = ClockInitSet(&CLOCKCFG); + CMSDK_SYSCON->APB_CLKEN = 0; +} + +//PCLK时钟使能 +uint8_t PCLK_Enable(uint8_t APB_CLKEN_POS) +{ + CMSDK_SYSCON->APB_CLKEN |= (0x1 << APB_CLKEN_POS); + return 0; +} + +//PCLK时钟关闭 +uint8_t PCLK_Disable(uint8_t APB_CLKEN_POS) +{ + CMSDK_SYSCON->APB_CLKEN &=~ (0x1 << APB_CLKEN_POS); + return 0; +} +//配置外部晶振，配置前请保留足够延时，否则无法二次烧录程序 +void HSE_ClockInit(uint32_t Clock_Freq) +{ + CMSDK_GPIO->IE = (CMSDK_GPIO->IE & ~(0x01ul << 0)) | (0x01 << 0); + CMSDK_GPIO->ALTFL = (CMSDK_GPIO->ALTFL & ~(0x03ul << 0)) | (0x02 << 0); + CMSDK_SYSCON->CLK_CFG = (CMSDK_SYSCON->CLK_CFG & ~CMSDK_SYSCON_SYSCLK_SEL_Msk) | (0x1 << CMSDK_SYSCON_SYSCLK_SEL_Pos); + while (((CMSDK_SYSCON->CLK_CFG & CMSDK_SYSCON_SYSCLK_SWSTS_Msk) >> CMSDK_SYSCON_SYSCLK_SWSTS_Pos) != 0x01) { } + CMSDK_SYSCON->HSI_CTRL = (CMSDK_SYSCON->HSI_CTRL & ~CMSDK_SYSCON_HSI_EN_Msk); + APB_Clock_Freq = Clock_Freq;//外部时钟频率 +} diff --git a/FWLIB/source/ENS1_EXTI.c b/FWLIB/source/ENS1_EXTI.c new file mode 100644 index 0000000..6a2044f --- /dev/null +++ b/FWLIB/source/ENS1_EXTI.c @@ -0,0 +1,81 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_EXTI.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + + +#include "ENS1_EXTI.h" + + +/*每一位在相应的线路上使能/失能事件或中断的上升沿触发 0-29*/ +void EXTI_RisingTriggerSelect(EXTI_NUM NUM , FunctionalState newstate) +{ + if(newstate == ENABLE) + CMSDK_EXTI->RTSR |= (1<RTSR &=~ (1<FTSR |= (1<FTSR &=~ (1<SWIER |= (1<RISE_PEND_STS >> NUM ) & 0x1); +} +//清除上升沿触发状态 +void Clear_EXTI_RisingEdgePending(EXTI_NUM NUM) +{ + CMSDK_EXTI->RISE_PEND_CLR |= (1<FALL_PEND_STS >> NUM) & 0x1); +} +//清除下降沿触发状态 +void Clear_EXTI_FallingEdgePending(EXTI_NUM NUM) +{ + CMSDK_EXTI->FALL_PEND_CLR |= (1<31) + return ; + CMSDK_EXTI->IMR |= (1<31) + return ; + CMSDK_EXTI->EMR |= (1<15) + { + CMSDK_GPIO->ALTFH &=~ (0x3 << ((GPIO_X-16)*2)); + CMSDK_GPIO->ALTFH |= (GPIO_AltFuncSelx << ((GPIO_X-16)*2)); + } + else + { + CMSDK_GPIO->ALTFL &=~ (0x3 << (GPIO_X*2) ); + CMSDK_GPIO->ALTFL |= (GPIO_AltFuncSelx << (GPIO_X*2)); + } + return 0; +} + +int8_t GPIO_IO_Init(GPIO_NUM GPIO_X, I_O_SELECT INorOUT ,GPIOOType_TypeDef GPIO_OType,GPIO_PUPD_TypeDef GPIO_PUPD,OUTPUT_SPEED_TypeDef OUTPUT_SPEED,OUTPUT_PDRV_TypeDef OUTPUT_PDRV,FunctionalState ENABLEorNOT){ + //??GPIO?????? + GPIO_AltFunction(GPIO_X,ALT_FUNC0); + //???????? + if(INorOUT == INPUT && ENABLEorNOT ==ENABLE) + { + CMSDK_GPIO->OE &=~ (1<IE |= (1<OE &=~ (1<IE &=~ (1<IE &=~ (1<OE |= (1<SL = OUTPUT_SPEED; + //????????? + CMSDK_GPIO->ODEN = GPIO_OType; + } + else if(INorOUT == OUTPUT && ENABLEorNOT == DISABLE) + { + CMSDK_GPIO->OE &=~ (1<IE &=~ (1<PU &= ~(0x01 << GPIO_X); //???? + CMSDK_GPIO->PD &= ~(0x01 << GPIO_X); //???? + } + else if(GPIO_PUPD==GPIO_PU) + { + CMSDK_GPIO->PU |= (0x01 << GPIO_X); //?? + CMSDK_GPIO->PD &= ~(0x01 << GPIO_X); //???? + } + else if(GPIO_PUPD==GPIO_PD) + { + CMSDK_GPIO->PU &= ~(0x01 << GPIO_X); //???? + CMSDK_GPIO->PD |= (0x01 << GPIO_X); //?? + } + //?????? + CMSDK_GPIO->OPDRV0 &=~( 0x01 << (GPIO_X)); + CMSDK_GPIO->OPDRV0 |= (OUTPUT_PDRV & 0x01) << (GPIO_X); + CMSDK_GPIO->OPDRV1 &=~( 0x01 << (GPIO_X)); + CMSDK_GPIO->OPDRV1 |= ((OUTPUT_PDRV >>1)&0x01) << (GPIO_X); + // + return 0; +} +//IO鍙ｈ緭鍏ヨ緭鍑鸿缃,褰㈠弬1锛歡pio鍙凤紝褰㈠弬2锛氳緭鍏ヨ緭鍑洪夋嫨 锛屽舰鍙3锛氫娇鑳戒笌鍚 +int8_t GPIO_IO_Select(GPIO_NUM GPIO_X, I_O_SELECT INorOUT ,FunctionalState ENABLEorNOT){ + if(INorOUT == INPUT && ENABLEorNOT ==ENABLE) + { + CMSDK_GPIO->OE &=~ (1<IE |= (1<OE &=~ (1<IE &=~ (1<IE &=~ (1<OE |= (1<OE &=~ (1<IE &=~ (1<DATAIN & (1<>GPIO_X); +} + +//璇诲彇IO鍙ｈ緭鍑虹姸鎬 +uint8_t GPIO_GetOutputValue(GPIO_NUM GPIO_X){ + return (uint8_t)((CMSDK_GPIO->DATAOUT & (1<>GPIO_X); +} + +//璁剧疆杈撳嚭鐢靛钩涓洪珮鎴栦綆 +void GPIO_Output(GPIO_NUM GPIO_X,LEVELStatus HIGHorLOW){ + if(HIGHorLOW == HIGH_LEVEL) + { + CMSDK_GPIO->DATAOUT |= (1<DATAOUT &=~ (1<DATAOUT |= (1<DATAOUT &=~ (1<ANAEN |= (1 << GPIO_X); + else if(ENABLEorNOT == DISABLE) + CMSDK_GPIO->ANAEN &=~ (1 << GPIO_X); + else + return ; +} + + + + diff --git a/FWLIB/source/ENS1_IIC.c b/FWLIB/source/ENS1_IIC.c new file mode 100644 index 0000000..91e312a --- /dev/null +++ b/FWLIB/source/ENS1_IIC.c @@ -0,0 +1,361 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_I2C.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#include "ENS1_IIC.h" + +IIC_ConfigStructure IIC0_Config = +{ + .MODE = IIC_SLAVE , + .OWN_ADDRESS = 0x78 , + .ACK_EN = true , + .IIC_SPEED = IIC_STARDARD_MODE_10K , +}; + +IIC_ConfigStructure IIC1_Config = +{ + .MODE = IIC_SLAVE , + .OWN_ADDRESS = 0x78 , + .ACK_EN = true , + .IIC_SPEED = IIC_STARDARD_MODE_10K , +}; + + +//bus error 判断（ITERREN使能） +bool IIC_BUS_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 8)&0x1) ? true :false);} +//应答错误判断 +bool IIC_ACK_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 10)&0x1) ? true :false);} +//仲裁 +bool IIC_ARBITRAT_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 9)&0x1) ? true :false);} +//溢出/下溢错误 +bool IIC_OVERRUN_ERROR(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 11)&0x1) ? true :false);} + +//ITEVFEN使能后有如下事件 +//起始状态，起始位发送（主机模式） +bool IIC_SB_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS)&0x1) ? true :false);} +//地址发送（主机模式） / 地址匹配（从机事件） +bool IIC_ADDR_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 1)&0x1) ? true :false);} +//主机模式下，主机已发送10bit地址数据的第一个字节！！！ +bool IIC_ADD10_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 3)&0x1) ? true :false);} +//从机模式下，停止条件被接收到 +bool IIC_STOPF_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 4)&0x1) ? true :false);} +//数据字节传输成功 +bool IIC_BTF_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 2)&0x1) ? true :false);} + +//ITEVFEN 且 ITBUFEN 使能后，有如下事件 +//数据寄存器非空（接受器读到数据） +bool IIC_RxNE_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 5)&0x1) ? true :false);} +//数据寄存器空（传输完数据） +bool IIC_TxE_EVENT(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 6)&0x1) ? true :false);} + +//总线状态：繁忙与否 +uint8_t IIC_Bus_BUSY(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (uint8_t)(((CMSDK_I2Cx->I2C_STS >> 13)&0x1) ? 1 :0);}; + +//模式确认 +bool IIC_MASTER_MODE(CMSDK_I2C_TypeDef* CMSDK_I2Cx){return (bool)(((CMSDK_I2Cx->I2C_STS >> 12)&0x1) ? true :false);} + +uint8_t IIC_Config_init(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,IIC_ConfigStructure* IIC_Para ) +{ + if(CMSDK_I2Cx == CMSDK_I2C0) + { + GPIO_AltFunction(GPIO_6 , ALT_FUNC1); + GPIO_AltFunction(GPIO_7 , ALT_FUNC1); + } + else if(CMSDK_I2Cx == CMSDK_I2C1) + { + GPIO_AltFunction(GPIO_8 , ALT_FUNC2); + GPIO_AltFunction(GPIO_9 , ALT_FUNC2); + } + if(IIC_Para->MODE == IIC_SLAVE) + { + // CMSDK_I2Cx->I2C_CR2|=(1<<7);//|(1<<8);//中断使能--bit8：buffer中断 / bit7：事件中断 / bit6：错误中断 + CMSDK_I2Cx->I2C_CR1|=(1); + CMSDK_I2Cx->I2C_OAR = IIC_Para->OWN_ADDRESS ; + if(IIC_Para->ACK_EN == true) + CMSDK_I2Cx->I2C_CR1 |= (1<<5); + } + else + { + /* + IIC master transmitter: + IIC_CR2:配置中断时钟频率 + IIC_CR1:使能IIC接口 + IIC_CR1:配置START 位 IIC主机 + */ + CMSDK_I2Cx->I2C_CR2 |= IIC_Para->IIC_SPEED ; + CMSDK_I2Cx->I2C_CR1 |= (1) ; + CMSDK_I2Cx->I2C_OAR = IIC_Para->OWN_ADDRESS ; + if(IIC_Para->ACK_EN == true) + CMSDK_I2Cx->I2C_CR1 |= (1<<5); + } + return 0; +} + +void IIC_ITConfig(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,uint16_t IIC_IT_SEL ,FunctionalState NewState) +{ + if(CMSDK_I2Cx == CMSDK_I2C1){ + CMSDK_I2C1->I2C_CR2 |= IIC_IT_SEL; + NVIC_DisableIRQ(I2C1_Event_IRQn); + NVIC_ClearPendingIRQ(I2C1_Event_IRQn); + NVIC_DisableIRQ(I2C1_Error_IRQn); + NVIC_ClearPendingIRQ(I2C1_Error_IRQn); + if(NewState == ENABLE) + NVIC_EnableIRQ(I2C1_Event_IRQn); + } + else if(CMSDK_I2Cx == CMSDK_I2C0){ + CMSDK_I2C0->I2C_CR2 |= IIC_IT_SEL; + NVIC_DisableIRQ(I2C0_Event_IRQn); + NVIC_ClearPendingIRQ(I2C0_Event_IRQn); + NVIC_DisableIRQ(I2C0_Error_IRQn); + NVIC_ClearPendingIRQ(I2C0_Error_IRQn); + if(NewState == ENABLE) + NVIC_EnableIRQ(I2C0_Event_IRQn); + } +} + +void IIC_Cmd(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,FunctionalState NewState) //使能IIC外设 +{ + if(CMSDK_I2Cx ==CMSDK_I2C0) + { + PCLK_Enable(I2C0_PCLK_EN); + } + else if(CMSDK_I2Cx ==CMSDK_I2C1) + { + PCLK_Enable(I2C1_PCLK_EN); + } + else + { + + } + + if(NewState == ENABLE) + CMSDK_I2Cx->I2C_CR1 |= (1); + else + CMSDK_I2Cx->I2C_CR1 &=~ (1); +} + +void IIC_GenerateSTART(CMSDK_I2C_TypeDef* CMSDK_I2Cx) +{ + while(IIC_Bus_BUSY(CMSDK_I2Cx)); + CMSDK_I2Cx->I2C_CR1 |= (1<<3); +} + +void IIC_GenerateSTOP(CMSDK_I2C_TypeDef* CMSDK_I2Cx) +{ + CMSDK_I2Cx->I2C_CR1 |= (1<<4); +} + +//general call 用于向总线所有设备发送消息，用于初始化从设备与设备同步 +//主设备通过向总线发送0x00地址来触发GENERAL CALL +void IIC_GeneralCallCmd(CMSDK_I2C_TypeDef* CMSDK_I2Cx) +{ + +} + +void IIC_Send7bitAddress(CMSDK_I2C_TypeDef* CMSDK_I2Cx ,uint8_t Address) +{ + CMSDK_I2Cx->I2C_DR = Address ; +} + +void IIC_SendData(CMSDK_I2C_TypeDef* CMSDK_I2Cx , uint8_t data) +{ + CMSDK_I2Cx->I2C_DR = data; + while(IIC_BTF_EVENT(CMSDK_I2Cx) == false); //字节传输完成 +} + +uint8_t IIC_ReadData(CMSDK_I2C_TypeDef* CMSDK_I2Cx) +{ + return CMSDK_I2Cx->I2C_DR; +} + + + +void I2C0_Event_Handler(void) +{ + NVIC_ClearPendingIRQ(I2C0_Event_IRQn); + if(IIC_MASTER_MODE(CMSDK_I2C0) == TRUE) + { + if(IIC_SB_EVENT(CMSDK_I2C0) == true ) + { + return ; + } + + if(IIC_ADDR_EVENT(CMSDK_I2C0) == true ) + { + return ; + } + + if(IIC_ADD10_EVENT(CMSDK_I2C0) == true) + { + return; + } + } + + else + { + if(IIC_ADDR_EVENT(CMSDK_I2C0) == true) + { + return ; + } + if(IIC_STOPF_EVENT(CMSDK_I2C0) == true) + { + //如果不再接收，则关闭IIC!!! + IIC_Cmd(CMSDK_I2C0 ,DISABLE) ; + CMSDK_I2C0->I2C_CR2|=(1<<7); //中断使能--bit8：buffer中断 / bit7：事件中断 / bit6：错误中断 + CMSDK_I2C0->I2C_CR1|=(1); + CMSDK_I2C0->I2C_OAR = 0X78 ; + CMSDK_I2C0->I2C_CR1 |= (1<<5); + IIC_Cmd(CMSDK_I2C0 ,ENABLE) ; + return ; + } + } + + if(IIC_BTF_EVENT(CMSDK_I2C0) == true) + { + + } + + if(IIC_RxNE_EVENT(CMSDK_I2C0) == true) + { + uint8_t read_data = (uint8_t)(CMSDK_I2C0->I2C_DR & 0xff); + printf("%d\n", read_data); + } + + if(IIC_TxE_EVENT(CMSDK_I2C0) == true) + { + + } + return ; +} + +void I2C0_Error_Handler(void) +{ + NVIC_ClearPendingIRQ(I2C0_Error_IRQn); + + if(IIC_BUS_ERROR(CMSDK_I2C0) == true) + { + printf("bus error\n"); + return ; + } + + if(IIC_ACK_ERROR(CMSDK_I2C0) == true) + { + printf("IIC_ACK_ERROR\n"); + return ; + } + + if(IIC_ARBITRAT_ERROR(CMSDK_I2C0) == true) + { + printf("IIC_ARBITRAT_ERROR\n"); + return ; + } + + if(IIC_OVERRUN_ERROR(CMSDK_I2C0) == true) + { + printf("IIC_OVERRUN_ERROR\n"); + return ; + } + +} + + +void I2C1_Event_Handler(void) +{ + NVIC_ClearPendingIRQ(I2C1_Event_IRQn); + if(IIC_MASTER_MODE(CMSDK_I2C1) == TRUE) + { + if(IIC_SB_EVENT(CMSDK_I2C1) == true ) + { + return ; + } + + if(IIC_ADDR_EVENT(CMSDK_I2C1) == true ) + { + return; + } + + if(IIC_ADD10_EVENT(CMSDK_I2C1) == true) + { + return; + } + } + else + { + if(IIC_ADDR_EVENT(CMSDK_I2C1) == true) //作为从机，进入此处则地址匹配！ + { + return ; + } + + if(IIC_STOPF_EVENT(CMSDK_I2C1) == true) //作为从机，接收到STOP信号 + { + printf("get stop\n"); + //如果不再接收，则关闭IIC!!! + IIC_Cmd(CMSDK_I2C1 ,DISABLE) ; + CMSDK_I2C1->I2C_CR2|=(1<<7); //中断使能--bit8：buffer中断 / bit7：事件中断 / bit6：错误中断 + CMSDK_I2C1->I2C_CR1|=(1); + CMSDK_I2C1->I2C_OAR = 0X78 ; + CMSDK_I2C1->I2C_CR1 |= (1<<5); + IIC_Cmd(CMSDK_I2C1 ,ENABLE) ; + IIC_ITConfig(CMSDK_I2C0,0 ,DISABLE); + IIC_ITConfig(CMSDK_I2C0,0 ,ENABLE); + return ; + } + } + if(IIC_BTF_EVENT(CMSDK_I2C1) == true) + { + + } + if((IIC_RxNE_EVENT(CMSDK_I2C1) == true)) //作为从机，buffer非空，读IIC_DR中的数据 + { + uint8_t read_data = (uint8_t)(CMSDK_I2C1->I2C_DR & 0xff); + printf("%d\n", read_data); + } + if(IIC_TxE_EVENT(CMSDK_I2C1) == true) + { + + } + return ; +} + +void I2C1_Error_Handler(void) +{ + NVIC_ClearPendingIRQ(I2C1_Error_IRQn); + + if(IIC_BUS_ERROR(CMSDK_I2C1) == true) + { + printf("bus error\n"); + return ; + } + + if(IIC_ACK_ERROR(CMSDK_I2C1) == true) + { + printf("IIC_ACK_ERROR\n"); + return ; + } + + if(IIC_ARBITRAT_ERROR(CMSDK_I2C1) == true) + { + printf("IIC_ARBITRAT_ERROR\n"); + return ; + } + + if(IIC_OVERRUN_ERROR(CMSDK_I2C1) == true) + { + printf("IIC_OVERRUN_ERROR\n"); + return ; + } + +} + diff --git a/FWLIB/source/ENS1_MTP.c b/FWLIB/source/ENS1_MTP.c new file mode 100644 index 0000000..063f4cd --- /dev/null +++ b/FWLIB/source/ENS1_MTP.c @@ -0,0 +1,90 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_MTP.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: +1.V1.0 +Date: +Author: +Modification: 初版 +*/ + + +/* +MTP说明 +1、MTP部分只能按块写入,每块有1024字节大小 +块的编号： +SECTOR 0 : 0000H - 03FFH +SECTOR 1 : 0400H - 07FFH +SECTOR 2 : 0800H - 0BFFH +SECTOR 3 : 0C00H - 0FFFH +SECTOR 4 : 1000H - 13FFH +SECTOR 5 : 1400H - 17FFH +SECTOR 6 : 1800H - 1BFFH +SECTOR 7 : 1C00H - 1FFFH +*/ + +#include "ENS1_MTP.h" + +uint16_t write_current_data[4]={0,0,0,0}; +STRUCT_MTP_TRIM MTP_FT_SET= +{ + .OSCA_FT = 0x10, //默认值为 0X10 + .OSC32K_RTRIM = 0x10, //默认值为 0X10 + .BG_TRIM = 0x88, + +}; + +uint8_t MTP_init(void) +{ + #ifdef ENS1_HSI_16MHz + CMSDK_MTPREG->MTP_CR = 0x00000001; + #elif ENS1_HSI_32MHz + CMSDK_MTPREG->MTP_CR = 0x00000003; + #endif + return 0; +} + + + +//MTP内保存的电流检测数据读取 +void flash_read(uint32_t start_addr,uint16_t *test_i){ + uint16_t result = 0; + result = HW16_REG(start_addr); + *test_i = result ; +} + +//向MTP中写入数据（仅限于向用户自定义块写入！！！） +//可自定义读写的区域为MTP的第0x1BC0块（MTP_BASE_ADDR + 0x6F00） +int8_t flash_buff_write(uint32_t start_addr, uint16_t *buff) { + HW32_REG(start_addr) = ((uint32_t)((*(buff+1)<<16)&0xffff0000) + ((*buff)&0x0000ffff)); +// while(!(CMSDK_MTPREG->MTP_SR&0x00000002)){}; + if(HW32_REG(start_addr) != ((uint32_t)(*(buff+1)<<16) + *buff )) + { + printf("write error\n"); + return -1; + } + return 0; +} + +int8_t flash_write_ctrl(uint16_t *buff , uint32_t start_addr){ + CMSDK_MTPREG->MTP_CLR = 0xffffffff; //SR寄存器 + CMSDK_MTPREG->MTP_CR = 0x00000002; //2等待周期 + CMSDK_MTPREG->MTP_ACLR = 0x00000000; //允许软件读写从sector0 -sector 6 （sector7 作为bootloader区） + CMSDK_MTPREG->MTP_KEYR = 0x5a5a5a5a; //key + return flash_buff_write(start_addr, buff); +} + +int8_t write_data(void){ + uint16_t *wr_data = (uint16_t *)malloc(8*sizeof(uint8_t)); + memcpy(wr_data , write_current_data, 8); + int8_t val = flash_write_ctrl(wr_data,DATA_SAVE_ADDR); //第 0x1BC0块 + val = flash_write_ctrl(wr_data+2, DATA_SAVE_ADDR + 4); + return val; +} + diff --git a/FWLIB/source/ENS1_PWM.c b/FWLIB/source/ENS1_PWM.c new file mode 100644 index 0000000..cbc9f7d --- /dev/null +++ b/FWLIB/source/ENS1_PWM.c @@ -0,0 +1,166 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_PWM.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#include "ens1_pwm.h" +//PWMx 选择PWM输出通道 +//edge_mode pwm边沿模式 默认单边 +//pulse_duty 占空比 0-100 （有些偏差） +//freq_HZ 频率 单位 HZ +//pwmEnable 使能输出 +void PWM_init(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue* PWM_Para , bool pwmEnable) +{ + if(PWMx > 6 || PWMx < 1) + PWMx = IO16_PWM1; + int pwmsel = PWMx-2; + if(pwmsel<0) + pwmsel = 0; + if(PWM_Para->pwm_Duty_cycle>100) + PWM_Para->pwm_Duty_cycle=100; + //IO复用 + CMSDK_GPIO->ALTFH |= (0x01 << ((PWMx-1)*2)); + uint32_t pulse_width = (uint32_t)((uint8_t)APB_Clock_Freq / ((PRESCALE_PWM+1) * (PWM_Para->pwm_freq))); + CMSDK_PWM->MR0 = pulse_width; + /*模式： 1 单边模式 2 双边正脉冲 3 双边负脉冲*/ + if(PWM_Para->mode == pwm_single_mode) + { + //pwm通道1-6的某一个通道的计数值填充 + *(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(PWM_Para->pwm_Duty_cycle*CMSDK_PWM->MR0/100); + } + else if(PWM_Para->mode == pwm_double_positive_mode) + { + //pwm通道1-6的某一个通道的计数值填充 + CMSDK_PWM->PCR |= (1< 1) //仅允许使用2-6 + { + *(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx-1))=(uint32_t)(0); + *(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)(PWM_Para->pwm_Duty_cycle*pulse_width/100); + } + } + else + { + CMSDK_PWM->PCR |= (1<1) //仅允许使用2-6 + { + *(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx-1))=(uint32_t)(pulse_width); + *(unsigned long*)(CMSDK_PWM_BASE + 0x018 + 0x4*(PWMx))=(uint32_t)((100-PWM_Para->pwm_Duty_cycle)*pulse_width/100); + } + } + + CMSDK_PWM->PR = PRESCALE_PWM;//Prescale + CMSDK_PWM->LER |= (1)|(1<TCR |= (1<<1); //计数使能 + CMSDK_PWM->MCR |= (1<<1) ; //中断不使能和复位使能| ((PWMx*3+1)<<1) + if(pwmEnable == true) + CMSDK_PWM->PCR |= (0x01 << (PWMx+4)); + else + CMSDK_PWM->PCR &=~ (0x01 << (PWMx+4)); +} + +void PWM_SetFreq(ENS1_PWM_CHANNEL PWMx , PWM_ParaStructrue * PWM_Para ) +{ + CMSDK_PWM->MR0 = (uint32_t)((uint8_t)APB_Clock_Freq/ ((PRESCALE_PWM+1) * (PWM_Para->pwm_freq))); +} + +void PWM_SetDutyCycle_SingleMode(ENS1_PWM_CHANNEL PWMx ,uint8_t DutyCycle) //设置占空比 +{ + PWM_OutputDisable(PWMx); + CMSDK_PWM->LER &=~ (1<MR0/100); + CMSDK_PWM->LER |= (1<LER &=~ (1<MR0/100); + CMSDK_PWM->LER |= (1<LER &=~ (1<MR0/100); + CMSDK_PWM->LER |= (1<PCR &=~ (0x01 << (PWMx+4)); +} + +void PWM_OutputEnable(ENS1_PWM_CHANNEL PWMx) +{ + CMSDK_PWM->PCR |= (0x01 << (PWMx+4)); +} + +uint32_t pwm_irq_occurred_mr[7]; +void PWM_Handler(void) { +//MR0 status interrupt + if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR0_INT_STS_Msk)==CMSDK_PWM_MR0_INT_STS_Msk) { + CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR0_INT_STS_Msk;//Clear Interrupt + pwm_irq_occurred_mr[0]++; + } +//MR1 status interrupt + if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR1_INT_STS_Msk)==CMSDK_PWM_MR1_INT_STS_Msk) { + CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR1_INT_STS_Msk;//Clear Interrupt + pwm_irq_occurred_mr[1]++; + } +//MR2 status interrupt + if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR2_INT_STS_Msk)==CMSDK_PWM_MR2_INT_STS_Msk) { + CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR2_INT_STS_Msk;//Clear Interrupt + pwm_irq_occurred_mr[2]++; + } +//MR3 status interrupt + if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR3_INT_STS_Msk)==CMSDK_PWM_MR3_INT_STS_Msk) { + CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR3_INT_STS_Msk;//Clear Interrupt + pwm_irq_occurred_mr[3]++; + } +//MR4 status interrupt + if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR4_INT_STS_Msk)==CMSDK_PWM_MR4_INT_STS_Msk) { + CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR4_INT_STS_Msk;//Clear Interrupt + pwm_irq_occurred_mr[4]++; + } +//MR5 status interrupt + if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR5_INT_STS_Msk)==CMSDK_PWM_MR5_INT_STS_Msk) { + CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR5_INT_STS_Msk;//Clear Interrupt + pwm_irq_occurred_mr[5]++; + } +//MR6 status interrupt + if((CMSDK_PWM->INTSTATUS & CMSDK_PWM_MR6_INT_STS_Msk)==CMSDK_PWM_MR6_INT_STS_Msk) { + CMSDK_PWM->INTCLEAR = CMSDK_PWM_MR6_INT_STS_Msk;//Clear Interrupt + pwm_irq_occurred_mr[6]++; + } +} + diff --git a/FWLIB/source/ENS1_SPI.c b/FWLIB/source/ENS1_SPI.c new file mode 100644 index 0000000..3a5a167 --- /dev/null +++ b/FWLIB/source/ENS1_SPI.c @@ -0,0 +1,380 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_SPI.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#include "ENS1_SPI.h" +#include "ENS1_GPIO.h" +/*---------------------------------------------------fifo相关的函数头--------------------------------------------------*/ +/*清除FIFO和计数清0*/ +uint8_t CLR_TX_FIFO( CMSDK_SPI_TypeDef* SPIx) +{ + return (uint8_t)(SPIx->FCR>>8 & 0x1); +} + +uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx) +{ + return (uint8_t)(SPIx->FCR>>1 & 0x1); +} +/*FIFO 状态读取*/ +uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx) +{ + return (uint8_t)(((SPIx->FCR & 0x1) == 0x1) ? ((uint8_t)((SPIx->FSR & 0x001f0000)>>16)):0); //读取当前接收FIFO数据长度 +} + +uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx) +{ + return (uint8_t)(((SPIx->FCR & 0x1) == 0x1) ? ((uint8_t)((SPIx->FSR & 0x00001f00)>>8)):0); //读取当前发送FIFO数据长度 +} + +SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx) +{ + return (SPI_BUSY_STATE)((((SPIx->FSR & 0x10) >> 4)==1) ? ( BUSY ) : ( NOTBUSY )); //读取当前SPI是否繁忙 +} + +uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) +{ + return (uint8_t)((((SPIx->FSR & 0x8)>> 3 )==1) ? (1) : (0)) ; //当前读取FIFO是否为满？ +} + +uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) +{ + return (uint8_t)((((SPIx->FSR & 0x4) >> 2)==1) ? (1) : (0) ) ; //当前读取FIFO是否为空？ +} + +uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) +{ + return (uint8_t)((((SPIx->FSR & 0x2) >> 1)==1) ? (1) : (0)) ; //当前发送FIFO是否为满？ +} + +uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) +{ + return (uint8_t)(((SPIx->FSR & 0x1)==1) ? (1) : (0)) ; //当前发送FIFO是否为空？ +} + + + + +/*FIFO使能/DMA使能*/ +uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx) //读FIFO设置 +{ + return (uint8_t)(SPIx->FCR & 0x1) ; +} +uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx ) +{ + SPIx->FCR |= 0x1; + return 0;//(uint8_t)(SPIx->FCR & 0x1) ; +} + +uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx ) +{ + SPIx->FCR &=~ 0x1; + return (uint8_t)(SPIx->FCR & 0x1) ; +} + +uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET) +{ + if(TXDMA_SET == true) + SPIx->CTRL2 |= (1<<5); + else if(TXDMA_SET == false) + SPIx->CTRL2 &=~ (1<<5); + + if(TXDMA_SET == true) + SPIx->CTRL2 |= (1<<4); + else if(TXDMA_SET == false) + SPIx->CTRL2 &=~ (1<<4); + return (uint8_t)((SPIx->CTRL2>>4)&0x3); +} + +/*------------------------------------------------------fifo相关的函数尾--------------------------------------------------*/ + +/*----------------------------------------------------------SPI配置-------------------------------------------------------*/ +//读取当前的SPI模式 +uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx) +{ + return ((SPIx->CTRL1 & 0x7000) >> 12); +} + +//NSS通道选择 +uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS) +{ + if(ENorDIS == ENABLE) + SPIx->CTRL2 |= ( 1 << NSSx ); + else + SPIx->CTRL2 &=~ ( 1 << NSSx); + + return (uint8_t)((SPIx->CTRL2 & 0x0f00) >> 8); +} + +//spi的参数配置 +uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , + struct SPI_ModeConfig_Struct SPI_Config, + struct SPI_FIFO_Struct FIFO_Struct) +{ +/*1、GPIO ALTER*/ + if(SPIx == CMSDK_SPI1) + { + + + GPIO_AltFunction(GPIO_16 , ALT_FUNC2); + GPIO_AltFunction(GPIO_17 , ALT_FUNC2); + GPIO_AltFunction(GPIO_18 , ALT_FUNC2); + GPIO_AltFunction(GPIO_19 , ALT_FUNC2); + + } + else if(SPIx == CMSDK_SPI0) + { + + + GPIO_AltFunction(GPIO_8, ALT_FUNC1); + GPIO_AltFunction(GPIO_9, ALT_FUNC1); + GPIO_AltFunction(GPIO_10,ALT_FUNC1); + GPIO_AltFunction(GPIO_11,ALT_FUNC1); + } + +/* + 2、写SPI_CTRL1寄存器 + （1）配置时钟波特率BAUD_RATE[2:0] + （2）配置时钟极性和相位 CPOL and CPHA bits + （3）选择传输模式 BIDI_EN, BIDI_MODE, UNIDI_MODE bits + （4）配置LSB_SEL位来定义帧格式 + （5）通过配置NSS_TOGGLE、NSS_MST_CTRL、NSS_MST_SW bits来选择NSS控制方式 bit11 9 8 + （6）通过配置MST_SLV_SEL位选择主模式或从模式 +*/ + SPIx->CTRL1 = (SPIx->CTRL1&~ 0xffff) | ( SPI_Config.BAUD_FPCLKdivx << 4); + SPIx->CTRL1 |= (SPI_Config.SPI_MODE << 2); + SPIx->CTRL1 |= (SPI_Config.SPI_TRANS_MODE << 12 ); + SPIx->CTRL1 &=~ (0x1 << 7); //帧格式默认大端模式 + SPIx->CTRL1 &=~ (0x1 << 8); //帧格式默认大端模式 + SPIx->CTRL1 &=~ (1 << 11); + SPIx->CTRL1 |= (1 << 11) ; // 默认硬件生成NSS + + if(SPI_Config.MS_SEL == MASTER) + { + SPIx->CTRL1 |= (1<<1); + } + else + { + SPIx->CTRL1 &=~ (1<<1); + } +/* + 3、写SPI_CTRL2寄存器 + （1）配置CHAR_LEN[3:0]位来选择传输的数据长度 + （2）选择“NSS端口” NSS0_EN, NSS1_EN, NSS2_EN + （3）通过配置主机选择合适的RX数据采集阶段 SAMP_PHASE(1:0)位 + （4）通过配置C2T_DELAY和T2C_DELAY位，可以根据从设备的需求选择合适的C2T/T2C延迟 + （5）通过配置TXDMA_EN和RXDMA_EN位使能或使能FIFO模式的TX/RX DMA。 +*/ + SPIx->CTRL2 = (SPIx->CTRL2&~ 0xffff); + if(SPI_Config.CHAR_LEN < 4) + { + + } + else if((SPI_Config.CHAR_LEN >= 4) && (SPI_Config.CHAR_LEN < 17)) + { + SPIx->CTRL2 |= (SPI_Config.CHAR_LEN -1); + } + else + { + + } + SPI_NSS_CHANNEL(SPIx ,SPI_Config.NSSx ,ENABLE); + //rx读采集相位， 仅仅在主模式下有效，默认选normal + //C2T_DELAY ,仅在主模式下有效 + //T2C_DELAY, 仅在主模式下有效 + if(SPI_Config.MS_SEL == MASTER) + { + SPIx->CTRL2 |= (SPI_Config.SAMP_PHASE << 6); + //T2C 是Transmit-end-to-chip-inactive 的延迟时间，默认为1T SCK + //C2T 是Chip-select-active-to-transmit-start 的时间 默认1T SCK ,这里对这两参数没做设置 + } + + +/* + 4、写FIFO 寄存器 + （1）配置TX_FIFO_TH或RX_FIFO_TH来定义触发级别阈值 + （2）通过配置TX_FIFO_CLR和RX_FIFO_CLR位清除TX/RX FIFO + （3）通过配置fif_en位使能或禁用FIFO模式 +*/ + SPIx->FCR |= (FIFO_Struct.TX_FIFO_TH << 9 ); + SPIx->FCR |= (FIFO_Struct.RX_FIFO_TH << 2 ); + CLR_TX_FIFO(SPIx) ; + CLR_RX_FIFO(SPIx) ; + if(FIFO_Struct.FIFO_ENABLE_SET == true) + SPI_FIFO_ENABLE(SPIx); + //SPI_FIFODMA_SET(SPIx ,FIFO_Struct.TXDMA_SET ,FIFO_Struct.RXDMA_SET); + return 0; +} + +/*---------------------------------------------SPI启动和停止-------------------------------------------------*/ +uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx ) +{ + SPIx->CTRL1 |= (1); + return (uint8_t)(SPIx->CTRL1 & 0x1); +} + +uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx) +{ + if((READ_SPI_MODE(SPIx)==(L2_UniDirect_R & 0x7)) || (READ_SPI_MODE(SPIx)==(L1_BiDirect_R & 0x7))) + { + if(SPI_FIFO_STATE(SPIx) == 1) + { + //读 RX的FIFO 直到 FIFO长度为 0 + while((RX_FIFO_LEN(SPIx) != 0) || (BUSY_STATE(SPIx) == BUSY)) + { + //save_data = READ_SPI_RCVBuff(SPIx); + } + SPIx->CTRL1 &=~ (1); + } + else if(SPI_FIFO_STATE(SPIx) == 0) + { + while(BUSY_STATE(SPIx) == BUSY); + SPIx->CTRL1 &=~ (1); + } + } + else + { + if(SPI_FIFO_STATE(SPIx) == 1) + { + while((TX_FIFO_LEN(SPIx)!= 0) || (BUSY_STATE(SPIx) == BUSY)); + SPIx->CTRL1 &=~ (1); + //读 RX的FIFO 直到 FIFO长度为 0 + while(RX_FIFO_LEN(SPIx) != 0) + { + uint16_t save_data = READ_SPI_RCVBuff(SPIx); + } + } + else if(SPI_FIFO_STATE(SPIx) == 0) + { + while(BUSY_STATE(SPIx) == BUSY); + SPIx->CTRL1 &=~ (1); + } + } + return (uint8_t)(SPIx->CTRL1*0x1); +} + +/*-----------------------------------------读 / 写 SPI BUFFER的数据-------------------------------------------------*/ +//读被接收的数据 最多16bits +uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx) +{ + return (uint16_t)(SPIx->RBR & 0xffff); +} + +//写数据 +void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data) +{ + SPIx->THR = data; + while(BUSY_STATE(SPIx) == BUSY); +} + +/*------------------------------------------------------SPI中断------------------------------------------------------*/ +uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET) +{ + NVIC_DisableIRQ(IRQn); + NVIC_ClearPendingIRQ(IRQn); + if(IRQn == SPI0_IRQn) + { + CMSDK_SPI0->IER = ((CMSDK_SPI0->IER &~ (0xff)) | SPI_INT_BIT_SET); + } + else if(IRQn == SPI1_IRQn) + { + CMSDK_SPI1->IER = ((CMSDK_SPI0->IER &~ (0xff)) | SPI_INT_BIT_SET); + } + + if(SPI_INT_ENABLE == true) + { + NVIC_EnableIRQ(IRQn); + } + else + { + NVIC_DisableIRQ(IRQn); + } + return 0; +} + +//中断处理函数 +/* +中断有如下类型： +1、发送部分有 下溢 中断（发送数据没有啦） +2、接收部分有 溢出 中断（接满啦） +3、收发完成中断？ +4、发送缓冲区空 中断 +5、接收缓冲区非空 中断 +*/ +void SPI1_Handler(void) +{ + NVIC_ClearPendingIRQ(SPI1_IRQn); + uint8_t read_fifo=0; + if((CMSDK_SPI1->INTSTATUS & 0x10 )== UNDERRUN_INT) //下溢-发送时发送数据已为空时触发 + { + CMSDK_SPI1->INTCLEAR |= (1<<4); //清除中断 + } + if((CMSDK_SPI1->INTSTATUS & 0x8) ==OVERRUN_INT) + { + CMSDK_SPI1->INTCLEAR |= (1<<3); + } + if((CMSDK_SPI1->INTSTATUS& 0x4) ==CMPL_INT) + { + CMSDK_SPI1->INTCLEAR |= (1<<2); + } + if((CMSDK_SPI1->INTSTATUS &0x2) ==TXE_INT) + { + + } + if((CMSDK_SPI1->INTSTATUS & 1)== RXNE_INT) + { + + while(!RX_FIFO_EMPTY(CMSDK_SPI1)) + { + read_fifo = READ_SPI_RCVBuff(CMSDK_SPI1); + printf("masterrcv:%d\n",read_fifo); + } + } + + +} + +void SPI0_Handler(void) +{ + NVIC_ClearPendingIRQ(SPI0_IRQn); + uint8_t read_fifo=0; + if((CMSDK_SPI0->INTSTATUS & 0x10 )== UNDERRUN_INT) //下溢-发送时发送数据已为空时触发 + { + CMSDK_SPI0->INTCLEAR |= (1<<4); //清除中断 + } + if((CMSDK_SPI0->INTSTATUS & 0x8) ==OVERRUN_INT) + { + CMSDK_SPI0->INTCLEAR |= (1<<3); + } + if((CMSDK_SPI0->INTSTATUS& 0x4) ==CMPL_INT) + { + CMSDK_SPI0->INTCLEAR |= (1<<2); + } + if((CMSDK_SPI0->INTSTATUS &0x2) ==TXE_INT) + { + + } + if((CMSDK_SPI0->INTSTATUS & 1)== RXNE_INT) + { + + while(!RX_FIFO_EMPTY(CMSDK_SPI0)) + { + read_fifo = READ_SPI_RCVBuff(CMSDK_SPI0); + printf("masterrcv:%d\n",read_fifo); + } + } +} + + + diff --git a/FWLIB/source/ENS1_TIMER.c b/FWLIB/source/ENS1_TIMER.c new file mode 100644 index 0000000..e059693 --- /dev/null +++ b/FWLIB/source/ENS1_TIMER.c @@ -0,0 +1,402 @@ +#include "ENS1_TIMER.h" +#include "ENS_CURRENT_CALIBRATION.h" +#include "ENS1_CLOCK.h" + +void TIMER0_Init(uint32_t Int_Period) //形参，输入中断触发周期 （单位ms） +{ + PCLK_Enable(TIMER0_PCLK_EN); + NVIC_DisableIRQ(TIMER0_IRQn); + NVIC_ClearPendingIRQ(TIMER0_IRQn); + CMSDK_timer_Init(CMSDK_TIMER0,(uint32_t)(APB_Clock_Freq / 1000 *Int_Period) , 1); // + NVIC_EnableIRQ(TIMER0_IRQn); +} + +void TIMER1_Init(uint32_t Int_Period) +{ + PCLK_Enable(TIMER1_PCLK_EN); + NVIC_DisableIRQ(TIMER1_IRQn); + NVIC_ClearPendingIRQ(TIMER1_IRQn); + CMSDK_timer_Init(CMSDK_TIMER1,(uint32_t)(APB_Clock_Freq / 1000 * Int_Period) , 1); // 1ms + NVIC_EnableIRQ(TIMER1_IRQn); +} + + + +/*使能定时器中断*/ + void CMSDK_timer_EnableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER) + { + CMSDK_TIMER->CTRL |= CMSDK_TIMER_CTRL_IRQEN_Msk; + } + +/*关闭定时器中断*/ + void CMSDK_timer_DisableIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER) + { + CMSDK_TIMER->CTRL &= ~CMSDK_TIMER_CTRL_IRQEN_Msk; + } + +/*定时器启动*/ + void CMSDK_timer_StartTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER) + { + CMSDK_TIMER->CTRL |= CMSDK_TIMER_CTRL_EN_Msk; + } + +/*定时器关闭*/ + void CMSDK_timer_StopTimer(CMSDK_TIMER_TypeDef *CMSDK_TIMER) + { + CMSDK_TIMER->CTRL &= ~CMSDK_TIMER_CTRL_EN_Msk; + } + +/*获取定时器Value*/ + uint32_t CMSDK_timer_GetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER) + { + return CMSDK_TIMER->VALUE; + } + +/*设置定时器值*/ + void CMSDK_timer_SetValue(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value) + { + CMSDK_TIMER->VALUE = value; + } + +/*获取重载值*/ + uint32_t CMSDK_timer_GetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER) + { + return CMSDK_TIMER->RELOAD; + } + +/*设置重载值*/ + void CMSDK_timer_SetReload(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t value) + { + CMSDK_TIMER->RELOAD = value; + } + + + void CMSDK_timer_ClearIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER) + { + CMSDK_TIMER->INTCLEAR = CMSDK_TIMER_INTCLEAR_Msk; + } + +/*返回定时器状态*/ + uint32_t CMSDK_timer_StatusIRQ(CMSDK_TIMER_TypeDef *CMSDK_TIMER) + { + return CMSDK_TIMER->INTSTATUS; + } + +/*初始化定时器*/ +void CMSDK_timer_Init(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload, uint8_t irq_en) +{ + uint32_t new_ctrl = 0; + CMSDK_TIMER->VALUE = reload; + CMSDK_TIMER->RELOAD = reload; + if (irq_en!=0) + new_ctrl |= CMSDK_TIMER_CTRL_IRQEN_Msk; /* non zero - enable IRQ */ + new_ctrl |= CMSDK_TIMER_CTRL_EN_Msk; /* enable timer */ + CMSDK_TIMER->CTRL = new_ctrl; +} + +/** + * + * @param *CMSDK_TIMER Timer Pointer + * @param reload The value to which the timer is to be set after an underflow has occurred + * @param irq_en Defines whether the timer IRQ is to be enabled + * @return none + * @brief Initialises the timer to use the external clock and specifies the timer reload value and whether IRQ is enabled or not. + */ + +void CMSDK_timer_Init_ExtClock(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,uint32_t irq_en) +{ + CMSDK_TIMER->CTRL = 0; + CMSDK_TIMER->VALUE = reload; + CMSDK_TIMER->RELOAD = reload; + if (irq_en!=0) /* non zero - enable IRQ */ + CMSDK_TIMER->CTRL = (CMSDK_TIMER_CTRL_IRQEN_Msk | + CMSDK_TIMER_CTRL_SELEXTCLK_Msk |CMSDK_TIMER_CTRL_EN_Msk); + else { /* zero - do not enable IRQ */ + CMSDK_TIMER->CTRL = ( CMSDK_TIMER_CTRL_EN_Msk | + CMSDK_TIMER_CTRL_SELEXTCLK_Msk); /* enable timer */ + } + } + +/** + * + * @brief Initialises the timer to use the internal clock but with an external enable. It also specifies the timer reload value and whether IRQ is enabled or not. + * + * @param *CMSDK_TIMER Timer Pointer + * @param reload The value to which the timer is to be set after an underflow has occurred + * @param irq_en Defines whether the timer IRQ is to be enabled + * @return none + * Timer 0 only + * + */ +void CMSDK_timer_Init_ExtEnable(CMSDK_TIMER_TypeDef *CMSDK_TIMER, uint32_t reload,uint32_t irq_en) +{ + CMSDK_TIMER->CTRL = 0; + CMSDK_TIMER->VALUE = reload; + CMSDK_TIMER->RELOAD = reload; + if (irq_en!=0) /* non zero - enable IRQ */ + CMSDK_TIMER->CTRL = (CMSDK_TIMER_CTRL_IRQEN_Msk | CMSDK_TIMER_CTRL_SELEXTEN_Msk | CMSDK_TIMER_CTRL_EN_Msk); + else{ /* zero - do not enable IRQ */ + CMSDK_TIMER->CTRL = ( CMSDK_TIMER_CTRL_EN_Msk | CMSDK_TIMER_CTRL_SELEXTEN_Msk); /* enable timer */ + } +} + + /*DUAL Timer driver functions*/ +/** + * + * @param *CMSDK_DUALTIMER DUAL Timer Pointer + * @return none + * + * @brief Start timer in dual timers. + */ + /* Start Timer */ + void CMSDK_dualtimer_start(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx) + { + CMSDK_DUALTIMERx->TimerControl |= CMSDK_DUALTIMER_CTRL_EN_Msk; + } + +/** + * + * @param *CMSDK_DUALTIMER DUAL Timer Pointer + * @return none + * + * @brief Stop timer in dual timers. + */ + + /* Stop Timer */ + void CMSDK_dualtimer_stop(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx) + { + CMSDK_DUALTIMERx->TimerControl &= ~CMSDK_DUALTIMER_CTRL_EN_Msk; + } + +/** + * + * @param *CMSDK_DUALTIMER DUAL Timer Pointer + * @return none + * + * @brief Clear the interrupt request in dual timers. + */ + + /* Clear the Interrupt */ + void CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx) + { + CMSDK_DUALTIMERx->TimerIntClr = 0; + } + +/** + * + * @param *CMSDK_DUALTIMER DUAL Timer Pointer + * @return none + * + * @brief Setup Free running mode in dual timers. + */ + + /* Free running timer mode */ + void CMSDK_dualtimer_setup_freerunning(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx, + unsigned int cycle, unsigned int prescale, unsigned int interrupt, unsigned int size) + { + int ctrl_val; + CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */ + /* Previous timer activities might have trigger interrupt flag, + so need to clear it */ + CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMERx); + CMSDK_DUALTIMERx->TimerLoad = cycle; + + ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos | + (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos | + (size & 0x1) << CMSDK_DUALTIMER_CTRL_SIZE_Pos | + CMSDK_DUALTIMER_CTRL_EN_Msk; + + CMSDK_DUALTIMERx->TimerControl = ctrl_val; + } + +/** + * + * @param *CMSDK_DUALTIMER DUAL Timer Pointer + * @return none + * + * @brief Setup Periodic mode in dual timers. + */ + + /* Periodic timer mode */ + void CMSDK_dualtimer_setup_periodic(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx, + unsigned int cycle, unsigned int prescale, + unsigned int interrupt, unsigned int size) + { + int ctrl_val; + CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */ + /* Previous timer activities might have trigger interrupt flag, + so need to clear it */ + CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMERx); + CMSDK_DUALTIMERx->TimerLoad = cycle; + + ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos | + (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos | + (size & 0x1) << CMSDK_DUALTIMER_CTRL_SIZE_Pos | + CMSDK_DUALTIMER_CTRL_EN_Msk | + CMSDK_DUALTIMER_CTRL_MODE_Msk; + + CMSDK_DUALTIMERx->TimerControl = ctrl_val; + } + +/** + * + * @param *CMSDK_DUALTIMER DUAL Timer Pointer + * @return none + * + * @brief Setup One shot mode in dual timers. + */ + + /* One shot timer mode */ + void CMSDK_dualtimer_setup_oneshot(CMSDK_DUALTIMER_TypeDef *CMSDK_DUALTIMERx, + unsigned int cycle, unsigned int prescale, + unsigned int interrupt, unsigned int size) + { + int ctrl_val; + CMSDK_DUALTIMERx->TimerControl = 0; /* Disable during programming */ + /* Previous timer activities might have trigger interrupt flag, + so need to clear it */ + CMSDK_dualtimer_irq_clear(CMSDK_DUALTIMERx); + CMSDK_DUALTIMERx->TimerLoad = cycle; + + ctrl_val = (prescale & 0x3) << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos | + (interrupt & 0x1) << CMSDK_DUALTIMER_CTRL_INTEN_Pos | + (size & 0x1) << CMSDK_DUALTIMER_CTRL_SIZE_Pos | + CMSDK_DUALTIMER_CTRL_EN_Msk | + CMSDK_DUALTIMER_CTRL_ONESHOT_Msk; + + CMSDK_DUALTIMERx->TimerControl = ctrl_val; + } + + + /*RTC driver functions*/ + +/** + * + * @param *CMSDK_RTC RTC Pointer + * @return none + * + * @brief Initialize RTC Calender + */ + void CMSDK_RTC_Init_Calender(uint16_t prescaler, uint8_t data_mode, uint8_t hour_mode, + uint32_t init_time, uint32_t init_date) + { + uint32_t new_reg_ctrl = 0; + //wait for rtc prescaler sync ready + while(!((CMSDK_RTC->SR & CMSDK_RTC_PRES_SYNC_READY_Msk) >> CMSDK_RTC_PRES_SYNC_READY_Pos)); + //set prescaler + CMSDK_RTC->PR = prescaler; + //config data/hour mode + if(data_mode != 0) new_reg_ctrl |= CMSDK_RTC_DATA_MODE_Msk; + if(hour_mode != 0) new_reg_ctrl |= CMSDK_RTC_HOUR_MODE_Msk; + CMSDK_RTC->CR = new_reg_ctrl; + //wait for init sync ready + while(!(CMSDK_RTC->SR & CMSDK_RTC_INIT_SYNC_READY_Msk)); + //set INIT + CMSDK_RTC->CR |= CMSDK_RTC_INIT_EN_Msk; + //Set Initial Time & Date + CMSDK_RTC->TR = init_time; + CMSDK_RTC->DR = init_date; + //Clear INIT bit + CMSDK_RTC->CR &= ~CMSDK_RTC_INIT_EN_Msk; + //wait for init sync ready + while(!(CMSDK_RTC->SR & CMSDK_RTC_INIT_SYNC_READY_Msk)); + + return; + } +/** + * + * @param *CMSDK_RTC RTC Pointer + * @return none + * + * @brief Config RTC Alarm + */ + void CMSDK_RTC_Config_Alarm(uint16_t prescaler, uint8_t data_mode, uint8_t hour_mode, + uint32_t init_time, uint32_t init_date, uint32_t alarm_time, + uint32_t alarm_date) + { + uint32_t new_reg_ctrl = 0; + //wait for rtc prescaler sync ready + while(!((CMSDK_RTC->SR & CMSDK_RTC_PRES_SYNC_READY_Msk) >> CMSDK_RTC_PRES_SYNC_READY_Pos)); + //set prescaler + CMSDK_RTC->PR = prescaler; + //config data/hour mode + if(data_mode != 0) new_reg_ctrl |= CMSDK_RTC_DATA_MODE_Msk; + if(hour_mode != 0) new_reg_ctrl |= CMSDK_RTC_HOUR_MODE_Msk; + CMSDK_RTC->CR = new_reg_ctrl; + //wait for init sync ready + while(!(CMSDK_RTC->SR & CMSDK_RTC_INIT_SYNC_READY_Msk)); + //set INIT + CMSDK_RTC->CR |= CMSDK_RTC_INIT_EN_Msk; + //Set Initial Time & Date + CMSDK_RTC->TR = init_time; + CMSDK_RTC->DR = init_date; + //Set Alarm Time & Date + CMSDK_RTC->TAR = alarm_time; + CMSDK_RTC->DAR = alarm_date; + //Alarm enabled + CMSDK_RTC->CR |= CMSDK_RTC_ALARM_EN_Msk; + //Clear INIT bit + CMSDK_RTC->CR &= ~CMSDK_RTC_INIT_EN_Msk; + + return; + } +/** + * + * @param *CMSDK_RTC RTC Pointer + * @return none + * + * @brief Config Period Wakeup + */ + void CMSDK_RTC_Config_PeriodWake(uint8_t clock_sel, uint16_t prescaler, uint16_t period_time) + { + if(clock_sel) { + CMSDK_RTC->CR |= CMSDK_RTC_WUT_CLK_EN_Msk; + //wait for rtc prescaler sync ready + while(!((CMSDK_RTC->SR & CMSDK_RTC_PRES_SYNC_READY_Msk) >> CMSDK_RTC_PRES_SYNC_READY_Pos)); + //set prescaler + CMSDK_RTC->PR = prescaler; + } + else { + CMSDK_RTC->CR &= ~CMSDK_RTC_WUT_CLK_EN_Msk; + //wait for wut prescaler sync ready + while(!((CMSDK_RTC->SR & CMSDK_RTC_WUT_PRES_SYNC_READY_Msk) >> CMSDK_RTC_WUT_PRES_SYNC_READY_Pos)); + //set prescaler + CMSDK_RTC->WPR = prescaler; + } + //wait for wut value sync ready + while(!((CMSDK_RTC->SR & CMSDK_RTC_WUT_VAL_SYNC_READY_Msk) >> CMSDK_RTC_WUT_VAL_SYNC_READY_Pos)); + //set Wakeup time register + CMSDK_RTC->WTR = period_time; + //Config CR with Periodic Wakeup timer enabled + CMSDK_RTC->CR |= CMSDK_RTC_WUT_EN_Msk; + return; + } + + + + +// --------------------------------------------------------------- // +// TIMER0_IRQ +// --------------------------------------------------------------- // +uint32_t timer0_irq_occurred=0; +uint32_t time_flag =0; +void TIMER0_Handler(void){ + CMSDK_TIMER0->INTCLEAR = 1; + timer0_irq_occurred++; + if(timer0_irq_occurred % 1000 == 0) + { + GPIO_Overturn(GPIO_19); + time_flag++; + printf("%d s\n",time_flag); + } + +} + +// --------------------------------------------------------------- // +// TIMER1_IRQ +// --------------------------------------------------------------- // +uint32_t timer1_irq_occurred=0; +void TIMER1_Handler(void){ + CMSDK_TIMER1->INTCLEAR = 1; + timer1_irq_occurred++; +} diff --git a/FWLIB/source/ENS1_UART.c b/FWLIB/source/ENS1_UART.c new file mode 100644 index 0000000..7a2e693 --- /dev/null +++ b/FWLIB/source/ENS1_UART.c @@ -0,0 +1,300 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_UART.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: +1.V1.0 +Date: +Author: +Modification: 鍒濈増 +*/ + +/* +ENS1 uart鐗规ц鏄 +1 绗﹀悎AMBA APB瑙勮寖 +2 鏈楂115200bps娉㈢壒鐜(鍙互鏈夋洿楂樼殑璁剧疆) +3 鍙戦 鎺ユ敹 鍒嗙FIFO 锛16瀛楄妭锛 +4 鏀寔鑷姩娴佹帶 +5 鏍囧噯寮傛閫氫俊浣(寮濮嬨佸仠姝€佸鍋舵牎楠) +6 DMA +7 鏀寔鍥炵幆娴嬭瘯 +8 涓柇 +9 鍏ㄥ彲缂栫▼涓茶鎺ュ彛鐗圭偣: + 鏁版嵁浣嶅彲璁剧疆锛 5锛6锛7锛8 + 鍋躲佸鎴栭潪濂囧伓浣嶇殑鐢熸垚鍜屾娴 + 鍙骇鐢1銆1.5鎴2浣嶅仠姝綅 + +*/ +#include "my_header.h" +#include "ENS1_UART.h" +#include "ENS1_GPIO.h" +UART_FifoStructrue UART1_Fifo = { + .level = bytes_8 , + .DMA_Enable = 0 , + .FIFO_Enable = 1 , +}; +UART_InitStructure UART1_Init = { + .UART_BaudRate = 115200 , //璁＄畻鍑烘潵鐨凞LL DLH涓嶄负鏁存暟锛 1銆侀渶瑕佹牎鍑哛C绮剧‘搴︼紝2銆侀渶瑕佽皟鏁存澶勭殑娉㈢壒鐜 + .UART_HardwareFlowControl = 0, + .FifoSetting = &UART1_Fifo , +}; +UART_ITStructure UART1_ITSet = { + .UartIntModel = RLSI_EN | RDAI_EN , +}; + +/*鍒ゆ柇鏄惁鏈変腑鏂寕璧*/ +uint8_t UART_INT_PEND(CMSDK_UART_TypeDef* UARTx) //涓0鏃舵湁UART鐨勪腑鏂寕璧 +{ + return (uint8_t)(UARTx->IIR & 0x1); +} +/*涓柇绫诲瀷鍒ゆ柇*/ +uint8_t UART_INT_TYPE(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((UARTx->IIR >> 1) & 0x7 ); +} +/*fifo 浣跨敤鎸囩ず鍣*/ +uint8_t UART_FIFO_USE(CMSDK_UART_TypeDef* UARTx) //0:闈瀎ifo妯″紡 1锛歠ifo 浣胯兘 +{ + return (uint8_t)((UARTx->IIR >> 6) & 0x3); +} + +/*娓呴櫎浼犺緭FIFO*/ +void UART_TXCLR(CMSDK_UART_TypeDef* UARTx) +{ + UARTx->FCR |= (1<<2) ; +} +/*娓呴櫎鎺ユ敹FIFO*/ +void UART_RXCLR(CMSDK_UART_TypeDef* UARTx) +{ + UARTx->FCR |= (1<<1); +} +/*FIFO浣胯兘*/ +void UART_FIFOEnable(CMSDK_UART_TypeDef* UARTx) +{ + UARTx->FCR |= (1); +} +/*FIFO鍏抽棴*/ +void UART_FIFODisable(CMSDK_UART_TypeDef* UARTx) +{ + UARTx->FCR &=~ 1; +} + +/*鎺ユ敹鏁版嵁*/ +uint8_t READ_UART_RCVBuff(CMSDK_UART_TypeDef* UARTx ) +{ + return (uint8_t)(UARTx->RBR & 0xff); +} + +/*鍙戦佹暟鎹*/ +void WRITE_UART_THRBuff(CMSDK_UART_TypeDef* UARTx ,uint8_t data) +{ + UARTx->THR = data; +} + +/*FIFO 鐘舵佽鍙*/ +uint8_t UART_RX_FIFO_LEN(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((UARTx->FSR & 0x001f0000)>>16); //璇诲彇褰撳墠鎺ユ敹FIFO鏁版嵁闀垮害 +} + +uint8_t UART_TX_FIFO_LEN(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((UARTx->FSR & 0x00001f00)>>8); //璇诲彇褰撳墠鍙戦丗IFO鏁版嵁闀垮害 +} + +uint8_t UART_RX_FIFO_FULL(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((((UARTx->FSR & 0x8)>> 3 )==1) ? (1) : (0)) ; //褰撳墠璇诲彇FIFO鏄惁涓烘弧锛 +} + +uint8_t UART_RX_FIFO_EMPTY(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((((UARTx->FSR & 0x4) >> 2)==1) ? (1) : (0) ) ; //褰撳墠璇诲彇FIFO鏄惁涓虹┖锛 +} + +uint8_t UART_TX_FIFO_FULL(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((((UARTx->FSR & 0x2) >> 1)==1) ? (1) : (0)) ; //褰撳墠鍙戦丗IFO鏄惁涓烘弧锛 +} + +uint8_t UART_TX_FIFO_EMPTY(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)(((UARTx->FSR & 0x1)==1) ? (1) : (0)) ; //褰撳墠鍙戦丗IFO鏄惁涓虹┖锛 +} + + +/*鏀跺彂绾跨姸鎬佽幏鍙*/ +uint8_t UARTLine_RCVError(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((UARTx->LSR>>7) & 0x1); //杩斿洖0 娌℃湁閿欒锛 杩斿洖1 鍦╢ifo鍜岄潪fifo鐘舵佷笅閮芥湁涓涓牎楠/甯/鎴栨帴鏀剁紦瀛樻垨fifo 鐨勪腑鏂寚绀猴紙榛樿涓嶄娇鑳絙reak锛 +} + +/*鍒ゆ柇鍙戦佺紦瀛樻槸鍚︿负绌*/ +uint8_t UARTLine_TRANSEmpty(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((UARTx->LSR>>6) & 0x1) ; +} + +/*鍒ゆ柇THR鏄惁涓虹┖*/ +uint8_t UARTLine_THREmpty(CMSDK_UART_TypeDef* UARTx) +{ + return (uint8_t)((UARTx->LSR>>5) & 0x1) ; +} + +/* +鍒濆鍖朥ART闇瑕佷互涓嬫楠: +1. 鎵ц蹇呰鐨勮澶囧紩鑴氬璺鐢ㄨ缃 +2. 閫氳繃灏嗛傚綋鐨勬椂閽熼櫎鏁板煎啓鍏ラ櫎鏁伴攣瀛樺瘎瀛樺櫒(DLL鍜孌LH)鏉ヨ缃墍闇鐨勬尝鐗圭巼銆 +3. 濡傛灉瑕佷娇鐢‵IFO锛岃閫夋嫨鎵闇鐨勮Е鍙戠瓑绾э紝骞堕氳繃灏嗛傚綋鐨勫煎啓鍏(FCR)鏉ュ惎鐢‵IFO銆 + 鍦‵CR瀵勫瓨鍣ㄧ殑 FIFOEN 浣嶉渶棣栧厛閰嶇疆銆 +4. 閫氳繃鍚戣鎺у埗瀵勫瓨鍣(LCR)鍐欏叆閫傚綋鐨勫兼潵閫夋嫨鎵闇鐨勫崗璁缃 +5. 濡傛灉闇瑕佽嚜鍔ㄦ祦閲忔帶鍒讹紝鍒欏皢閫傚綋鐨勫煎啓鍏ヨ皟鍒惰В璋冨櫒鎺у埗瀵勫瓨鍣(MCR)銆 + 璇锋敞鎰忥紝骞堕潪鎵鏈塽art閮芥敮鎸佽嚜鍔ㄦ祦閲忔帶鍒躲 +6. 瀵规寕璧蜂簨浠剁殑閫夋嫨鎵闇鍝嶅簲閫氳繃閰嶇疆FREE浣嶏紝 + 閫氳繃鍦(PMU)瀵勫瓨鍣ㄤ腑璁剧疆TXRST鍜孯XRST浣嶆潵閲婃斁浣嶅苟浣胯兘UART +*/ + + +//uart鍒濆鍖栵紝鍙傛暟1锛歶art0/1锛屽弬鏁2锛歶art鍙傛暟璁剧疆缁撴瀯浣 +void UART_Init(CMSDK_UART_TypeDef *CMSDK_UART, UART_InitStructure* uart_paraX){ + uint16_t divisor_value; + uint8_t overSamp_mode; + /* 1 GPIO - alt_function*/ + if(CMSDK_UART == CMSDK_UART0){ + PCLK_Enable(UART0_PCLK_EN); + GPIO_AltFunction(UART0_RX , ALT_FUNC1); //rx + GPIO_AltFunction(UART0_TX , ALT_FUNC1); //tx + } + else if(CMSDK_UART == CMSDK_UART1) + { + PCLK_Enable(UART1_PCLK_EN); + GPIO_AltFunction(UART1_RX , ALT_FUNC1); //RX + GPIO_AltFunction(UART1_TX , ALT_FUNC1); //TX + } + /* 2 娉㈢壒鐜囪缃*/ + if(((CMSDK_UART->MDR)&0x00000001) == 0) + { + overSamp_mode = 16; //榛樿0 + } + else + { + overSamp_mode = 13; + } + divisor_value = (uint16_t)((uint32_t)(APB_Clock_Freq / uart_paraX->UART_BaudRate / overSamp_mode) - 1); + CMSDK_UART->DLL = (uint8_t)(divisor_value & 0x0011); + CMSDK_UART->DLH = (uint8_t)((divisor_value & 0x1100)>>8); + + /*FCR閰嶇疆 FIFO control*/ + CMSDK_UART->FCR |= (uart_paraX->FifoSetting->level <<6); + if(uart_paraX->FifoSetting->FIFO_Enable == 1) + { + CMSDK_UART->FCR |= (1); + } + + /*LCR閰嶇疆,涓嶅仛閰嶇疆锛岄粯璁 8 1 */ + + + /*MCR鑷姩娴佹帶閰嶇疆*/ + if(uart_paraX->UART_HardwareFlowControl == 1) + { + CMSDK_UART->MCR |= (1<<5); + } + + /*鐢垫簮绠＄悊瀵勫瓨鍣≒MU 鐨凾XRST鍜孯XRST璁剧疆,涓嶉渶瑕佽缃*/ + + +} + +/*UART 鐨勪腑鏂缃*/ +void UART_ITConfig(CMSDK_UART_TypeDef *CMSDK_UART, UART_ITStructure* uart_paraX) +{ + if(CMSDK_UART == CMSDK_UART1){ + NVIC_DisableIRQ(UART1_IRQn);//Disable NVIC interrupt + NVIC_ClearPendingIRQ(UART1_IRQn);//Clear Pending NVINVIC_EnableIRQ(UART1_IRQn);//Enable NVIC interrupt + } + else if(CMSDK_UART == CMSDK_UART0){ + NVIC_DisableIRQ(UART0_IRQn);//Disable NVIC interrupt + NVIC_ClearPendingIRQ(UART0_IRQn);//Clear Pending NVIC interrupt + } + /*IER閰嶇疆锛屼腑鏂娇鑳藉瘎瀛樺櫒*/ + CMSDK_UART->IER |= (uart_paraX->UartIntModel); + + if(CMSDK_UART == CMSDK_UART1){ + NVIC_EnableIRQ(UART1_IRQn); + } + else if(CMSDK_UART == CMSDK_UART0){ + NVIC_EnableIRQ(UART0_IRQn); + } +} + + +unsigned char UartPutc(CMSDK_UART_TypeDef *CMSDK_UART ,unsigned char my_ch) +{ + while (UARTLine_THREmpty(CMSDK_UART) == 0x0); + WRITE_UART_THRBuff(CMSDK_UART,my_ch); + return (my_ch); +} + + + +/* +涓柇涓庝腑鏂姸鎬佹竻闄 +1 鎺ユ敹绾跨姸鎬侊細INT_RCV_LINE_STATUS + 婧㈠嚭銆佹牎楠屻佸抚閿欒鎴栨娴嬪埌break + 涓柇娓呴櫎鏂瑰紡锛氬浜庢孩鍑洪敊璇紝璇诲彇LSR 鍙竻闄や腑鏂紝瀵逛簬鏍￠獙銆佸抚閿欒鎴朾reak锛屼腑鏂渶瑕佺瓑寰呮墍鏈夌殑閿欒鏁版嵁琚鍙栧悗鎵嶈娓呴櫎 +2 鎺ユ敹鏁版嵁灏辩华锛 INT_RCV_DATA_AVAILABLE + 闈濬IFO妯″紡涓嬶紝鎺ユ敹鏁版嵁鍑嗗灏辩华锛 fifo妯″紡涓嬶紝杈惧埌瑙﹀彂闃堝硷紝濡傛灉鍥涗釜瀛楄妭鏃堕棿鍐呮病鏈夎闂瓼IFO ,灏卞啀娆¤Е鍙 + 涓柇娓呴櫎鏂瑰紡锛氶潪FIFO妯″紡涓嬶紝RBR琚鍙 锛 FIFO妯″紡涓嬶紝FIFO浣庝簬瑙﹀彂闃堝艰娓呴櫎 +3 鎺ユ敹瓒呮椂锛欼NT_CHAR_TIMEOUT_INDICATION + 浠呬粎FIFO妯″紡鏈夋晥 锛 鍦ㄦ渶鍚庡洓涓瓧鑺傜殑鏃堕棿鍐咃紝娌℃湁瀛楃浠庢帴鏀跺櫒FIFO 涓Щ闄ゆ垨鑰呰緭鍏ワ紝骞朵笖鍦ㄦ鏈熼棿鎺ユ敹鍣‵IFO涓嚦灏戞湁涓涓瓧绗 + 涓柇娓呴櫎鏂瑰紡锛氾紙1锛1涓瓧鑺備粠鎺ユ敹FIFO涓璇诲嚭 锛2锛変竴涓柊鐨勫瓧鑺傚埌杈炬帴鏀禙IFO 锛3锛塒MU瀵勫瓨鍣ㄤ腑鐨刄RRST 浣嶇疆1 +4 浼犺緭淇濇寔瀵勫瓨鍣ㄧ┖锛圱HR锛 INT_THR_EMPTY + 闈濬IFO妯″紡涓嬶細 THR绌恒 FIFO妯″紡涓嬶紝浼犺緭鍣‵IFO绌 + 涓柇娓呴櫎鏂瑰紡锛氫竴涓瓧鑺傝鍐欏埌 THR +*/ + +void UART0_Handler(void) { + uint8_t rev_data = 0; + NVIC_ClearPendingIRQ(UART0_IRQn); + //鎺ユ敹绾夸腑鏂 鏈夐敊璇垨鑰卋reak + if(UART_INT_TYPE(CMSDK_UART0) == INT_RCV_LINE_STATUS) { + CMSDK_UART0->IER &= ~CMSDK_UART_IER_RLSI_EN_Msk; + } + + //鏁版嵁灏辩华涓柇 + //鎺ユ敹瓒呮椂涓柇 + if((UART_INT_TYPE(CMSDK_UART0) == INT_RCV_DATA_AVAILABLE) || (UART_INT_TYPE(CMSDK_UART0) == INT_CHAR_TIMEOUT_INDICATION)) + { + CMSDK_UART0->IER &= ~CMSDK_UART_IER_RDAI_EN_Msk; + rev_data = CMSDK_UART0->RBR; + UartPutc(CMSDK_UART0,rev_data); + CMSDK_UART0->IER |= CMSDK_UART_IER_RDAI_EN_Msk; + } + return; +} + +void UART1_Handler(void) { + uint8_t rev_data = 0; + NVIC_ClearPendingIRQ(UART1_IRQn); + //鎺ユ敹绾夸腑鏂 鏈夐敊璇垨鑰卋reak + if(UART_INT_TYPE(CMSDK_UART1) == INT_RCV_LINE_STATUS) { + CMSDK_UART1->IER &= ~CMSDK_UART_IER_RLSI_EN_Msk; + } + + //鏁版嵁灏辩华涓柇 + //鎺ユ敹瓒呮椂涓柇 + if((UART_INT_TYPE(CMSDK_UART1) == INT_RCV_DATA_AVAILABLE) || (UART_INT_TYPE(CMSDK_UART1) == INT_CHAR_TIMEOUT_INDICATION)) { + + CMSDK_UART1->IER &= ~CMSDK_UART_IER_RDAI_EN_Msk; + rev_data = CMSDK_UART1->RBR; + UartPutc(CMSDK_UART1,rev_data); + CMSDK_UART1->IER |= CMSDK_UART_IER_RDAI_EN_Msk; + } + return; +} + diff --git a/FWLIB/source/ENS1_WATCHDOG.c b/FWLIB/source/ENS1_WATCHDOG.c new file mode 100644 index 0000000..c726ad9 --- /dev/null +++ b/FWLIB/source/ENS1_WATCHDOG.c @@ -0,0 +1,64 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_WATCHDOG.c +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ + +#include "ENS1_WATCHDOG.h" + + +//设置load值 +void WatchDogLoad(uint32_t loadvalue_us) +{ + CMSDK_WATCHDOG->LOAD = loadvalue_us * (uint8_t)(APB_Clock_Freq/1000000) ; +} + +//读取watchdog 递减计数器当前值 +uint32_t Read_WDOGVALUE(void) +{ + return ( CMSDK_WATCHDOG->VALUE & 0xffffffff ); +} + +//使能看门够中断事件 +void WatchDog_Control(FunctionalState newstate) +{ + if(newstate == ENABLE) + { + CMSDK_WATCHDOG->CTRL |= (0x3); + } + else + { + CMSDK_WATCHDOG->CTRL &=~ (0x3); + } +} + +//清除看门狗中断事件,清除后将自动重载计数值 +void WatchDog_IntClear(void) +{ + CMSDK_WATCHDOG->INTCLR = 1 ; +} + +//解除看门狗锁寄存器或给看门狗寄存器上锁 +uint8_t WatchDog_LOCK_RegSet(WdogLockState newstate) +{ + if(newstate == LOCK) + { + CMSDK_WATCHDOG->LOCK = 0; + } + else + { + CMSDK_WATCHDOG->LOCK = 0x1ACCE551; + } + return (CMSDK_WATCHDOG->LOCK &0x1); +} + diff --git a/FWLIB/source/ENS_ADC.c b/FWLIB/source/ENS_ADC.c new file mode 100644 index 0000000..d222ba1 --- /dev/null +++ b/FWLIB/source/ENS_ADC.c @@ -0,0 +1,250 @@ +/* +*Copyright (C),2023 , NANOCHAP +*File name: ENS1_ADC.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: +1.V1.0 +Date: +Author: +Modification: 初版 +*/ + +#include "ENS1_ADC.h" +#include "ENS1_GPIO.h" +#include "ENS1_CLOCK.h" +#include "ENS1_ANAC.h" +/* 一、寄存器说明： +ADC配置：转换模式 数据覆盖模式 等待模式 +ADC控制： ADC使能 ， ADC启动 +ADC中断使能： EOC中断使能 数据覆盖中断使能 +ADC中断状态： EOC中断发生 数据覆盖中断发生 +ADC状态 ： EOC标志 ADC空闲或繁忙状态 +ADC时钟分频 ：分频值 2 4 6 8 10 12 16 32 +ADC采样时间 ：ADC采样时间时钟数 2 3 4 5 +ADC数据： +ADC通道选择 ： +ADCEOC配置 ：在连续模式下 ， 是否在接收到EOC标志后开启下次转换 +*/ + +/* 二、单次转换模式 + *ADC控制启将 给ADC_START 位置0 当接收到EOC或者EOC_WAIT_COUNT_DONE ， 无论哪一个先到来 + *如果直到EOC_WAIT_COUNT_DONE 都没有接收到EOC ，数据将不会被保存 + *ADC将停止转换，通过用户设置ADC_CTRL_REG 的 ADC_EN 位 为1 + *如果在采样和转换期间，ADC_EN 位置为0 ，控制器将完成正在进行的转换，然后基于 EOC/EOC_WAIT_COUNT_DONE 停止转换 + *数据会在EOC 到达后锁存 + +ADC单次转换流程： +1、设置单次转换（无等待模式） +2、设置ADC_CONFIG_reg bit0 = 0 bit2 = 0 +3、单次转换启动 +4、转换结束， 数据保存至ADC_Data register +5、一个ADC_EOC_IE中断生成， +6、如果使能了 IER寄存器的 EOC_INT_EN 和OVER_RUN_INT_EN 位，则系统进入中断 +7、硬件停止ADC +*/ + +/*三、连续转换模式 +1、设置ADC_CONFIG_reg bit0 = 1 +2、启动位置1 ADC_EN bit and ADC_START bits +3、在每次转换完成之后，基于adc_eoc_config_regsiter[0] 启动下次转换： + 如果Adc_eoc_config_register[0] =1 ， 则接收到EOC后开始下次转换 + 数据保存到寄存器中 +4、ADC_EOC_IE 中断生成 +5、如果使能了 IER寄存器的 EOC_INT_EN 和OVER_RUN_INT_EN 位，则系统进入中断 + +注意：ADC_eoc_config_reg寄存器仅仅在连续采样-非等待模式下有效 即：0：连续模式不接收EOC即开始启动下一次转换 + 1：连续模式接收到EOC后开始启动下一次转换 +在连续采样-等待模式下，ADC_eoc_config_reg应该被设置为0 ！！！ +*/ + +/*四、等待模式 +1、设置ADC_CONFIG_reg bit2 = 1 （使能等待模式） +2、启动测量转换 +3、在转换完成后： + 存ADC数据到相应寄存器中 + ADC_EOC_IE 中断生成 + 如果使能了 IER寄存器的 EOC_INT_EN 和OVER_RUN_INT_EN 位，则系统进入中断 +4、ADC控制器进入到ADC_WAIT 等待状态直到EOC中断被清除 或者 ADC数据被系统读走 +5、一旦EOC中断被清除，ADC开始下一次的转换 +*/ + +/*五、数据锁存器 +1、当ADC控制启接收到EOC后，数据将被锁存 +2、如果 OVERRUN模式被使能，新的转换数据将会被锁存 无论 overrun 错误状态如何 + +注意： 如果overrun 模式没有被使能， 新的或者旧的转换数据将根据overrun 错误状态选择性锁存 + 即： 如果overrun 错误发生，数据将不会被锁存 + 如果没有overrun 错误发生，新数据将被锁存 +*/ + +/*六、中断说明 +1、接收到EOC后 EOC_IR 生成 +2、OVERRUN错误发生后OVERRUN_IR 生成 +3、EOC_IR 和overrun 作为ADC中断被 通道到系统 + 在系统通过 data_reg 读取走adc数据后， EOC_IR 被 EOC_IR_CLEAR 清除 +*/ + +/*overrun 错误 + 此错误指的是： ADC控制器在系统读取走ADC数据前（在清除到上一个EOC_IR前），接收到新的EOC +*/ + + +volatile uint8_t ADC_READ_STATUS = ADC_READ_DATA_IS_WAITING; +uint8_t ADC_UART_BYTE_LOW = 0; +uint8_t ADC_UART_BYTE_HIGH = 0; + +uint8_t ENS1_ADCCLKConfig(uint8_t ADC_CLK_div) +{ + CMSDK_ADC->ADC_CLK_DIV = ((CMSDK_ADC->ADC_CLK_DIV &~ (0x7)) | (ADC_CLK_div)); + return 0; +} +/* + ENS_ADC_COV_MODE COV_MODE + ENS_ADC_OVERRUN_MODE OVERRUN_MODE + WAIT_MODE WAITorNOT +*/ +uint8_t ENS1_ADC_CONFIG(ENS_ADC_SEL channelx , + uint8_t MODE_SEL, + ENS_ADC_COV_INC_EOC EOC_CONFIG , + uint8_t SIMLING_TIME, + uint8_t INT_MODE_SEL) +{ + NVIC_ClearPendingIRQ(ADC_IRQn); + NVIC_DisableIRQ(ADC_IRQn); + if(channelx == ENS1_ADC_CHANNEL1) + { + CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<10))|(0x03<<10); + CMSDK_GPIO->ANAEN |= (1 << 21); + CMSDK_ADC->ADC_CH_SEL &=~ (0x7); + CMSDK_ADC->ADC_CH_SEL = 1; + } + else if(channelx == ENS1_ADC_CHANNEL2) + { + CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<12))|(0x03<<12); + CMSDK_GPIO->ANAEN |= (1 << 22); + CMSDK_ADC->ADC_CH_SEL &=~ (0x7); + CMSDK_ADC->ADC_CH_SEL = 2; + } + else if(channelx == ENS1_ADC_CHANNEL3) + { + CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<14))|(0x03<<14); + CMSDK_GPIO->ANAEN |= (1 << 23); + CMSDK_ADC->ADC_CH_SEL &=~ (0x7); + CMSDK_ADC->ADC_CH_SEL = 3; + } + else + { + CMSDK_ADC->ADC_CH_SEL &=~ (0x7); + CMSDK_ADC->ADC_CH_SEL = 0; + } + + + CMSDK_ADC->ADC_CONFG =(CMSDK_ADC->ADC_CONFG &~ 0x7 )| MODE_SEL; + + CMSDK_ADC->ADC_SAMP_TIME = (CMSDK_ADC->ADC_SAMP_TIME &~ 0x3) | SIMLING_TIME; + + //配置ADC_eoc_config_reg寄存器，（仅仅在连续采样-非等待模式下有效） + if( ((MODE_SEL & 0X1 )== 1 ) && (MODE_SEL & 0X4) == 0) + { + CMSDK_ADC->ADC_EOC_CONFG = (CMSDK_ADC->ADC_EOC_CONFG &~ (0x1)) | EOC_CONFIG; + } + + //中断使能 + CMSDK_ADC->ADC_IER = (CMSDK_ADC->ADC_IER &~ (0x3)) | ( INT_MODE_SEL ); + return CMSDK_ADC->ADC_CONFG; +} + +uint8_t ENS1_ADC_START(ENS_ADC_SEL channelx ) +{ + CMSDK_ADC->ADC_CTRL |= (1) |(1<<8); + if(CMSDK_ADC->ADC_IER != 0) + { + NVIC_EnableIRQ(ADC_IRQn); + } + return 0; +} + +uint8_t ENS1_ADC_STOP(ENS_ADC_SEL channelx) +{ + CMSDK_ADC->ADC_CTRL &=~ (1); + NVIC_DisableIRQ(ADC_IRQn); + return 0; +} + +//连续读取数据 +//ADC在不同模式下有不同的采集方式，根据Adc_config_register的配置不同，共8种模式 +uint16_t save_data; +uint8_t ADC_CONFIG_READ; +//此函数未完成，测试使用连续采集+中断模式，此函数暂时用不到 + +uint16_t ADC_READ_DATA(void) +{ + + ADC_CONFIG_READ = CMSDK_ADC->ADC_CONFG; + switch(ADC_CONFIG_READ & 0x7) { + case single_mode_without_overrun_without_wait : + while(ADC_READ_STATUS == ADC_READ_DATA_IS_WAITING); //等待在中断中EOC的到来 + ADC_READ_STATUS = ADC_READ_DATA_IS_WAITING; //中断发生，已经有ADC的数据了，此时再将状态切换到等待下一次数据 + + break; + + case continious_mode_without_overrun_without_wait : + + break; + + case single_mode_with_overrun_without_wait : + + break; + + case continious_mode_with_overrun_without_wait : + + break; + + case single_mode_without_overrun_with_wait : + + + + break; + + case Continious_mode_without_overun_with_wait : + + break; + + case single_mode_with_overrun_with_wait : + + break; + + case continious_mode_with_overrun_with_wait : + + break; + + } + return (uint16_t)save_data; +} + +//ADC interrupt handler +void ADC_Handler(void) __irq +{ + if((CMSDK_ADC->ADC_ISR & 0x01) == 0x01) //接收到EOC + { + CMSDK_ADC->ADC_INT_CLR = (0x01<<0); + ADC_READ_STATUS = ADC_READ_DATA_IS_READY; + save_data = (CMSDK_ADC->ADC_DATA & 0x0fff); //读走数据后，可以进行下一次采集 + printf("%d\n",save_data); + ADC_UART_BYTE_LOW = save_data&0xff; + ADC_UART_BYTE_HIGH = (save_data&0x0f00)>>8; + } + if(((CMSDK_ADC->ADC_ISR & 0x02)>>1) == 0x01) //overrun error + { + CMSDK_ADC->ADC_INT_CLR = (0x01<<1); + } +} + + + + diff --git a/FWLIB/source/ENS_CURRENT_CALIBRATION.c b/FWLIB/source/ENS_CURRENT_CALIBRATION.c new file mode 100644 index 0000000..55829d4 --- /dev/null +++ b/FWLIB/source/ENS_CURRENT_CALIBRATION.c @@ -0,0 +1,480 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: ENS1_CURRENT_CALIBRATION.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: +*Function List: + +History: + 1.V1.0 + Date: + Author: + Modification: 初版 +*/ +#include "ENS_CURRENT_CALIBRATION.h" +#include "ENS1_MTP.h" +#include "ENS1_UART.h" +#include "ENS1_TIMER.h" + +/*--------------------------------波形参数的初始化幅值结构体-----------------------------*/ + +STRUCT_WAVEFORM_PARA ParaSet_waveform[4] = +{ + /*通道1 -- ST0 ST1 */ + { + .Type = SQUARE_WAVE , //波形种类选择 + .PositivePulseWidth = 100 , //正半周期脉宽-微秒 + .DeadTime = 10, //死区时间-微秒 + .NegativePulseWidth = 100 , //负半周期脉宽-微秒 + .ClientTime = 1000 , //静默时间-微秒 + .DelayOutputTime_US = 0, //延迟输出时间-微秒 + .OtherWaveformPara.AlternatingFreq_HZ = 0, //交替波形频率 // + .OtherWaveformPara.TotalOutputTime_S = 0, //设置总输出时间 秒 + .OtherWaveformPara.NumOfPulseGroups = 0, //脉冲群模式下的每组脉冲数量 + .OtherWaveformPara.TimeOfPulseGroups_MS = 0, //脉冲群模式下的组间隔时间 毫秒 + }, + /*通道2 -- ST2 ST3 */ + { + .Type = TRIANGULAR_WAVE , //波形种类选择 + .PositivePulseWidth = 0 , //正半周期脉宽-微秒 + .DeadTime = 0, //死区时间-微秒 + .NegativePulseWidth = 0 , //负半周期脉宽-微秒 + .ClientTime = 0 , //静默时间-微秒 + .DelayOutputTime_US = 0, //延迟输出时间-微秒 + .OtherWaveformPara.AlternatingFreq_HZ = 0, //交替波形频率 // + .OtherWaveformPara.TotalOutputTime_S = 0, //设置总输出时间 秒 + .OtherWaveformPara.NumOfPulseGroups = 0, //脉冲群模式下的每组脉冲数量 + .OtherWaveformPara.TimeOfPulseGroups_MS = 0, //脉冲群模式下的组间隔时间 毫秒 + }, + /*通道3 -- ST4 ST5 */ + { + .Type = TRIANGULAR_WAVE , //波形种类选择 + .PositivePulseWidth = 0 , //正半周期脉宽-微秒 + .DeadTime = 0, //死区时间-微秒 + .NegativePulseWidth = 0 , //负半周期脉宽-微秒 + .ClientTime = 0 , //静默时间-微秒 + .DelayOutputTime_US = 0, //延迟输出时间-微秒 + .OtherWaveformPara.AlternatingFreq_HZ = 0, //交替波形频率 // + .OtherWaveformPara.TotalOutputTime_S = 0, //设置总输出时间 秒 + .OtherWaveformPara.NumOfPulseGroups = 0, //脉冲群模式下的每组脉冲数量 + .OtherWaveformPara.TimeOfPulseGroups_MS = 0, //脉冲群模式下的组间隔时间 毫秒 + }, + /*通道4 -- ST6 ST7 */ + { + .Type = TRIANGULAR_WAVE , //波形种类选择 + .PositivePulseWidth = 0 , //正半周期脉宽-微秒 + .DeadTime = 0, //死区时间-微秒 + .NegativePulseWidth = 0 , //负半周期脉宽-微秒 + .ClientTime = 0 , //静默时间-微秒 + .DelayOutputTime_US = 0, //延迟输出时间-微秒 + .OtherWaveformPara.AlternatingFreq_HZ = 0, //交替波形频率 // + .OtherWaveformPara.TotalOutputTime_S = 0, //设置总输出时间 秒 + .OtherWaveformPara.NumOfPulseGroups = 0, //脉冲群模式下的每组脉冲数量 + .OtherWaveformPara.TimeOfPulseGroups_MS = 0, //脉冲群模式下的组间隔时间 毫秒 + }, +}; + +/*-------------------------------------------------------------------------------------*/ + +/*-------------------------获取到FT测试后的实际测量单元电流值---------------------------*/ +uint16_t FT_CURRENT_SAVE[4]={0,0,0,0}; //用于保存FT读取出的数据 +uint8_t CUSTOM_UNIT_CURRENT[4]={33,33,33,33}; //用于自定义单元电流值 +uint8_t unit_current[4] ={0,0,0,0}; //保存计算好的实际单元电流值 +uint8_t GET_FT_CURRENT(void) //电流设置：208*4 +{ + //当需要使用FT后的芯片时，打开注释， 此时自动计算单元电流 + //当手动校准时，修改CUSTOM_UNIT_CURRENT[4] 数组中的数据，并将下面4行注释掉 +// flash_read(DATA_SAVE_ADDR ,&FT_CURRENT_SAVE[0]);//读出保存在MTP中的实际检测电流值用于计算实际单元电流 +// flash_read(DATA_SAVE_ADDR+2 ,&FT_CURRENT_SAVE[1]);//读出保存在MTP中的实际检测电流值用于计算实际单元电流 +// flash_read(DATA_SAVE_ADDR+4 ,&FT_CURRENT_SAVE[2]);//读出保存在MTP中的实际检测电流值用于计算实际单元电流 +// flash_read(DATA_SAVE_ADDR+6 ,&FT_CURRENT_SAVE[3]);//读出保存在MTP中的实际检测电流值用于计算实际单元电流 + for(int i = 0 ;i<4;i++) + { + if(FT_CURRENT_SAVE[i] != 0) + unit_current[i] = (uint8_t)(FT_CURRENT_SAVE[i] /( 208 * 4 )) ; //计算实际单元电流 + else + unit_current[i] = CUSTOM_UNIT_CURRENT[i] ; + } + return 0; +} + +/*-------------------------------------输出电流大小设置--------------------------------*/ +//正弦波计算数据填充值 +double sin_cal(uint8_t angle) //0-180 +{ + double radian = angle*PI/180; + return sin(radian); +} + +//计算不同波形下的的64个点的值，当前有方波，正弦波，三角波 +uint16_t unit_t[4]; //保存计算后的单元电流系数（0-7） 共四个通道 +uint32_t isel_t[4][64]; //保存计算后得到的电流挡位（0-255）共四个通道 +BasicWaveformType wavePara_type[4]; +uint8_t cal_output_current_mA(CHANNEL_NUM CHANNEL_X,float mA,BasicWaveformType type, uint16_t* unit , uint32_t (*isel)[64]) // uint16_t read_current_data +{ + CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK; + if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; + else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; + else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; + else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; + + if(!mA) + { + for(uint8_t i = 0 ;i<4;i++){ + unit_t[i] = 0; + for(uint8_t j = 0;j<64;j++) + { + isel_t[i][j] = 0; + } + } + } + else + { + if(type == SQUARE_WAVE) + { + //保存计算结果,用于给电流相关的寄存器赋值 + *(unit+CHANNEL_X) = (uint16_t)(mA * 1000 / (unit_current[CHANNEL_X] * 255)); // 0 - 7 + for(int i = 0 ;i<64;i++) + { + *(isel[0]+CHANNEL_X*64+i) = (uint16_t)(mA * 1000 / ((*(unit+CHANNEL_X)+1)*unit_current[CHANNEL_X])); // 0 - 255 + } + } + else if(type== SINE_WAVE) + { + //保存计算结果,用于给电流相关的寄存器赋值 + *(unit+CHANNEL_X) = (uint16_t)(mA * 1000 / (unit_current[CHANNEL_X] * 255)); // 0 - 7 + for(int i = 0 ;i<64;i++) + { + *(isel[0]+CHANNEL_X*64+i) = (uint16_t)(mA * 1000 / ((*(unit+CHANNEL_X) + 1)*unit_current[CHANNEL_X])*sin_cal(i*2.85714)); // 0 - 255 + } + } + else //三角波赋值(type == TRIANGULAR_WAVE ) + { + //保存计算结果,用于给电流相关的寄存器赋值 + + *(unit+CHANNEL_X) = (uint16_t)(mA * 1000 / (unit_current[CHANNEL_X] * 255)); // 0 - 7 + *(isel[0]+CHANNEL_X*64) = 0; + *(isel[0]+CHANNEL_X*64+63) = 0; + for(int j = 1 ; j<32 ; j++) + { + *(isel[0]+CHANNEL_X*64+j) = (uint16_t)(mA * 1000 / ((*(unit+CHANNEL_X)+1)*unit_current[CHANNEL_X]) * 0.033258*j); // 0 - 255 + // printf("%d\n",*(isel[0]+CHANNEL_X*64+j)); + } + for(int k = 32 ; k<63 ; k++) + { + *(isel[0]+CHANNEL_X*64+k) =*(isel[0]+CHANNEL_X*64+(63-k)) ; + // printf("%d\n",*(isel[0]+CHANNEL_X*64+k)); + } + } + } + return 0; +} + +/*初始化设置*/ +/*CONFIG寄存器设置*/ +uint8_t ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_NUM CHANNEL_X , DRV_CONFIG BIT) +{ + CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK; + if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; + else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; + else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; + else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; + if(BIT == DISABLE_ALL_BIT) + { + WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG = 0x00; + return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ; + } + if(BIT == ENABLE_ALL_BIT) + { + WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG = ENABLE_ALL_BIT; + return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ; + } + if((BIT != DISABLE_ALL_BIT) && (BIT != ENABLE_ALL_BIT)) + { + WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG |= BIT; + } + return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ; +} + +uint8_t ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_NUM CHANNEL_X , DRV_CONFIG BIT) +{ + CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK; + if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; + else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; + else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; + else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; + if(BIT == DISABLE_ALL_BIT) + { + WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG = 0x00; + return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ; + } + if(BIT == ENABLE_ALL_BIT) + { + WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG = ENABLE_ALL_BIT; + return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ; + } + if((BIT != DISABLE_ALL_BIT) && (BIT != ENABLE_ALL_BIT)) + { + WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG &=~ BIT; + } + return (uint8_t)WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG ; +} + + +/*---------------------------电刺激有关的寄存器的初始化--------------------------------*/ +uint32_t StimulatorInit(CHANNEL_NUM CHANNEL_X) +{ + //uint32_t WaveformFreq=0; + CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK; + if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; + else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; + else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; + else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; + //config 设置 + ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,DISABLE_ALL_BIT); + //1 、 死区时间不为0，波形不为sine波 ,使能REST + if((ParaSet_waveform[CHANNEL_X].DeadTime > 0)){ + ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,REST_BIT); + } + else + { + ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,REST_BIT); + } + //2 、 负半周期脉宽大于0 使能 NEGATIVE_BIT 和 SOURCE_B_BIT + if(ParaSet_waveform[CHANNEL_X].NegativePulseWidth > 0) + { + ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,SOURCE_B_BIT ); //SOURCEB不使能则负半周期的数据无效（=0） + ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,NEGATIVE_BIT ); + } + //3、静默时间不为0，开启SILENT_BIT + if(ParaSet_waveform[CHANNEL_X].ClientTime>0) + { + ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,SILENT_BIT); + } + else + { + ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,SILENT_BIT); + } + + //4、交替模式ALTERNATING_POSITIVE_BIT + if(ParaSet_waveform[CHANNEL_X].OtherWaveformPara.AlternatingFreq_HZ > 0 ) + { + ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,ALTERNATING_POSITIVE_BIT); + ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,SOURCE_B_BIT); + ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,NEGATIVE_BIT); + //交替时间与主频有关,输入的参数为交替频率，需要转化为时钟个数，时钟个数不能超过2^16 + WAVE_GEN_BLK ->WAVE_GEN_DRV_ALT_LIM_REG =(uint16_t)(ParaSet_waveform[CHANNEL_X].PositivePulseWidth / (uint16_t)ParaSet_waveform[CHANNEL_X].OtherWaveformPara.AlternatingFreq_HZ * (uint16_t)(APB_Clock_Freq/1000000)) ; + ParaSet_waveform[CHANNEL_X].NegativePulseWidth = 0; + } + else + { + ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,ALTERNATING_POSITIVE_BIT); + } + + ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,CONTINUE_REPEATING_BIT); + //延迟输出时间计算 单位us + WAVE_GEN_BLK->WAVE_GEN_DRV_DELAY_LIM_REG = (uint8_t)(APB_Clock_Freq/1000000)*ParaSet_waveform[CHANNEL_X].DelayOutputTime_US; + //根据初始化后的STRUCT_WAVEFORM_PARA结构体给对应的寄存器赋值 + + WAVE_GEN_BLK->WAVE_GEN_DRV_NEG_HLF_WAVE_PRD_REG = ParaSet_waveform[CHANNEL_X].NegativePulseWidth; + WAVE_GEN_BLK->WAVE_GEN_DRV_HLF_WAVE_PRD_REG = ParaSet_waveform[CHANNEL_X].PositivePulseWidth; + WAVE_GEN_BLK->WAVE_GEN_DRV_CLK_FREQ_REG = (uint32_t)(APB_Clock_Freq/1000000); // + WAVE_GEN_BLK->WAVE_GEN_DRV_SILENT_T_REG = ParaSet_waveform[CHANNEL_X].ClientTime; + WAVE_GEN_BLK->WAVE_GEN_DRV_REST_T_REG = ParaSet_waveform[CHANNEL_X].DeadTime; + WAVE_GEN_BLK->WAVE_GEN_DRV_NEG_SCALE_REG = 1; //寄存器默认为0， 必须写大于0的数 + WAVE_GEN_BLK->WAVE_GEN_DRV_NEG_OFFSET_REG = 0; + + //WaveformFreq = (uint32_t)(1000000 / (wavePara.ClientTime + wavePara.DeadTime +wavePara.NegativePulseWidth + wavePara.PositivePulseWidth)); + //保存波形类型数据 + wavePara_type[CHANNEL_X] = ParaSet_waveform[CHANNEL_X].Type; + + TOTAL_TIME_THRESHOLD_VALUE[CHANNEL_X] = ParaSet_waveform[CHANNEL_X].OtherWaveformPara.TotalOutputTime_S * 1000; + if( (ParaSet_waveform[CHANNEL_X].OtherWaveformPara.TimeOfPulseGroups_MS > 0) || (ParaSet_waveform[CHANNEL_X].OtherWaveformPara.NumOfPulseGroups >0)) + { + TRIGGER_TIME_COUNT[CHANNEL_X] = 0; //间隔时间清零 + TRIGGER_TIME_THRESHOLD_VALUE[CHANNEL_X]=ParaSet_waveform[CHANNEL_X].OtherWaveformPara.TimeOfPulseGroups_MS ; + NUM_OF_PULSES_THRESHOLD[CHANNEL_X] = ParaSet_waveform[CHANNEL_X].OtherWaveformPara.NumOfPulseGroups ; + WAVE_GEN_BLK->WAVE_GEN_DRV_INT_REG = 0x001f0001; + } + uint8_t returnValue = cal_output_current_mA(CHANNEL_X,0, wavePara_type[CHANNEL_X], unit_t , isel_t) ; + + return (uint32_t)(WAVE_GEN_BLK->WAVE_GEN_DRV_CONFIG_REG); //返回波形的频率 +} + +/*--------------------------------------启动输出-----------------------------------------*/ +volatile uint8_t statics_config=0; //明确当前有几个通道在输出 0 / 1 / 2 /4 / 8 +void StartStimulatorOut(CHANNEL_NUM CHANNEL_X) +{ + CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK; + if(CHANNEL_X == CHANNEL_0) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; statics_config |= (1<<0); } + else if(CHANNEL_X == CHANNEL_1) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; statics_config |= (1<<1);} + else if(CHANNEL_X == CHANNEL_2) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; statics_config |= (1<<2);} + else {WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; statics_config |= (1<<3) ;} + if(statics_config > 1) + { + ENS_STIMU_CONFIG_BIT_ENABLE(CHANNEL_X,MULTI_ELECTRODE_BIT); //多电极使能 + } + WAVE_GEN_BLK->WAVE_GEN_DRV_CTRL_REG = 1; +} +/*--------------------------------------停止输出----------------------------------------*/ +void StopStimulatorOut(CHANNEL_NUM CHANNEL_X) +{ + CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK; + if(CHANNEL_X == CHANNEL_0) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; statics_config &=~(1<<0); } + else if(CHANNEL_X == CHANNEL_1) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; statics_config &=~(1<<1); } + else if(CHANNEL_X == CHANNEL_2) {WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; statics_config &=~(1<<2); } + else {WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; statics_config &=~(1<<3); } + WAVE_GEN_BLK->WAVE_GEN_DRV_CTRL_REG = 0; + if(statics_config < 2) + { + ENS_STIMU_CONFIG_BIT_DISABLE(CHANNEL_X,MULTI_ELECTRODE_BIT); + } +} + +/*-----------------------------电刺激过程中的电流、频率设置-------------------------------*/ +/*输出电流大小修改*/ +uint8_t CURRENT_AMPLITUDE_MODIFY(CHANNEL_NUM CHANNEL_X , float mA) +{ + CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK; + if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; + else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; + else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; + else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; + + NVIC_DisableIRQ(WG_DRV_IRQn); + WAVE_GEN_BLK->WAVE_GEN_DRV_INT_REG = 0; + StopStimulatorOut(CHANNEL_X); + cal_output_current_mA(CHANNEL_X,mA, wavePara_type[CHANNEL_X], unit_t , isel_t) ; + WAVE_GEN_BLK ->WAVE_GEN_DRV_ISEL_REG = unit_t[CHANNEL_X]; //范围 0x00 - 0x07 单元电流 + for(int i=0; i<64; i++){ + WAVE_GEN_BLK->WAVE_GEN_DRV_IN_WAVE_ADDR_REG = i; + WAVE_GEN_BLK->WAVE_GEN_DRV_IN_WAVE_REG = isel_t[CHANNEL_X][i]; //最大0xff 电流挡位 + } + WAVE_GEN_BLK->WAVE_GEN_DRV_INT_REG = 0x001f0001; + NVIC_EnableIRQ(WG_DRV_IRQn); + StartStimulatorOut(CHANNEL_X); + return (uint8_t)(WAVE_GEN_BLK->WAVE_GEN_DRV_CTRL_REG); //返回状态 +} + +/*输出波形频率的实时修改，输出时，波形频率=(1000000/(正半周期脉宽 + 负半周期脉宽 + 死区时间 + 静默时间))*/ +uint32_t CURRENT_FREQ_MODIFY(CHANNEL_NUM CHANNEL_X , uint32_t freq) +{ + uint32_t Pulse_Width = 0; + CMSDK_WAVE_GEN_TypeDef* WAVE_GEN_BLK; + if(CHANNEL_X == CHANNEL_0) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK0; + else if(CHANNEL_X == CHANNEL_1) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK1; + else if(CHANNEL_X == CHANNEL_2) WAVE_GEN_BLK=WAVE_GEN_DRVA_BLK2; + else WAVE_GEN_BLK = WAVE_GEN_DRVA_BLK3; + if(freq > 50000 ) + freq = 50000; + else if(freq < 10) + freq = 10; + //死区数值不改动，如果静默时间不为0 ，则通过修改静默时间修改波形频率 ，如果静默时间为0，则修改正半周期/负半周期脉宽修改频率 + if(ParaSet_waveform[CHANNEL_X].ClientTime > 0) + { + Pulse_Width/*静默时间*/ = (uint32_t)((1000000/freq) - ParaSet_waveform[CHANNEL_X].DeadTime - ParaSet_waveform[CHANNEL_X].PositivePulseWidth - ParaSet_waveform[CHANNEL_X].NegativePulseWidth); + WAVE_GEN_BLK->WAVE_GEN_DRV_SILENT_T_REG = Pulse_Width; + return Pulse_Width; + } + else if(ParaSet_waveform[CHANNEL_X].ClientTime == 0) + { + Pulse_Width/*正+负脉宽*/ = (uint32_t)((1000000/freq) - ParaSet_waveform[CHANNEL_X].DeadTime) ; + if(ParaSet_waveform[CHANNEL_X].NegativePulseWidth == 0) + WAVE_GEN_BLK->WAVE_GEN_DRV_HLF_WAVE_PRD_REG = Pulse_Width; + else + { + WAVE_GEN_BLK->WAVE_GEN_DRV_HLF_WAVE_PRD_REG = (uint32_t) (Pulse_Width / 2) ; + WAVE_GEN_BLK->WAVE_GEN_DRV_NEG_HLF_WAVE_PRD_REG = (uint32_t) (Pulse_Width / 2) ; + } + return Pulse_Width; + } + else + { + return 0; + } +} + + +//电刺激时间计时 + +uint32_t StimuTimeCount_S(CHANNEL_NUM CHANNEL_X , TIME_COUNT_MODE MODE) +{ + uint32_t count_time = 0; + if(MODE == TOTAL_TIME_MODE) + { + count_time = *(CHANNEL_TIME_COUNT+CHANNEL_X) ; + } + else //MODE == TRIGGER_TIME_MODE 间隔时间 + { + count_time = *(TRIGGER_TIME_COUNT+CHANNEL_X); + } + return count_time; +} + +//返回当前波形发生了多少次（需要开启波形发生器的中断） +uint32_t waveformOccurreCount(CHANNEL_NUM CHANNEL_X) +{ + return (uint32_t)(wave_gen_irq_occurred[CHANNEL_X]/4); +} + +/*-------------------------------电刺激驱动器中断处理函数-----------------------*/ +volatile uint32_t NUM_OF_PULSES_THRESHOLD[4]={0,0,0,0}; +volatile uint32_t wave_gen_irq_occurred[4]={0,0,0,0}; +void WG_DRV_Handler(void) +{ + + CMSDK_WAVE_GEN_TypeDef *DRVA; + for(int i =0; i<4;i++) + { + if(i==0){ DRVA= WAVE_GEN_DRVA_BLK0; } + else if(i==1){ DRVA= WAVE_GEN_DRVA_BLK1; } + else if(i==2){ DRVA= WAVE_GEN_DRVA_BLK2; } + else if(i==3){ DRVA= WAVE_GEN_DRVA_BLK3; } + + if((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_READ_DRIVER_NUM_Msk) == i) //判断哪个通道发生了中断 + { + if((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_STS_Msk) == CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_STS_Msk)//第一中断点发生中断 + { + if(((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Msk)>>CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Pos) == 0) + { + if((NUM_OF_PULSES_THRESHOLD[i] > 0) && (wave_gen_irq_occurred[i] > (NUM_OF_PULSES_THRESHOLD[i]*4 - 2))) + DRVA->WAVE_GEN_DRV_INT_REG = (63 << CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Pos) | (0 << CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Pos) | CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Msk | CMSDK_WAVE_GEN_DRV_INT_EN_Msk; + else + DRVA->WAVE_GEN_DRV_INT_REG = (63 << CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Pos) | (32 << CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Pos) | CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Msk | CMSDK_WAVE_GEN_DRV_INT_EN_Msk; + } + else if(((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Msk)>>CMSDK_WAVE_GEN_DRV_INT_READ_FIRST_ADDR_Pos) == 32) + { + DRVA->WAVE_GEN_DRV_INT_REG = (31 << CMSDK_WAVE_GEN_DRV_INT_SECOND_ADDR_Pos) | (0 << CMSDK_WAVE_GEN_DRV_INT_FIRST_ADDR_Pos) | CMSDK_WAVE_GEN_DRV_INT_FIRSTADDR_CLR_Msk | CMSDK_WAVE_GEN_DRV_INT_EN_Msk; + } + if((NUM_OF_PULSES_THRESHOLD[i] > 0)) //需要脉冲计数功能才开启计数 + wave_gen_irq_occurred[i]++; + + + } + if((DRVA->WAVE_GEN_DRV_INT_REG & CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_STS_Msk) == CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_STS_Msk) + { + StopStimulatorOut((CHANNEL_NUM)i); + DRVA->WAVE_GEN_DRV_INT_REG = CMSDK_WAVE_GEN_DRV_INT_SECONDADDR_CLR_Msk | CMSDK_WAVE_GEN_DRV_INT_EN_Msk; + NVIC_DisableIRQ(WG_DRV_IRQn); + DRVA->WAVE_GEN_DRV_INT_REG = 0; + TRIGGER_TIME_COUNT_FLAG |= (1< +#include +#include +#include "CMSDK_CM0.h" +#pragma import(__use_no_semihosting_swi) + +//extern unsigned char UartGetc(void); +extern unsigned char UartPutc(CMSDK_UART_TypeDef *CMSDK_UART ,unsigned char my_ch); +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; + + +int fputc(int ch, FILE *f) { + return (UartPutc(CMSDK_UART1 ,ch)); +} + + +int ferror(FILE *f) { + /* Your implementation of ferror */ + return EOF; +} + +void _ttywrch(int ch) { + UartPutc (CMSDK_UART1 ,ch); +} + + +void _sys_exit(int return_code) { +label: goto label; /* endless loop */ +} + +#else + +/******************************************************************************/ +/* Retarget functions for GNU Tools for ARM Embedded Processors */ +/******************************************************************************/ +#include +#include + +extern unsigned char UartPutc(unsigned char my_ch); + +__attribute__ ((used)) int _write (int fd, char *ptr, int len) +{ + size_t i; + for (i=0; i>> ------------------ + 39 00000000 ;*/ + 40 00000000 + 41 00000000 + 42 00000000 ; Stack Configuration + 43 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 44 00000000 ; + 45 00000000 + 46 00000000 00000400 + Stack_Size + EQU 0x00000400 + 47 00000000 + 48 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 49 00000000 Stack_Mem + SPACE Stack_Size + 50 00000400 __initial_sp + 51 00000400 + 52 00000400 + 53 00000400 ; Heap Configuration + 54 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 55 00000400 ; + 56 00000400 + 57 00000400 00000C00 + Heap_Size + EQU 0x00000C00 + 58 00000400 + 59 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 60 00000000 __heap_base + 61 00000000 Heap_Mem + SPACE Heap_Size + 62 00000C00 __heap_limit + 63 00000C00 + 64 00000C00 + 65 00000C00 PRESERVE8 + 66 00000C00 THUMB + 67 00000C00 + 68 00000C00 + 69 00000C00 ; Vector Table Mapped to Address 0 at Reset + 70 00000C00 + 71 00000C00 AREA RESET, DATA, READONLY + 72 00000000 EXPORT __Vectors + 73 00000000 EXPORT __Vectors_End + 74 00000000 EXPORT __Vectors_Size + 75 00000000 + 76 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 77 00000004 00000000 DCD Reset_Handler ; Reset Handler + 78 00000008 00000000 DCD NMI_Handler ; NMI Handler + 79 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 80 00000010 00000000 DCD 0 ; Reserved + 81 00000014 00000000 DCD 0 ; Reserved + 82 00000018 00000000 DCD 0 ; Reserved + 83 0000001C 00000000 DCD 0 ; Reserved + 84 00000020 00000000 DCD 0 ; Reserved + + + +ARM Macro Assembler Page 3 + + + 85 00000024 00000000 DCD 0 ; Reserved + 86 00000028 00000000 DCD 0 ; Reserved + 87 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 88 00000030 00000000 DCD 0 ; Reserved + 89 00000034 00000000 DCD 0 ; Reserved + 90 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 91 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 92 00000040 + 93 00000040 ; External Interrupts + 94 00000040 00000000 DCD WDT_IRQHandler ; 0: Watchdog + Timer + 95 00000044 00000000 DCD RTC_IRQHandler ; 1: Real Time + Clock + 96 00000048 00000000 DCD TIM0_IRQHandler ; 2: Timer0 / + Timer1 + 97 0000004C 00000000 DCD TIM2_IRQHandler ; 3: Timer2 / + Timer3 + 98 00000050 00000000 DCD MCIA_IRQHandler ; 4: MCIa + 99 00000054 00000000 DCD MCIB_IRQHandler ; 5: MCIb + 100 00000058 00000000 DCD UART0_IRQHandler ; 6: UART0 - + DUT FPGA + 101 0000005C 00000000 DCD UART1_IRQHandler ; 7: UART1 - + DUT FPGA + 102 00000060 00000000 DCD UART2_IRQHandler ; 8: UART2 - + DUT FPGA + 103 00000064 00000000 DCD UART4_IRQHandler ; 9: UART4 - + not connected + 104 00000068 00000000 DCD AACI_IRQHandler + ; 10: AACI / AC97 + 105 0000006C 00000000 DCD CLCD_IRQHandler ; 11: CLCD Comb + ined Interrupt + 106 00000070 00000000 DCD ENET_IRQHandler ; 12: Ethernet + 107 00000074 00000000 DCD USBDC_IRQHandler + ; 13: USB Device + 108 00000078 00000000 DCD USBHC_IRQHandler ; 14: USB Host + Controller + 109 0000007C 00000000 DCD CHLCD_IRQHandler + ; 15: Character LCD + + 110 00000080 00000000 DCD FLEXRAY_IRQHandler + ; 16: Flexray + 111 00000084 00000000 DCD CAN_IRQHandler ; 17: CAN + 112 00000088 00000000 DCD LIN_IRQHandler ; 18: LIN + 113 0000008C 00000000 DCD I2C_IRQHandler + ; 19: I2C ADC/DAC + 114 00000090 00000000 DCD 0 ; 20: Reserved + 115 00000094 00000000 DCD 0 ; 21: Reserved + 116 00000098 00000000 DCD 0 ; 22: Reserved + 117 0000009C 00000000 DCD 0 ; 23: Reserved + 118 000000A0 00000000 DCD 0 ; 24: Reserved + 119 000000A4 00000000 DCD 0 ; 25: Reserved + 120 000000A8 00000000 DCD 0 ; 26: Reserved + 121 000000AC 00000000 DCD 0 ; 27: Reserved + 122 000000B0 00000000 DCD CPU_CLCD_IRQHandler ; 28: Reser + ved - CPU FPGA CLCD + + 123 000000B4 00000000 DCD 0 ; 29: Reserved - CP + + + +ARM Macro Assembler Page 4 + + + U FPGA + 124 000000B8 00000000 DCD UART3_IRQHandler ; 30: UART3 + - CPU FPGA + 125 000000BC 00000000 DCD SPI_IRQHandler ; 31: SPI Touchs + creen - CPU FPGA + 126 000000C0 __Vectors_End + 127 000000C0 + 128 000000C0 000000C0 + __Vectors_Size + EQU __Vectors_End - __Vectors + 129 000000C0 + 130 000000C0 AREA |.text|, CODE, READONLY + 131 00000000 + 132 00000000 + 133 00000000 ; Reset Handler + 134 00000000 + 135 00000000 Reset_Handler + PROC + 136 00000000 EXPORT Reset_Handler [WEAK +] + 137 00000000 IMPORT SystemInit + 138 00000000 IMPORT __main + 139 00000000 4807 LDR R0, =SystemInit + 140 00000002 4780 BLX R0 + 141 00000004 4807 LDR R0, =__main + 142 00000006 4700 BX R0 + 143 00000008 ENDP + 144 00000008 + 145 00000008 + 146 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 147 00000008 + 148 00000008 NMI_Handler + PROC + 149 00000008 EXPORT NMI_Handler [WEAK +] + 150 00000008 E7FE B . + 151 0000000A ENDP + 153 0000000A HardFault_Handler + PROC + 154 0000000A EXPORT HardFault_Handler [WEAK +] + 155 0000000A E7FE B . + 156 0000000C ENDP + 157 0000000C SVC_Handler + PROC + 158 0000000C EXPORT SVC_Handler [WEAK +] + 159 0000000C E7FE B . + 160 0000000E ENDP + 161 0000000E PendSV_Handler + PROC + 162 0000000E EXPORT PendSV_Handler [WEAK +] + 163 0000000E E7FE B . + 164 00000010 ENDP + 165 00000010 SysTick_Handler + PROC + 166 00000010 EXPORT SysTick_Handler [WEAK + + + +ARM Macro Assembler Page 5 + + +] + 167 00000010 E7FE B . + 168 00000012 ENDP + 169 00000012 + 170 00000012 Default_Handler + PROC + 171 00000012 + 172 00000012 EXPORT WDT_IRQHandler [WEAK +] + 173 00000012 EXPORT RTC_IRQHandler [WEAK +] + 174 00000012 EXPORT TIM0_IRQHandler [WEAK +] + 175 00000012 EXPORT TIM2_IRQHandler [WEAK +] + 176 00000012 EXPORT MCIA_IRQHandler [WEAK +] + 177 00000012 EXPORT MCIB_IRQHandler [WEAK +] + 178 00000012 EXPORT UART0_IRQHandler [WEAK +] + 179 00000012 EXPORT UART1_IRQHandler [WEAK +] + 180 00000012 EXPORT UART2_IRQHandler [WEAK +] + 181 00000012 EXPORT UART3_IRQHandler [WEAK +] + 182 00000012 EXPORT UART4_IRQHandler [WEAK +] + 183 00000012 EXPORT AACI_IRQHandler [WEAK +] + 184 00000012 EXPORT CLCD_IRQHandler [WEAK +] + 185 00000012 EXPORT ENET_IRQHandler [WEAK +] + 186 00000012 EXPORT USBDC_IRQHandler [WEAK +] + 187 00000012 EXPORT USBHC_IRQHandler [WEAK +] + 188 00000012 EXPORT CHLCD_IRQHandler [WEAK +] + 189 00000012 EXPORT FLEXRAY_IRQHandler [WEAK +] + 190 00000012 EXPORT CAN_IRQHandler [WEAK +] + 191 00000012 EXPORT LIN_IRQHandler [WEAK +] + 192 00000012 EXPORT I2C_IRQHandler [WEAK +] + 193 00000012 EXPORT CPU_CLCD_IRQHandler [WEAK +] + 194 00000012 EXPORT SPI_IRQHandler [WEAK +] + 195 00000012 + 196 00000012 WDT_IRQHandler + 197 00000012 RTC_IRQHandler + 198 00000012 TIM0_IRQHandler + 199 00000012 TIM2_IRQHandler + 200 00000012 MCIA_IRQHandler + + + +ARM Macro Assembler Page 6 + + + 201 00000012 MCIB_IRQHandler + 202 00000012 UART0_IRQHandler + 203 00000012 UART1_IRQHandler + 204 00000012 UART2_IRQHandler + 205 00000012 UART3_IRQHandler + 206 00000012 UART4_IRQHandler + 207 00000012 AACI_IRQHandler + 208 00000012 CLCD_IRQHandler + 209 00000012 ENET_IRQHandler + 210 00000012 USBDC_IRQHandler + 211 00000012 USBHC_IRQHandler + 212 00000012 CHLCD_IRQHandler + 213 00000012 FLEXRAY_IRQHandler + 214 00000012 CAN_IRQHandler + 215 00000012 LIN_IRQHandler + 216 00000012 I2C_IRQHandler + 217 00000012 CPU_CLCD_IRQHandler + 218 00000012 SPI_IRQHandler + 219 00000012 E7FE B . + 220 00000014 + 221 00000014 ENDP + 222 00000014 + 223 00000014 + 224 00000014 ALIGN + 225 00000014 + 226 00000014 + 227 00000014 ; User Initial Stack & Heap + 228 00000014 + 229 00000014 IF :DEF:__MICROLIB + 236 00000014 + 237 00000014 IMPORT __use_two_region_memory + 238 00000014 EXPORT __user_initial_stackheap + 239 00000014 + 240 00000014 __user_initial_stackheap + PROC + 241 00000014 4804 LDR R0, = Heap_Mem + 242 00000016 4905 LDR R1, =(Stack_Mem + Stack_Size) + 243 00000018 4A05 LDR R2, = (Heap_Mem + Heap_Size) + 244 0000001A 4B06 LDR R3, = Stack_Mem + 245 0000001C 4770 BX LR + 246 0000001E ENDP + 247 0000001E + 248 0000001E 00 00 ALIGN + 249 00000020 + 250 00000020 ENDIF + 251 00000020 + 252 00000020 + 253 00000020 END + 00000000 + 00000000 + 00000000 + 00000400 + 00000C00 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw +ork --depend=.\objects\startup_armcm0.d -o.\objects\startup_armcm0.o -IC:\Users +\admin\Desktop\---工作中---\0、重要内容：ENS驱动开发\程序\RTE\_ENS001_BASIC_PRJ + -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.0\Device\ARM\ARMCM0\Include -IC:\Keil_v5\A +RM\CMSIS\Include --predefine="__UVISION_VERSION SETA 522" --predefine="ARMCM0 S + + + +ARM Macro Assembler Page 7 + + +ETA 1" --list=.\listings\startup_armcm0.lst CORE\startup_ARMCM0.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 48 in file CORE\startup_ARMCM0.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 49 in file CORE\startup_ARMCM0.s + Uses + At line 242 in file CORE\startup_ARMCM0.s + At line 244 in file CORE\startup_ARMCM0.s + +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 50 in file CORE\startup_ARMCM0.s + Uses + At line 76 in file CORE\startup_ARMCM0.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 59 in file CORE\startup_ARMCM0.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 61 in file CORE\startup_ARMCM0.s + Uses + At line 241 in file CORE\startup_ARMCM0.s + At line 243 in file CORE\startup_ARMCM0.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 60 in file CORE\startup_ARMCM0.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000C00 + +Symbol: __heap_limit + Definitions + At line 62 in file CORE\startup_ARMCM0.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 71 in file CORE\startup_ARMCM0.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 76 in file CORE\startup_ARMCM0.s + Uses + At line 72 in file CORE\startup_ARMCM0.s + At line 128 in file CORE\startup_ARMCM0.s + +__Vectors_End 000000C0 + +Symbol: __Vectors_End + Definitions + At line 126 in file CORE\startup_ARMCM0.s + Uses + At line 73 in file CORE\startup_ARMCM0.s + At line 128 in file CORE\startup_ARMCM0.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 130 in file CORE\startup_ARMCM0.s + Uses + None +Comment: .text unused +AACI_IRQHandler 00000012 + +Symbol: AACI_IRQHandler + Definitions + At line 207 in file CORE\startup_ARMCM0.s + Uses + At line 104 in file CORE\startup_ARMCM0.s + At line 183 in file CORE\startup_ARMCM0.s + +CAN_IRQHandler 00000012 + +Symbol: CAN_IRQHandler + Definitions + At line 214 in file CORE\startup_ARMCM0.s + Uses + At line 111 in file CORE\startup_ARMCM0.s + At line 190 in file CORE\startup_ARMCM0.s + +CHLCD_IRQHandler 00000012 + +Symbol: CHLCD_IRQHandler + Definitions + At line 212 in file CORE\startup_ARMCM0.s + Uses + At line 109 in file CORE\startup_ARMCM0.s + At line 188 in file CORE\startup_ARMCM0.s + +CLCD_IRQHandler 00000012 + +Symbol: CLCD_IRQHandler + Definitions + At line 208 in file CORE\startup_ARMCM0.s + Uses + At line 105 in file CORE\startup_ARMCM0.s + At line 184 in file CORE\startup_ARMCM0.s + +CPU_CLCD_IRQHandler 00000012 + +Symbol: CPU_CLCD_IRQHandler + Definitions + At line 217 in file CORE\startup_ARMCM0.s + Uses + At line 122 in file CORE\startup_ARMCM0.s + At line 193 in file CORE\startup_ARMCM0.s + +Default_Handler 00000012 + +Symbol: Default_Handler + Definitions + At line 170 in file CORE\startup_ARMCM0.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + None +Comment: Default_Handler unused +ENET_IRQHandler 00000012 + +Symbol: ENET_IRQHandler + Definitions + At line 209 in file CORE\startup_ARMCM0.s + Uses + At line 106 in file CORE\startup_ARMCM0.s + At line 185 in file CORE\startup_ARMCM0.s + +FLEXRAY_IRQHandler 00000012 + +Symbol: FLEXRAY_IRQHandler + Definitions + At line 213 in file CORE\startup_ARMCM0.s + Uses + At line 110 in file CORE\startup_ARMCM0.s + At line 189 in file CORE\startup_ARMCM0.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 153 in file CORE\startup_ARMCM0.s + Uses + At line 79 in file CORE\startup_ARMCM0.s + At line 154 in file CORE\startup_ARMCM0.s + +I2C_IRQHandler 00000012 + +Symbol: I2C_IRQHandler + Definitions + At line 216 in file CORE\startup_ARMCM0.s + Uses + At line 113 in file CORE\startup_ARMCM0.s + At line 192 in file CORE\startup_ARMCM0.s + +LIN_IRQHandler 00000012 + +Symbol: LIN_IRQHandler + Definitions + At line 215 in file CORE\startup_ARMCM0.s + Uses + At line 112 in file CORE\startup_ARMCM0.s + At line 191 in file CORE\startup_ARMCM0.s + +MCIA_IRQHandler 00000012 + +Symbol: MCIA_IRQHandler + Definitions + At line 200 in file CORE\startup_ARMCM0.s + Uses + At line 98 in file CORE\startup_ARMCM0.s + At line 176 in file CORE\startup_ARMCM0.s + +MCIB_IRQHandler 00000012 + +Symbol: MCIB_IRQHandler + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 201 in file CORE\startup_ARMCM0.s + Uses + At line 99 in file CORE\startup_ARMCM0.s + At line 177 in file CORE\startup_ARMCM0.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 148 in file CORE\startup_ARMCM0.s + Uses + At line 78 in file CORE\startup_ARMCM0.s + At line 149 in file CORE\startup_ARMCM0.s + +PendSV_Handler 0000000E + +Symbol: PendSV_Handler + Definitions + At line 161 in file CORE\startup_ARMCM0.s + Uses + At line 90 in file CORE\startup_ARMCM0.s + At line 162 in file CORE\startup_ARMCM0.s + +RTC_IRQHandler 00000012 + +Symbol: RTC_IRQHandler + Definitions + At line 197 in file CORE\startup_ARMCM0.s + Uses + At line 95 in file CORE\startup_ARMCM0.s + At line 173 in file CORE\startup_ARMCM0.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 135 in file CORE\startup_ARMCM0.s + Uses + At line 77 in file CORE\startup_ARMCM0.s + At line 136 in file CORE\startup_ARMCM0.s + +SPI_IRQHandler 00000012 + +Symbol: SPI_IRQHandler + Definitions + At line 218 in file CORE\startup_ARMCM0.s + Uses + At line 125 in file CORE\startup_ARMCM0.s + At line 194 in file CORE\startup_ARMCM0.s + +SVC_Handler 0000000C + +Symbol: SVC_Handler + Definitions + At line 157 in file CORE\startup_ARMCM0.s + Uses + At line 87 in file CORE\startup_ARMCM0.s + At line 158 in file CORE\startup_ARMCM0.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +SysTick_Handler 00000010 + +Symbol: SysTick_Handler + Definitions + At line 165 in file CORE\startup_ARMCM0.s + Uses + At line 91 in file CORE\startup_ARMCM0.s + At line 166 in file CORE\startup_ARMCM0.s + +TIM0_IRQHandler 00000012 + +Symbol: TIM0_IRQHandler + Definitions + At line 198 in file CORE\startup_ARMCM0.s + Uses + At line 96 in file CORE\startup_ARMCM0.s + At line 174 in file CORE\startup_ARMCM0.s + +TIM2_IRQHandler 00000012 + +Symbol: TIM2_IRQHandler + Definitions + At line 199 in file CORE\startup_ARMCM0.s + Uses + At line 97 in file CORE\startup_ARMCM0.s + At line 175 in file CORE\startup_ARMCM0.s + +UART0_IRQHandler 00000012 + +Symbol: UART0_IRQHandler + Definitions + At line 202 in file CORE\startup_ARMCM0.s + Uses + At line 100 in file CORE\startup_ARMCM0.s + At line 178 in file CORE\startup_ARMCM0.s + +UART1_IRQHandler 00000012 + +Symbol: UART1_IRQHandler + Definitions + At line 203 in file CORE\startup_ARMCM0.s + Uses + At line 101 in file CORE\startup_ARMCM0.s + At line 179 in file CORE\startup_ARMCM0.s + +UART2_IRQHandler 00000012 + +Symbol: UART2_IRQHandler + Definitions + At line 204 in file CORE\startup_ARMCM0.s + Uses + At line 102 in file CORE\startup_ARMCM0.s + At line 180 in file CORE\startup_ARMCM0.s + +UART3_IRQHandler 00000012 + +Symbol: UART3_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 205 in file CORE\startup_ARMCM0.s + Uses + At line 124 in file CORE\startup_ARMCM0.s + At line 181 in file CORE\startup_ARMCM0.s + +UART4_IRQHandler 00000012 + +Symbol: UART4_IRQHandler + Definitions + At line 206 in file CORE\startup_ARMCM0.s + Uses + At line 103 in file CORE\startup_ARMCM0.s + At line 182 in file CORE\startup_ARMCM0.s + +USBDC_IRQHandler 00000012 + +Symbol: USBDC_IRQHandler + Definitions + At line 210 in file CORE\startup_ARMCM0.s + Uses + At line 107 in file CORE\startup_ARMCM0.s + At line 186 in file CORE\startup_ARMCM0.s + +USBHC_IRQHandler 00000012 + +Symbol: USBHC_IRQHandler + Definitions + At line 211 in file CORE\startup_ARMCM0.s + Uses + At line 108 in file CORE\startup_ARMCM0.s + At line 187 in file CORE\startup_ARMCM0.s + +WDT_IRQHandler 00000012 + +Symbol: WDT_IRQHandler + Definitions + At line 196 in file CORE\startup_ARMCM0.s + Uses + At line 94 in file CORE\startup_ARMCM0.s + At line 172 in file CORE\startup_ARMCM0.s + +__user_initial_stackheap 00000014 + +Symbol: __user_initial_stackheap + Definitions + At line 240 in file CORE\startup_ARMCM0.s + Uses + At line 238 in file CORE\startup_ARMCM0.s +Comment: __user_initial_stackheap used once +32 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000C00 + +Symbol: Heap_Size + Definitions + At line 57 in file CORE\startup_ARMCM0.s + Uses + At line 61 in file CORE\startup_ARMCM0.s + At line 243 in file CORE\startup_ARMCM0.s + +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 46 in file CORE\startup_ARMCM0.s + Uses + At line 49 in file CORE\startup_ARMCM0.s + At line 242 in file CORE\startup_ARMCM0.s + +__Vectors_Size 000000C0 + +Symbol: __Vectors_Size + Definitions + At line 128 in file CORE\startup_ARMCM0.s + Uses + At line 74 in file CORE\startup_ARMCM0.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 137 in file CORE\startup_ARMCM0.s + Uses + At line 139 in file CORE\startup_ARMCM0.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 138 in file CORE\startup_ARMCM0.s + Uses + At line 141 in file CORE\startup_ARMCM0.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 237 in file CORE\startup_ARMCM0.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +384 symbols in table diff --git a/Listings/startup_cmsdk_cm0.lst b/Listings/startup_cmsdk_cm0.lst new file mode 100644 index 0000000..0bd29a9 --- /dev/null +++ b/Listings/startup_cmsdk_cm0.lst @@ -0,0 +1,804 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;/****************************************************** + ********************//** + 2 00000000 ; * @file startup_CMSDK_CM0.s + 3 00000000 ; * @brief CMSIS Cortex-M0 Core Device Startup File f + or + 4 00000000 ; * Device CMSDK_CM0 + 5 00000000 ; * @version V3.01 + 6 00000000 ; * @date 06. March 2012 + 7 00000000 ; * + 8 00000000 ; * @note + 9 00000000 ; * Copyright (C) 2012 ARM Limited. All rights reserved. + + 10 00000000 ; * + 11 00000000 ; * @par + 12 00000000 ; * ARM Limited (ARM) is supplying this software for use + with Cortex-M + 13 00000000 ; * processor based microcontrollers. This file can be + freely distributed + 14 00000000 ; * within development tools that are supporting such AR + M based processors. + 15 00000000 ; * + 16 00000000 ; * @par + 17 00000000 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, W + HETHER EXPRESS, IMPLIED + 18 00000000 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED + WARRANTIES OF + 19 00000000 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + APPLY TO THIS SOFTWARE. + 20 00000000 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR S + PECIAL, INCIDENTAL, OR + 21 00000000 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + 22 00000000 ; * + 23 00000000 ; ****************************************************** + ************************/ + 24 00000000 ;/* + 25 00000000 ;//-------- <<< Use Configuration Wizard in Context Menu + >>> ------------------ + 26 00000000 ;*/ + 27 00000000 + 28 00000000 + 29 00000000 ; Stack Configuration + 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 31 00000000 ; + 32 00000000 + 33 00000000 00000200 + Stack_Size + EQU 0x00000200 + 34 00000000 + 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 36 00000000 Stack_Mem + SPACE Stack_Size + 37 00000200 __initial_sp + 38 00000200 + 39 00000200 + 40 00000200 ; Heap Configuration + 41 00000200 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 42 00000200 ; + 43 00000200 + + + +ARM Macro Assembler Page 2 + + + 44 00000200 00000100 + Heap_Size + EQU 0x00000100 + 45 00000200 + 46 00000200 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 47 00000000 __heap_base + 48 00000000 Heap_Mem + SPACE Heap_Size + 49 00000100 __heap_limit + 50 00000100 + 51 00000100 + 52 00000100 PRESERVE8 + 53 00000100 THUMB + 54 00000100 + 55 00000100 + 56 00000100 ; Vector Table Mapped to Address 0 at Reset + 57 00000100 + 58 00000100 AREA RESET, DATA, READONLY + 59 00000000 EXPORT __Vectors + 60 00000000 EXPORT __Vectors_End + 61 00000000 EXPORT __Vectors_Size + 62 00000000 + 63 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 64 00000004 00000000 DCD Reset_Handler ; Reset Handler + 65 00000008 00000000 DCD NMI_Handler ; NMI Handler + 66 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 67 00000010 00000000 DCD 0 ; Reserved + 68 00000014 00000000 DCD 0 ; Reserved + 69 00000018 00000000 DCD 0 ; Reserved + 70 0000001C 00000000 DCD 0 ; Reserved + 71 00000020 00000000 DCD 0 ; Reserved + 72 00000024 00000000 DCD 0 ; Reserved + 73 00000028 00000000 DCD 0 ; Reserved + 74 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 75 00000030 00000000 DCD 0 ; Reserved + 76 00000034 00000000 DCD 0 ; Reserved + 77 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 78 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 79 00000040 00000000 DCD LVD_Handler ; + 80 00000044 00000000 DCD RTC_Handler ; + 81 00000048 00000000 DCD COMP0_Handler ; + 82 0000004C 00000000 DCD COMP1_Handler ; + 83 00000050 00000000 DCD GPIO0_7_Handler ; + 84 00000054 00000000 DCD GPIO8_15_Handler ; + 85 00000058 00000000 DCD GPIO16_23_Handler ; + 86 0000005C 00000000 DCD MTP_Handler ; + 87 00000060 00000000 DCD CHARGER_OK_Handler ; + 88 00000064 00000000 DCD CHARGER_END_Handler ; + 89 00000068 00000000 DCD ADC_Handler ; + 90 0000006C 00000000 DCD LCD_Handler ; + 91 00000070 00000000 DCD UART0_Handler ; + 92 00000074 00000000 DCD UART1_Handler ; + 93 00000078 00000000 DCD SPI0_Handler ; + + + +ARM Macro Assembler Page 3 + + + 94 0000007C 00000000 DCD SPI1_Handler ; + 95 00000080 00000000 DCD I2C0_Event_Handler ; + 96 00000084 00000000 DCD I2C0_Error_Handler ; + 97 00000088 00000000 DCD I2C1_Event_Handler ; + 98 0000008C 00000000 DCD I2C1_Error_Handler ; + 99 00000090 00000000 DCD PWM_Handler ; + 100 00000094 00000000 DCD TIMER0_Handler ; + 101 00000098 00000000 DCD TIMER1_Handler ; + 102 0000009C 00000000 DCD DUALTIMER_Handler ; + 103 000000A0 00000000 DCD OVER_TEMP_Handler ; + 104 000000A4 00000000 DCD WG_DRV_Handler ; + 105 000000A8 00000000 DCD 0 ; + 106 000000AC 00000000 DCD 0 ; + 107 000000B0 00000000 DCD 0 ; + 108 000000B4 00000000 DCD 0 ; + 109 000000B8 00000000 DCD 0 ; + 110 000000BC 00000000 DCD 0 ; + 111 000000C0 __Vectors_End + 112 000000C0 + 113 000000C0 000000C0 + __Vectors_Size + EQU __Vectors_End - __Vectors + 114 000000C0 + 115 000000C0 AREA |.text|, CODE, READONLY + 116 00000000 + 117 00000000 + 118 00000000 ; Reset Handler + 119 00000000 + 120 00000000 Reset_Handler + PROC + 121 00000000 EXPORT Reset_Handler [WEAK +] + 122 00000000 IMPORT SystemInit + 123 00000000 IMPORT __main + 124 00000000 4804 LDR R0, =SystemInit + 125 00000002 4780 BLX R0 + 126 00000004 4804 LDR R0, =__main + 127 00000006 4700 BX R0 + 128 00000008 ENDP + 129 00000008 + 130 00000008 + 131 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 132 00000008 + 133 00000008 NMI_Handler + PROC + 134 00000008 EXPORT NMI_Handler [WEAK +] + 135 00000008 E7FE B . + 136 0000000A ENDP + 138 0000000A HardFault_Handler + PROC + 139 0000000A EXPORT HardFault_Handler [WEAK +] + 140 0000000A E7FE B . + 141 0000000C ENDP + 142 0000000C SVC_Handler + PROC + 143 0000000C EXPORT SVC_Handler [WEAK + + + +ARM Macro Assembler Page 4 + + +] + 144 0000000C E7FE B . + 145 0000000E ENDP + 146 0000000E PendSV_Handler + PROC + 147 0000000E EXPORT PendSV_Handler [WEAK +] + 148 0000000E E7FE B . + 149 00000010 ENDP + 150 00000010 SysTick_Handler + PROC + 151 00000010 EXPORT SysTick_Handler [WEA +K] + 152 00000010 E7FE B . + 153 00000012 ENDP + 154 00000012 Default_Handler + PROC + 155 00000012 EXPORT LVD_Handler [WEAK] + 156 00000012 EXPORT RTC_Handler [WEAK] + 157 00000012 EXPORT COMP0_Handler [WEAK] + 158 00000012 EXPORT COMP1_Handler [WEAK] + 159 00000012 EXPORT GPIO0_7_Handler [WEAK] + 160 00000012 EXPORT GPIO8_15_Handler [WEAK] + 161 00000012 EXPORT GPIO16_23_Handler [WEAK] + 162 00000012 EXPORT MTP_Handler [WEAK] + 163 00000012 EXPORT CHARGER_OK_Handler [WEAK] + 164 00000012 EXPORT CHARGER_END_Handler [WEAK] + 165 00000012 EXPORT ADC_Handler [WEAK] + 166 00000012 EXPORT LCD_Handler [WEAK] + 167 00000012 EXPORT UART0_Handler [WEAK] + 168 00000012 EXPORT UART1_Handler [WEAK] + 169 00000012 EXPORT SPI0_Handler [WEAK] + 170 00000012 EXPORT SPI1_Handler [WEAK] + 171 00000012 EXPORT I2C0_Event_Handler [WEAK] + 172 00000012 EXPORT I2C0_Error_Handler [WEAK] + 173 00000012 EXPORT I2C1_Event_Handler [WEAK] + 174 00000012 EXPORT I2C1_Error_Handler [WEAK] + 175 00000012 EXPORT PWM_Handler [WEAK] + 176 00000012 EXPORT TIMER0_Handler [WEAK] + 177 00000012 EXPORT TIMER1_Handler [WEAK] + 178 00000012 EXPORT DUALTIMER_Handler [WEAK] + 179 00000012 EXPORT OVER_TEMP_Handler [WEAK] + 180 00000012 EXPORT WG_DRV_Handler [WEAK] + 181 00000012 LVD_Handler + 182 00000012 RTC_Handler + 183 00000012 COMP0_Handler + 184 00000012 COMP1_Handler + 185 00000012 GPIO0_7_Handler + 186 00000012 GPIO8_15_Handler + 187 00000012 GPIO16_23_Handler + 188 00000012 MTP_Handler + 189 00000012 CHARGER_OK_Handler + 190 00000012 CHARGER_END_Handler + 191 00000012 ADC_Handler + 192 00000012 LCD_Handler + 193 00000012 UART0_Handler + 194 00000012 UART1_Handler + 195 00000012 SPI0_Handler + 196 00000012 SPI1_Handler + + + +ARM Macro Assembler Page 5 + + + 197 00000012 I2C0_Event_Handler + 198 00000012 I2C0_Error_Handler + 199 00000012 I2C1_Event_Handler + 200 00000012 I2C1_Error_Handler + 201 00000012 PWM_Handler + 202 00000012 TIMER0_Handler + 203 00000012 TIMER1_Handler + 204 00000012 DUALTIMER_Handler + 205 00000012 OVER_TEMP_Handler + 206 00000012 WG_DRV_Handler + 207 00000012 E7FE B . + 208 00000014 ENDP + 209 00000014 + 210 00000014 + 211 00000014 ALIGN + 212 00000014 + 213 00000014 + 214 00000014 ; User Initial Stack & Heap + 215 00000014 + 216 00000014 IF :DEF:__MICROLIB + 217 00000014 + 218 00000014 EXPORT __initial_sp + 219 00000014 EXPORT __heap_base + 220 00000014 EXPORT __heap_limit + 221 00000014 + 222 00000014 ELSE + 237 ENDIF + 238 00000014 + 239 00000014 + 240 00000014 END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw +ork --depend=.\objects\startup_cmsdk_cm0.d -o.\objects\startup_cmsdk_cm0.o -ID: +\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\ +Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include --predefine="__MICROLIB SE +TA 1" --predefine="__UVISION_VERSION SETA 538" --predefine="ARMCM0 SETA 1" --li +st=.\listings\startup_cmsdk_cm0.lst CORE\ARM\startup_CMSDK_CM0.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 35 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 36 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00000200 + +Symbol: __initial_sp + Definitions + At line 37 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 63 in file CORE\ARM\startup_CMSDK_CM0.s + At line 218 in file CORE\ARM\startup_CMSDK_CM0.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 46 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 48 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 47 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 219 in file CORE\ARM\startup_CMSDK_CM0.s +Comment: __heap_base used once +__heap_limit 00000100 + +Symbol: __heap_limit + Definitions + At line 49 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 220 in file CORE\ARM\startup_CMSDK_CM0.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 58 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 63 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 59 in file CORE\ARM\startup_CMSDK_CM0.s + At line 113 in file CORE\ARM\startup_CMSDK_CM0.s + +__Vectors_End 000000C0 + +Symbol: __Vectors_End + Definitions + At line 111 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 60 in file CORE\ARM\startup_CMSDK_CM0.s + At line 113 in file CORE\ARM\startup_CMSDK_CM0.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 115 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + None +Comment: .text unused +ADC_Handler 00000012 + +Symbol: ADC_Handler + Definitions + At line 191 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 89 in file CORE\ARM\startup_CMSDK_CM0.s + At line 165 in file CORE\ARM\startup_CMSDK_CM0.s + +CHARGER_END_Handler 00000012 + +Symbol: CHARGER_END_Handler + Definitions + At line 190 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 88 in file CORE\ARM\startup_CMSDK_CM0.s + At line 164 in file CORE\ARM\startup_CMSDK_CM0.s + +CHARGER_OK_Handler 00000012 + +Symbol: CHARGER_OK_Handler + Definitions + At line 189 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 87 in file CORE\ARM\startup_CMSDK_CM0.s + At line 163 in file CORE\ARM\startup_CMSDK_CM0.s + +COMP0_Handler 00000012 + +Symbol: COMP0_Handler + Definitions + At line 183 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 81 in file CORE\ARM\startup_CMSDK_CM0.s + At line 157 in file CORE\ARM\startup_CMSDK_CM0.s + +COMP1_Handler 00000012 + +Symbol: COMP1_Handler + Definitions + At line 184 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 82 in file CORE\ARM\startup_CMSDK_CM0.s + At line 158 in file CORE\ARM\startup_CMSDK_CM0.s + +DUALTIMER_Handler 00000012 + +Symbol: DUALTIMER_Handler + Definitions + At line 204 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 102 in file CORE\ARM\startup_CMSDK_CM0.s + At line 178 in file CORE\ARM\startup_CMSDK_CM0.s + +Default_Handler 00000012 + +Symbol: Default_Handler + Definitions + At line 154 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + None +Comment: Default_Handler unused +GPIO0_7_Handler 00000012 + +Symbol: GPIO0_7_Handler + Definitions + At line 185 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 83 in file CORE\ARM\startup_CMSDK_CM0.s + At line 159 in file CORE\ARM\startup_CMSDK_CM0.s + +GPIO16_23_Handler 00000012 + +Symbol: GPIO16_23_Handler + Definitions + At line 187 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 85 in file CORE\ARM\startup_CMSDK_CM0.s + At line 161 in file CORE\ARM\startup_CMSDK_CM0.s + +GPIO8_15_Handler 00000012 + +Symbol: GPIO8_15_Handler + Definitions + At line 186 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 84 in file CORE\ARM\startup_CMSDK_CM0.s + At line 160 in file CORE\ARM\startup_CMSDK_CM0.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 138 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 66 in file CORE\ARM\startup_CMSDK_CM0.s + At line 139 in file CORE\ARM\startup_CMSDK_CM0.s + +I2C0_Error_Handler 00000012 + +Symbol: I2C0_Error_Handler + Definitions + At line 198 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 96 in file CORE\ARM\startup_CMSDK_CM0.s + At line 172 in file CORE\ARM\startup_CMSDK_CM0.s + +I2C0_Event_Handler 00000012 + +Symbol: I2C0_Event_Handler + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 197 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 95 in file CORE\ARM\startup_CMSDK_CM0.s + At line 171 in file CORE\ARM\startup_CMSDK_CM0.s + +I2C1_Error_Handler 00000012 + +Symbol: I2C1_Error_Handler + Definitions + At line 200 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 98 in file CORE\ARM\startup_CMSDK_CM0.s + At line 174 in file CORE\ARM\startup_CMSDK_CM0.s + +I2C1_Event_Handler 00000012 + +Symbol: I2C1_Event_Handler + Definitions + At line 199 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 97 in file CORE\ARM\startup_CMSDK_CM0.s + At line 173 in file CORE\ARM\startup_CMSDK_CM0.s + +LCD_Handler 00000012 + +Symbol: LCD_Handler + Definitions + At line 192 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 90 in file CORE\ARM\startup_CMSDK_CM0.s + At line 166 in file CORE\ARM\startup_CMSDK_CM0.s + +LVD_Handler 00000012 + +Symbol: LVD_Handler + Definitions + At line 181 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 79 in file CORE\ARM\startup_CMSDK_CM0.s + At line 155 in file CORE\ARM\startup_CMSDK_CM0.s + +MTP_Handler 00000012 + +Symbol: MTP_Handler + Definitions + At line 188 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 86 in file CORE\ARM\startup_CMSDK_CM0.s + At line 162 in file CORE\ARM\startup_CMSDK_CM0.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 133 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 65 in file CORE\ARM\startup_CMSDK_CM0.s + At line 134 in file CORE\ARM\startup_CMSDK_CM0.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +OVER_TEMP_Handler 00000012 + +Symbol: OVER_TEMP_Handler + Definitions + At line 205 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 103 in file CORE\ARM\startup_CMSDK_CM0.s + At line 179 in file CORE\ARM\startup_CMSDK_CM0.s + +PWM_Handler 00000012 + +Symbol: PWM_Handler + Definitions + At line 201 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 99 in file CORE\ARM\startup_CMSDK_CM0.s + At line 175 in file CORE\ARM\startup_CMSDK_CM0.s + +PendSV_Handler 0000000E + +Symbol: PendSV_Handler + Definitions + At line 146 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 77 in file CORE\ARM\startup_CMSDK_CM0.s + At line 147 in file CORE\ARM\startup_CMSDK_CM0.s + +RTC_Handler 00000012 + +Symbol: RTC_Handler + Definitions + At line 182 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 80 in file CORE\ARM\startup_CMSDK_CM0.s + At line 156 in file CORE\ARM\startup_CMSDK_CM0.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 120 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 64 in file CORE\ARM\startup_CMSDK_CM0.s + At line 121 in file CORE\ARM\startup_CMSDK_CM0.s + +SPI0_Handler 00000012 + +Symbol: SPI0_Handler + Definitions + At line 195 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 93 in file CORE\ARM\startup_CMSDK_CM0.s + At line 169 in file CORE\ARM\startup_CMSDK_CM0.s + +SPI1_Handler 00000012 + +Symbol: SPI1_Handler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 196 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 94 in file CORE\ARM\startup_CMSDK_CM0.s + At line 170 in file CORE\ARM\startup_CMSDK_CM0.s + +SVC_Handler 0000000C + +Symbol: SVC_Handler + Definitions + At line 142 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 74 in file CORE\ARM\startup_CMSDK_CM0.s + At line 143 in file CORE\ARM\startup_CMSDK_CM0.s + +SysTick_Handler 00000010 + +Symbol: SysTick_Handler + Definitions + At line 150 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 78 in file CORE\ARM\startup_CMSDK_CM0.s + At line 151 in file CORE\ARM\startup_CMSDK_CM0.s + +TIMER0_Handler 00000012 + +Symbol: TIMER0_Handler + Definitions + At line 202 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 100 in file CORE\ARM\startup_CMSDK_CM0.s + At line 176 in file CORE\ARM\startup_CMSDK_CM0.s + +TIMER1_Handler 00000012 + +Symbol: TIMER1_Handler + Definitions + At line 203 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 101 in file CORE\ARM\startup_CMSDK_CM0.s + At line 177 in file CORE\ARM\startup_CMSDK_CM0.s + +UART0_Handler 00000012 + +Symbol: UART0_Handler + Definitions + At line 193 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 91 in file CORE\ARM\startup_CMSDK_CM0.s + At line 167 in file CORE\ARM\startup_CMSDK_CM0.s + +UART1_Handler 00000012 + +Symbol: UART1_Handler + Definitions + At line 194 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 92 in file CORE\ARM\startup_CMSDK_CM0.s + At line 168 in file CORE\ARM\startup_CMSDK_CM0.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +WG_DRV_Handler 00000012 + +Symbol: WG_DRV_Handler + Definitions + At line 206 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 104 in file CORE\ARM\startup_CMSDK_CM0.s + At line 180 in file CORE\ARM\startup_CMSDK_CM0.s + +34 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000100 + +Symbol: Heap_Size + Definitions + At line 44 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 48 in file CORE\ARM\startup_CMSDK_CM0.s +Comment: Heap_Size used once +Stack_Size 00000200 + +Symbol: Stack_Size + Definitions + At line 33 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 36 in file CORE\ARM\startup_CMSDK_CM0.s +Comment: Stack_Size used once +__Vectors_Size 000000C0 + +Symbol: __Vectors_Size + Definitions + At line 113 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 61 in file CORE\ARM\startup_CMSDK_CM0.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 122 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 124 in file CORE\ARM\startup_CMSDK_CM0.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 123 in file CORE\ARM\startup_CMSDK_CM0.s + Uses + At line 126 in file CORE\ARM\startup_CMSDK_CM0.s +Comment: __main used once +2 symbols +384 symbols in table diff --git a/Objects/ENS001_BASIC_PRJ.axf b/Objects/ENS001_BASIC_PRJ.axf new file mode 100644 index 0000000..c53d242 Binary files /dev/null and b/Objects/ENS001_BASIC_PRJ.axf differ diff --git a/Objects/ENS001_BASIC_PRJ.build_log.htm b/Objects/ENS001_BASIC_PRJ.build_log.htm new file mode 100644 index 0000000..3a0dc77 --- /dev/null +++ b/Objects/ENS001_BASIC_PRJ.build_log.htm @@ -0,0 +1,46 @@ + + +
+
礦ision Build Log

+
Tool Versions:

+IDE-Version: μVision V5.38.0.0
+Copyright (C) 2022 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: rick chen, hangzhouQX, LIC=RC93N-YY58Z-RAADM-X0YVM-V5YIY-0QTVL
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Plus  Version: 5.38.0.0
+Toolchain Path:  D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.38.0.0
+Dialog DLL:      DARMCM1.DLL V1.19.6.0
+Target DLL:      Segger\JL2CM3.dll V2.99.42.0
+Dialog DLL:      TARMCM1.DLL V1.14.6.0
+ 
+
Project:

+E:\Workspace\TIMER_DEMO\ENS001_BASIC_PRJ.uvprojx
+Project File Date:  08/13/2025
+
+
Output:

+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin'
+Build target 'ENS001_BASIC_PRJ'
+".\Objects\ENS001_BASIC_PRJ.axf" - 0 Error(s), 0 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: ARM
+                https://www.keil.com/pack/ARM.Cortex_DFP.1.1.0.pack
+                ARM.Cortex_DFP.1.1.0
+                ARM Cortex Reference Subsystems Device Family Pack
+
+
Collection of Component include folders:

+  D:/Keil_v5/ARM/Packs/ARM/Cortex_DFP/1.1.0/Device/ARMCM0/Include
+
+
Collection of Component Files used:

+Build Time Elapsed:  00:00:00
+
+ + diff --git a/Objects/ENS001_BASIC_PRJ.hex b/Objects/ENS001_BASIC_PRJ.hex new file mode 100644 index 0000000..1b05efd --- /dev/null +++ b/Objects/ENS001_BASIC_PRJ.hex @@ -0,0 +1,465 @@ +:020000041000EA +:1000000048020020D5000010DD000010DF000010C5 +:1000100000000000000000000000000000000000E0 +:10002000000000000000000000000000E1000010DF +:100030000000000000000000E3000010E5000010D8 +:10004000E7000010E7000010E7000010E7000010D4 +:10005000E7000010E7000010E7000010E7000010C4 +:10006000E7000010E7000010E7000010E7000010B4 +:100070003D0C0010A90C0010E7000010E700001074 +:10008000E7000010E7000010E7000010E700001094 +:10009000E70000108D0B0010210C0010E70000108D +:1000A000E7000010E7000010000000000000000062 +:1000B0000000000000000000000000000000000040 +:1000C0000348854600F096FA004800475111001099 +:1000D000480200200448804704480047FEE7FEE746 +:1000E000FEE7FEE7FEE7FEE77D0B0010C100001013 +:1000F00030B50B46014600202022012409E00D46C0 +:10010000D5409D4205D31D469540491B2546954047 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+:101C9000020001000000000000C20100000000007E +:101CA000000000200500000000000000000300000C +:101CB0000000000000000000000000000000000024 +:101CC00000000000000000000000000000E1F50539 +:081CD00000E1F5050000000031 +:04000005100000C126 +:00000001FF diff --git a/Objects/ENS001_BASIC_PRJ.htm b/Objects/ENS001_BASIC_PRJ.htm new file mode 100644 index 0000000..775cbf6 --- /dev/null +++ b/Objects/ENS001_BASIC_PRJ.htm @@ -0,0 +1,703 @@ + + +Static Call Graph - [.\Objects\ENS001_BASIC_PRJ.axf] +
+

Static Call Graph for image .\Objects\ENS001_BASIC_PRJ.axf

+

#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Wed Aug 13 16:25:22 2025 +

+

Maximum Stack Usage = 352 bytes + Unknown(Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+main ⇒ ClockInit ⇒ ClockInitSet ⇒ pow ⇒ __kernel_poly ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsl +

+

+Mutually Recursive functions +

  • NMI_Handler   ⇒   NMI_Handler
    +
  • HardFault_Handler   ⇒   HardFault_Handler
    +
  • SVC_Handler   ⇒   SVC_Handler
    +
  • PendSV_Handler   ⇒   PendSV_Handler
    +
  • SysTick_Handler   ⇒   SysTick_Handler
    +
  • ADC_Handler   ⇒   ADC_Handler
    + +

    +

    +Function Pointers +

      +
    • ADC_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • CHARGER_END_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • CHARGER_OK_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • COMP0_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • COMP1_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • DUALTIMER_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • GPIO0_7_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • GPIO16_23_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • GPIO8_15_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • HardFault_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • I2C0_Error_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • I2C0_Event_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • I2C1_Error_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • I2C1_Event_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • LCD_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • LVD_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • MTP_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • NMI_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • OVER_TEMP_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • PWM_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • PendSV_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • RTC_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • Reset_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • SPI0_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • SPI1_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • SVC_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • SysTick_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • SystemInit from system_cmsdk_cm0.o(i.SystemInit) referenced from startup_cmsdk_cm0.o(.text) +
    • TIMER0_Handler from ens1_timer.o(i.TIMER0_Handler) referenced from startup_cmsdk_cm0.o(RESET) +
    • TIMER1_Handler from ens1_timer.o(i.TIMER1_Handler) referenced from startup_cmsdk_cm0.o(RESET) +
    • UART0_Handler from ens1_uart.o(i.UART0_Handler) referenced from startup_cmsdk_cm0.o(RESET) +
    • UART1_Handler from ens1_uart.o(i.UART1_Handler) referenced from startup_cmsdk_cm0.o(RESET) +
    • WG_DRV_Handler from startup_cmsdk_cm0.o(.text) referenced from startup_cmsdk_cm0.o(RESET) +
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_cmsdk_cm0.o(.text) +
    • fputc from retarget.o(i.fputc) referenced from printf1.o(i.__0printf$1) +
    • main from mian.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(.text) +
    +

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) + +

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Calls]

    • >>   __scatterload +
    + +

    __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Called By]

    • >>   __scatterload +
    + +

    _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) + +

    _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) + +

    _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) + +

    __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D)) + +

    __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F)) + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +

    [Calls]

    • >>   NMI_Handler +
    +
    [Called By]
    • >>   NMI_Handler +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +

    [Calls]

    • >>   HardFault_Handler +
    +
    [Called By]
    • >>   HardFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +

    [Calls]

    • >>   SVC_Handler +
    +
    [Called By]
    • >>   SVC_Handler +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +

    [Calls]

    • >>   PendSV_Handler +
    +
    [Called By]
    • >>   PendSV_Handler +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +

    [Calls]

    • >>   SysTick_Handler +
    +
    [Called By]
    • >>   SysTick_Handler +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    ADC_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +

    [Calls]

    • >>   ADC_Handler +
    +
    [Called By]
    • >>   ADC_Handler +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    CHARGER_END_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    CHARGER_OK_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    COMP0_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    COMP1_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    DUALTIMER_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    GPIO0_7_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    GPIO16_23_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    GPIO8_15_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    I2C0_Error_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    I2C0_Event_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    I2C1_Error_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    I2C1_Event_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    LCD_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    LVD_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    MTP_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    OVER_TEMP_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    PWM_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    RTC_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    SPI0_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    SPI1_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    WG_DRV_Handler (Thumb, 0 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 12 bytes, uidiv.o(.text), UNUSED) + +

    __aeabi_uidivmod (Thumb, 44 bytes, Stack size 12 bytes, uidiv.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = __aeabi_uidivmod +
    +
    [Called By]
    • >>   TIMER0_Handler +
    • >>   UART_Init +
    • >>   TIMER0_Init +
    • >>   _printf_core +
    + +

    __aeabi_ddiv (Thumb, 234 bytes, Stack size 40 bytes, ddiv.o(.text)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = __aeabi_ddiv ⇒ _double_round +
    +
    [Calls]
    • >>   _double_round +
    +
    [Called By]
    • >>   pow +
    • >>   ClockInitSet +
    • >>   __mathlib_dbl_invalid +
    • >>   __mathlib_dbl_divzero +
    + +

    __aeabi_i2d (Thumb, 34 bytes, Stack size 16 bytes, dflti.o(.text)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = __aeabi_i2d ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   pow +
    • >>   ClockInitSet +
    + +

    __aeabi_ui2d (Thumb, 24 bytes, Stack size 16 bytes, dfltui.o(.text)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = __aeabi_ui2d ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   ClockInitSet +
    + +

    __aeabi_d2uiz (Thumb, 50 bytes, Stack size 8 bytes, dfixui.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_d2uiz ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_llsr +
    +
    [Called By]
    • >>   ClockInitSet +
    + +

    __aeabi_llsr (Thumb, 34 bytes, Stack size 8 bytes, llushr.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_llsr +
    +
    [Called By]
    • >>   __aeabi_d2uiz +
    • >>   _dsqrt +
    • >>   _double_epilogue +
    + +

    _ll_ushift_r (Thumb, 0 bytes, Stack size 8 bytes, llushr.o(.text), UNUSED) + +

    __I$use$fp (Thumb, 0 bytes, Stack size 8 bytes, iusefp.o(.text), UNUSED) + +

    _double_round (Thumb, 26 bytes, Stack size 8 bytes, depilogue.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = _double_round +
    +
    [Called By]
    • >>   __aeabi_dadd +
    • >>   __aeabi_ddiv +
    • >>   _dsqrt +
    • >>   _double_epilogue +
    + +

    _double_epilogue (Thumb, 164 bytes, Stack size 48 bytes, depilogue.o(.text)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   __aeabi_llsl +
    • >>   __ARM_clz +
    • >>   __aeabi_llsr +
    • >>   _double_round +
    +
    [Called By]
    • >>   __aeabi_dmul +
    • >>   __aeabi_dadd +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_i2d +
    + +

    __aeabi_dadd (Thumb, 328 bytes, Stack size 48 bytes, dadd.o(.text)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   __aeabi_lasr +
    • >>   __aeabi_llsl +
    • >>   _double_epilogue +
    • >>   _double_round +
    +
    [Called By]
    • >>   __aeabi_dsub +
    • >>   __aeabi_drsub +
    • >>   pow +
    • >>   __kernel_poly +
    • >>   __mathlib_dbl_infnan2 +
    + +

    __aeabi_dsub (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = __aeabi_dsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   pow +
    + +

    __aeabi_drsub (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   pow +
    + +

    __aeabi_dmul (Thumb, 202 bytes, Stack size 72 bytes, dmul.o(.text)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   pow +
    • >>   __kernel_poly +
    + +

    __ARM_scalbn (Thumb, 44 bytes, Stack size 16 bytes, dscalb.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __ARM_scalbn +
    +
    [Called By]
    • >>   pow +
    • >>   __mathlib_dbl_underflow +
    • >>   __mathlib_dbl_overflow +
    + +

    scalbn (Thumb, 0 bytes, Stack size 16 bytes, dscalb.o(.text), UNUSED) + +

    __aeabi_cdrcmple (Thumb, 38 bytes, Stack size 0 bytes, cdrcmple.o(.text)) +

    [Called By]

    • >>   pow +
    + +

    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text)) +

    [Calls]

    • >>   __main_after_scatterload +
    +
    [Called By]
    • >>   _main_scatterload +
    + +

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) + +

    __aeabi_llsl (Thumb, 32 bytes, Stack size 8 bytes, llshl.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_llsl +
    +
    [Called By]
    • >>   __aeabi_dadd +
    • >>   _double_epilogue +
    + +

    _ll_shift_l (Thumb, 0 bytes, Stack size 8 bytes, llshl.o(.text), UNUSED) + +

    __aeabi_lasr (Thumb, 38 bytes, Stack size 8 bytes, llsshr.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_lasr +
    +
    [Called By]
    • >>   __aeabi_dadd +
    + +

    _ll_sshift_r (Thumb, 0 bytes, Stack size 8 bytes, llsshr.o(.text), UNUSED) + +

    _dsqrt (Thumb, 162 bytes, Stack size 32 bytes, dsqrt.o(.text)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = _dsqrt ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_llsr +
    • >>   _double_round +
    +
    [Called By]
    • >>   sqrt +
    + +

    CMSDK_timer_Init (Thumb, 26 bytes, Stack size 8 bytes, ens1_timer.o(i.CMSDK_timer_Init)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = CMSDK_timer_Init +
    +
    [Called By]
    • >>   TIMER0_Init +
    + +

    ClockInit (Thumb, 20 bytes, Stack size 8 bytes, ens1_clock.o(i.ClockInit)) +

    [Stack]

    • Max Depth = 336
    • Call Chain = ClockInit ⇒ ClockInitSet ⇒ pow ⇒ __kernel_poly ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   ClockInitSet +
    +
    [Called By]
    • >>   main +
    + +

    ClockInitSet (Thumb, 348 bytes, Stack size 48 bytes, ens1_clock.o(i.ClockInitSet)) +

    [Stack]

    • Max Depth = 328
    • Call Chain = ClockInitSet ⇒ pow ⇒ __kernel_poly ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   pow +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_i2d +
    • >>   __aeabi_ddiv +
    • >>   __aeabi_d2uiz +
    +
    [Called By]
    • >>   ClockInit +
    + +

    GPIO_AltFunction (Thumb, 86 bytes, Stack size 8 bytes, ens1_gpio.o(i.GPIO_AltFunction)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = GPIO_AltFunction +
    +
    [Called By]
    • >>   UART_Init +
    • >>   GPIO_IO_Init +
    + +

    GPIO_GetOutputValue (Thumb, 18 bytes, Stack size 0 bytes, ens1_gpio.o(i.GPIO_GetOutputValue)) +

    [Called By]

    • >>   GPIO_Overturn +
    + +

    GPIO_IO_Init (Thumb, 342 bytes, Stack size 36 bytes, ens1_gpio.o(i.GPIO_IO_Init)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = GPIO_IO_Init ⇒ GPIO_AltFunction +
    +
    [Calls]
    • >>   GPIO_AltFunction +
    +
    [Called By]
    • >>   main +
    + +

    GPIO_Output (Thumb, 36 bytes, Stack size 0 bytes, ens1_gpio.o(i.GPIO_Output)) +

    [Called By]

    • >>   main +
    + +

    GPIO_Overturn (Thumb, 40 bytes, Stack size 4 bytes, ens1_gpio.o(i.GPIO_Overturn)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = GPIO_Overturn +
    +
    [Calls]
    • >>   GPIO_SetOutput +
    • >>   GPIO_ResetOutput +
    • >>   GPIO_GetOutputValue +
    +
    [Called By]
    • >>   TIMER0_Handler +
    + +

    GPIO_ResetOutput (Thumb, 16 bytes, Stack size 0 bytes, ens1_gpio.o(i.GPIO_ResetOutput)) +

    [Called By]

    • >>   GPIO_Overturn +
    + +

    GPIO_SetOutput (Thumb, 16 bytes, Stack size 0 bytes, ens1_gpio.o(i.GPIO_SetOutput)) +

    [Called By]

    • >>   GPIO_Overturn +
    + +

    MTP_init (Thumb, 4 bytes, Stack size 0 bytes, ens1_mtp.o(i.MTP_init)) +

    [Called By]

    • >>   main +
    + +

    PCLK_Enable (Thumb, 20 bytes, Stack size 0 bytes, ens1_clock.o(i.PCLK_Enable)) +

    [Called By]

    • >>   UART_Init +
    • >>   TIMER0_Init +
    + +

    SystemInit (Thumb, 8 bytes, Stack size 0 bytes, system_cmsdk_cm0.o(i.SystemInit)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(.text) +
    +

    TIMER0_Handler (Thumb, 62 bytes, Stack size 8 bytes, ens1_timer.o(i.TIMER0_Handler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = TIMER0_Handler ⇒ __2printf +
    +
    [Calls]
    • >>   GPIO_Overturn +
    • >>   __2printf +
    • >>   __aeabi_uidivmod +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    TIMER0_Init (Thumb, 56 bytes, Stack size 16 bytes, ens1_timer.o(i.TIMER0_Init)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = TIMER0_Init ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   CMSDK_timer_Init +
    • >>   NVIC_EnableIRQ +
    • >>   NVIC_DisableIRQ +
    • >>   NVIC_ClearPendingIRQ +
    • >>   PCLK_Enable +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   main +
    + +

    TIMER1_Handler (Thumb, 18 bytes, Stack size 0 bytes, ens1_timer.o(i.TIMER1_Handler)) +
    [Address Reference Count : 1]

    • startup_cmsdk_cm0.o(RESET) +
    +

    UART0_Handler (Thumb, 108 bytes, Stack size 8 bytes, ens1_uart.o(i.UART0_Handler)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = UART0_Handler ⇒ UartPutc +
    +
    [Calls]
    • >>   UartPutc +
    • >>   UART_INT_TYPE +
    • >>   NVIC_ClearPendingIRQ +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    UART1_Handler (Thumb, 92 bytes, Stack size 8 bytes, ens1_uart.o(i.UART1_Handler)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = UART1_Handler ⇒ UartPutc +
    +
    [Calls]
    • >>   UartPutc +
    • >>   UART_INT_TYPE +
    • >>   NVIC_ClearPendingIRQ +
    +
    [Address Reference Count : 1]
    • startup_cmsdk_cm0.o(RESET) +
    +

    UARTLine_THREmpty (Thumb, 10 bytes, Stack size 0 bytes, ens1_uart.o(i.UARTLine_THREmpty)) +

    [Called By]

    • >>   UartPutc +
    + +

    UART_INT_TYPE (Thumb, 10 bytes, Stack size 0 bytes, ens1_uart.o(i.UART_INT_TYPE)) +

    [Called By]

    • >>   UART1_Handler +
    • >>   UART0_Handler +
    + +

    UART_ITConfig (Thumb, 84 bytes, Stack size 16 bytes, ens1_uart.o(i.UART_ITConfig)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_ITConfig +
    +
    [Calls]
    • >>   NVIC_EnableIRQ +
    • >>   NVIC_DisableIRQ +
    • >>   NVIC_ClearPendingIRQ +
    +
    [Called By]
    • >>   main +
    + +

    UART_Init (Thumb, 164 bytes, Stack size 24 bytes, ens1_uart.o(i.UART_Init)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = UART_Init ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   PCLK_Enable +
    • >>   GPIO_AltFunction +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   main +
    + +

    UartPutc (Thumb, 30 bytes, Stack size 4 bytes, ens1_uart.o(i.UartPutc)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = UartPutc +
    +
    [Calls]
    • >>   WRITE_UART_THRBuff +
    • >>   UARTLine_THREmpty +
    +
    [Called By]
    • >>   fputc +
    • >>   UART1_Handler +
    • >>   UART0_Handler +
    + +

    WRITE_UART_THRBuff (Thumb, 4 bytes, Stack size 0 bytes, ens1_uart.o(i.WRITE_UART_THRBuff)) +

    [Called By]

    • >>   UartPutc +
    + +

    __0printf$1 (Thumb, 24 bytes, Stack size 24 bytes, printf1.o(i.__0printf$1), UNUSED) +

    [Calls]

    • >>   _printf_core +
    + +

    __1printf$1 (Thumb, 0 bytes, Stack size 24 bytes, printf1.o(i.__0printf$1), UNUSED) + +

    __2printf (Thumb, 0 bytes, Stack size 24 bytes, printf1.o(i.__0printf$1)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __2printf +
    +
    [Called By]
    • >>   TIMER0_Handler +
    + +

    __ARM_clz (Thumb, 46 bytes, Stack size 0 bytes, depilogue.o(i.__ARM_clz)) +

    [Called By]

    • >>   _double_epilogue +
    + +

    __ARM_fpclassify (Thumb, 40 bytes, Stack size 0 bytes, fpclassify.o(i.__ARM_fpclassify)) +

    [Called By]

    • >>   pow +
    + +

    __kernel_poly (Thumb, 172 bytes, Stack size 24 bytes, poly.o(i.__kernel_poly)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = __kernel_poly ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   __aeabi_dmul +
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   pow +
    + +

    __mathlib_dbl_divzero (Thumb, 16 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_divzero)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = __mathlib_dbl_divzero ⇒ __aeabi_ddiv ⇒ _double_round +
    +
    [Calls]
    • >>   __aeabi_ddiv +
    +
    [Called By]
    • >>   pow +
    + +

    __mathlib_dbl_infnan2 (Thumb, 8 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_infnan2)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = __mathlib_dbl_infnan2 ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   pow +
    + +

    __mathlib_dbl_invalid (Thumb, 16 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_invalid)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = __mathlib_dbl_invalid ⇒ __aeabi_ddiv ⇒ _double_round +
    +
    [Calls]
    • >>   __aeabi_ddiv +
    +
    [Called By]
    • >>   pow +
    + +

    __mathlib_dbl_overflow (Thumb, 16 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_overflow)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __mathlib_dbl_overflow ⇒ __ARM_scalbn +
    +
    [Calls]
    • >>   __ARM_scalbn +
    +
    [Called By]
    • >>   pow +
    + +

    __mathlib_dbl_underflow (Thumb, 14 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_underflow)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __mathlib_dbl_underflow ⇒ __ARM_scalbn +
    +
    [Calls]
    • >>   __ARM_scalbn +
    +
    [Called By]
    • >>   pow +
    + +

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) + +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) + +

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) + +

    __set_errno (Thumb, 6 bytes, Stack size 0 bytes, errno.o(i.__set_errno)) +

    [Called By]

    • >>   pow +
    • >>   sqrt +
    + +

    fputc (Thumb, 16 bytes, Stack size 16 bytes, retarget.o(i.fputc)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = fputc ⇒ UartPutc +
    +
    [Calls]
    • >>   UartPutc +
    +
    [Address Reference Count : 1]
    • printf1.o(i.__0printf$1) +
    +

    main (Thumb, 64 bytes, Stack size 16 bytes, mian.o(i.main)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = main ⇒ ClockInit ⇒ ClockInitSet ⇒ pow ⇒ __kernel_poly ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   UART_Init +
    • >>   UART_ITConfig +
    • >>   TIMER0_Init +
    • >>   MTP_init +
    • >>   GPIO_Output +
    • >>   GPIO_IO_Init +
    • >>   ClockInit +
    +
    [Address Reference Count : 1]
    • entry9a.o(.ARM.Collect$$$$0000000B) +
    +

    pow (Thumb, 2548 bytes, Stack size 128 bytes, pow.o(i.pow)) +

    [Stack]

    • Max Depth = 280
    • Call Chain = pow ⇒ __kernel_poly ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsl +
    +
    [Calls]
    • >>   __aeabi_dsub +
    • >>   __aeabi_drsub +
    • >>   __aeabi_dmul +
    • >>   __aeabi_dadd +
    • >>   __aeabi_cdrcmple +
    • >>   __ARM_scalbn +
    • >>   __aeabi_i2d +
    • >>   __aeabi_ddiv +
    • >>   __set_errno +
    • >>   sqrt +
    • >>   __kernel_poly +
    • >>   __ARM_fpclassify +
    • >>   __mathlib_dbl_underflow +
    • >>   __mathlib_dbl_overflow +
    • >>   __mathlib_dbl_invalid +
    • >>   __mathlib_dbl_infnan2 +
    • >>   __mathlib_dbl_divzero +
    +
    [Called By]
    • >>   ClockInitSet +
    + +

    sqrt (Thumb, 66 bytes, Stack size 24 bytes, sqrt.o(i.sqrt)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = sqrt ⇒ _dsqrt ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __set_errno +
    • >>   _dsqrt +
    +
    [Called By]
    • >>   pow +
    +

    +

    +Local Symbols +

    +

    NVIC_ClearPendingIRQ (Thumb, 14 bytes, Stack size 0 bytes, ens1_uart.o(i.NVIC_ClearPendingIRQ)) +

    [Called By]

    • >>   UART1_Handler +
    • >>   UART0_Handler +
    • >>   UART_ITConfig +
    + +

    NVIC_DisableIRQ (Thumb, 14 bytes, Stack size 0 bytes, ens1_uart.o(i.NVIC_DisableIRQ)) +

    [Called By]

    • >>   UART_ITConfig +
    + +

    NVIC_EnableIRQ (Thumb, 14 bytes, Stack size 0 bytes, ens1_uart.o(i.NVIC_EnableIRQ)) +

    [Called By]

    • >>   UART_ITConfig +
    + +

    NVIC_ClearPendingIRQ (Thumb, 14 bytes, Stack size 0 bytes, ens1_timer.o(i.NVIC_ClearPendingIRQ)) +

    [Called By]

    • >>   TIMER0_Init +
    + +

    NVIC_DisableIRQ (Thumb, 14 bytes, Stack size 0 bytes, ens1_timer.o(i.NVIC_DisableIRQ)) +

    [Called By]

    • >>   TIMER0_Init +
    + +

    NVIC_EnableIRQ (Thumb, 14 bytes, Stack size 0 bytes, ens1_timer.o(i.NVIC_EnableIRQ)) +

    [Called By]

    • >>   TIMER0_Init +
    + +

    _printf_core (Thumb, 332 bytes, Stack size 88 bytes, printf1.o(i._printf_core), UNUSED) +

    [Calls]

    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   __0printf$1 +
    +

    +

    +Undefined Global Symbols +

    diff --git a/Objects/ENS001_BASIC_PRJ.lnp b/Objects/ENS001_BASIC_PRJ.lnp new file mode 100644 index 0000000..485f152 --- /dev/null +++ b/Objects/ENS001_BASIC_PRJ.lnp @@ -0,0 +1,14 @@ +--cpu Cortex-M0 +".\objects\mian.o" +".\objects\ens1_uart.o" +".\objects\ens1_gpio.o" +".\objects\ens1_mtp.o" +".\objects\ens1_clock.o" +".\objects\retarget.o" +".\objects\ens1_timer.o" +".\objects\system_cmsdk_cm0.o" +".\objects\startup_cmsdk_cm0.o" +--library_type=microlib --strict --scatter ".\Objects\ENS001_BASIC_PRJ.sct" +--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Listings\ENS001_BASIC_PRJ.map" -o .\Objects\ENS001_BASIC_PRJ.axf \ No newline at end of file diff --git a/Objects/ENS001_BASIC_PRJ.sct b/Objects/ENS001_BASIC_PRJ.sct new file mode 100644 index 0000000..6d7be8f --- /dev/null +++ b/Objects/ENS001_BASIC_PRJ.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x10000000 0x00008000 { ; load region size_region + ER_IROM1 0x10000000 0x00008000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/Objects/ENS001_BASIC_PRJ_ENS001_BASIC_PRJ.dep b/Objects/ENS001_BASIC_PRJ_ENS001_BASIC_PRJ.dep new file mode 100644 index 0000000..35c375c --- /dev/null +++ b/Objects/ENS001_BASIC_PRJ_ENS001_BASIC_PRJ.dep @@ -0,0 +1,104 @@ +Dependencies for Project 'ENS001_BASIC_PRJ', Target 'ENS001_BASIC_PRJ': (DO NOT MODIFY !) +CompilerVersion: 5060750::V5.06 update 6 (build 750)::.\ARM_Compiler_5.06u7 +F (.\USER\mian.c)(0x689C4ADA)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\mian.o --omf_browse .\objects\mian.crf --depend .\objects\mian.d) +I (USER\my_header.h)(0x689C4B9B) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E) +I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8) +I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E) +I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6) +I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6) +I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6) +I (.\USER\my_header.h)(0x689C4B9B) +I (.\FWLIB\include\ENS1_MTP.h)(0x65605CD6) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdlib.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\string.h)(0x599ECD2C) +I (.\FWLIB\include\ENS1_CLOCK.h)(0x68358097) +I (.\FWLIB\include\ENS1_UART.h)(0x689C4BC8) +I (.\FWLIB\include\ENS1_GPIO.h)(0x656546CE) +F (.\FWLIB\source\ENS1_UART.c)(0x689C4BE6)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_uart.o --omf_browse .\objects\ens1_uart.crf --depend .\objects\ens1_uart.d) +I (.\USER\my_header.h)(0x689C4B9B) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E) +I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8) +I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E) +I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6) +I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6) +I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6) +I (.\FWLIB\include\ENS1_UART.h)(0x689C4BC8) +I (.\FWLIB\include\ENS1_CLOCK.h)(0x68358097) +I (.\FWLIB\include\ENS1_GPIO.h)(0x656546CE) +F (.\FWLIB\source\ENS1_GPIO.c)(0x689C4B85)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_gpio.o --omf_browse .\objects\ens1_gpio.crf --depend .\objects\ens1_gpio.d) +I (.\USER\my_header.h)(0x689C4B9B) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E) +I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8) +I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E) +I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6) +I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6) +I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6) +I (.\FWLIB\include\ENS1_GPIO.h)(0x656546CE) +F (.\FWLIB\source\ENS1_MTP.c)(0x680B4E85)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_mtp.o --omf_browse .\objects\ens1_mtp.crf --depend .\objects\ens1_mtp.d) +I (.\FWLIB\include\ENS1_MTP.h)(0x65605CD6) +I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8) +I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E) +I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6) +I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdlib.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\string.h)(0x599ECD2C) +I (.\USER\my_header.h)(0x689C4B9B) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E) +I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6) +F (.\FWLIB\source\ENS1_CLOCK.c)(0x68358347)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_clock.o --omf_browse .\objects\ens1_clock.crf --depend .\objects\ens1_clock.d) +I (.\FWLIB\include\ENS1_CLOCK.h)(0x68358097) +I (.\USER\my_header.h)(0x689C4B9B) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E) +I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8) +I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E) +I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6) +I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6) +I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6) +F (.\FWLIB\source\retarget.c)(0x6565495A)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\retarget.o --omf_browse .\objects\retarget.crf --depend .\objects\retarget.d) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\time.h)(0x599ECD2E) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\rt_misc.h)(0x599ECD2E) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stddef.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E) +I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8) +I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6) +I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6) +F (.\FWLIB\source\ENS1_TIMER.c)(0x689C4BF1)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\ens1_timer.o --omf_browse .\objects\ens1_timer.crf --depend .\objects\ens1_timer.d) +I (.\FWLIB\include\ENS1_TIMER.h)(0x689C4BA6) +I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8) +I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E) +I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6) +I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6) +I (.\USER\my_header.h)(0x689C4B9B) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdio.h)(0x599ECD2C) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\math.h)(0x599ECD2E) +I (.\FWLIB\include\ENS_CURRENT_CALIBRATION.h)(0x6566A27C) +I (.\FWLIB\include\ENS1_CLOCK.h)(0x68358097) +F (.\CORE\system_CMSDK_CM0.c)(0x63648DE6)(--c99 -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I .\CORE\INCLUDE -I .\USER -I .\FWLIB\include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="538" -DARMCM0 -o .\objects\system_cmsdk_cm0.o --omf_browse .\objects\system_cmsdk_cm0.crf --depend .\objects\system_cmsdk_cm0.d) +I (D:\Keil_v5\ARM\ARM_Compiler_5.06u7\include\stdint.h)(0x599ECD2E) +I (.\CORE\INCLUDE\CMSDK_CM0.h)(0x64D5ADE8) +I (.\CORE\INCLUDE\core_cm0.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmInstr.h)(0x63648DE6) +I (.\CORE\INCLUDE\core_cmFunc.h)(0x63648DE6) +I (.\CORE\INCLUDE\system_CMSDK_CM0.h)(0x63648DE6) +F (.\CORE\ARM\startup_CMSDK_CM0.s)(0x6365EF56)(--cpu Cortex-M0 --li -g --apcs=interwork --pd "__MICROLIB SETA 1" -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARMCM0\Include -ID:\Keil_v5\ARM\Packs\ARM\Cortex_DFP\1.1.0\Device\ARM\ARMCM0\Include --pd "__UVISION_VERSION SETA 538" --pd "ARMCM0 SETA 1" --list .\listings\startup_cmsdk_cm0.lst --xref -o .\objects\startup_cmsdk_cm0.o --depend .\objects\startup_cmsdk_cm0.d) diff --git a/Objects/ENS001_BASIC_PRJ_sct.Bak b/Objects/ENS001_BASIC_PRJ_sct.Bak new file mode 100644 index 0000000..2fe0a78 --- /dev/null +++ b/Objects/ENS001_BASIC_PRJ_sct.Bak @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x10000000 0x00008000 { ; load region size_region + ER_IROM1 0x10000000 0x00008000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/Objects/ExtDll.iex b/Objects/ExtDll.iex new file mode 100644 index 0000000..6c0896e --- /dev/null +++ b/Objects/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/Objects/ens1_anac.crf b/Objects/ens1_anac.crf new file mode 100644 index 0000000..b1c4f83 Binary files /dev/null and b/Objects/ens1_anac.crf differ diff --git a/Objects/ens1_anac.d b/Objects/ens1_anac.d new file mode 100644 index 0000000..33d3785 --- /dev/null +++ b/Objects/ens1_anac.d @@ -0,0 +1,12 @@ +.\objects\ens1_anac.o: FWLIB\source\ENS1_ANAC.c +.\objects\ens1_anac.o: .\FWLIB\include\ens1_anac.h +.\objects\ens1_anac.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens1_anac.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_anac.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_anac.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens1_anac.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_anac.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_anac.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_anac.o: .\USER\my_header.h +.\objects\ens1_anac.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\ens1_anac.o: .\FWLIB\include\ENS1_GPIO.h diff --git a/Objects/ens1_anac.o b/Objects/ens1_anac.o new file mode 100644 index 0000000..34d7ee2 Binary files /dev/null and b/Objects/ens1_anac.o differ diff --git a/Objects/ens1_boost.crf b/Objects/ens1_boost.crf new file mode 100644 index 0000000..2107f92 Binary files /dev/null and b/Objects/ens1_boost.crf differ diff --git a/Objects/ens1_boost.d b/Objects/ens1_boost.d new file mode 100644 index 0000000..9792d53 --- /dev/null +++ b/Objects/ens1_boost.d @@ -0,0 +1,12 @@ +.\objects\ens1_boost.o: FWLIB\source\ENS1_BOOST.c +.\objects\ens1_boost.o: .\FWLIB\include\ENS1_BOOST.h +.\objects\ens1_boost.o: .\USER\my_header.h +.\objects\ens1_boost.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens1_boost.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\ens1_boost.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_boost.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_boost.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens1_boost.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_boost.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_boost.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_boost.o: .\FWLIB\include\ENS1_CLOCK.h diff --git a/Objects/ens1_boost.o b/Objects/ens1_boost.o new file mode 100644 index 0000000..008906e Binary files /dev/null and b/Objects/ens1_boost.o differ diff --git a/Objects/ens1_clock.crf b/Objects/ens1_clock.crf new file mode 100644 index 0000000..8f70ffa Binary files /dev/null and b/Objects/ens1_clock.crf differ diff --git a/Objects/ens1_clock.d b/Objects/ens1_clock.d new file mode 100644 index 0000000..cd9acb9 --- /dev/null +++ b/Objects/ens1_clock.d @@ -0,0 +1,13 @@ +.\objects\ens1_clock.o: FWLIB\source\ENS1_CLOCK.c +.\objects\ens1_clock.o: .\FWLIB\include\ENS1_CLOCK.h +.\objects\ens1_clock.o: .\USER\my_header.h +.\objects\ens1_clock.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h +.\objects\ens1_clock.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h +.\objects\ens1_clock.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_clock.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_clock.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h +.\objects\ens1_clock.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_clock.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_clock.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_clock.o: .\FWLIB\include\ENS1_TIMER.h +.\objects\ens1_clock.o: .\USER\my_header.h diff --git a/Objects/ens1_clock.o b/Objects/ens1_clock.o new file mode 100644 index 0000000..e5275e4 Binary files /dev/null and b/Objects/ens1_clock.o differ diff --git a/Objects/ens1_exti.crf b/Objects/ens1_exti.crf new file mode 100644 index 0000000..1471029 Binary files /dev/null and b/Objects/ens1_exti.crf differ diff --git a/Objects/ens1_exti.d b/Objects/ens1_exti.d new file mode 100644 index 0000000..ef6b6e6 --- /dev/null +++ b/Objects/ens1_exti.d @@ -0,0 +1,11 @@ +.\objects\ens1_exti.o: FWLIB\source\ENS1_EXTI.c +.\objects\ens1_exti.o: .\FWLIB\include\ENS1_EXTI.h +.\objects\ens1_exti.o: .\USER\my_header.h +.\objects\ens1_exti.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens1_exti.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\ens1_exti.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_exti.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_exti.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens1_exti.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_exti.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_exti.o: .\CORE\INCLUDE\system_CMSDK_CM0.h diff --git a/Objects/ens1_exti.o b/Objects/ens1_exti.o new file mode 100644 index 0000000..c3060a7 Binary files /dev/null and b/Objects/ens1_exti.o differ diff --git a/Objects/ens1_gpio.crf b/Objects/ens1_gpio.crf new file mode 100644 index 0000000..b5216af Binary files /dev/null and b/Objects/ens1_gpio.crf differ diff --git a/Objects/ens1_gpio.d b/Objects/ens1_gpio.d new file mode 100644 index 0000000..bacb8e9 --- /dev/null +++ b/Objects/ens1_gpio.d @@ -0,0 +1,13 @@ +.\objects\ens1_gpio.o: FWLIB\source\ENS1_GPIO.c +.\objects\ens1_gpio.o: .\USER\my_header.h +.\objects\ens1_gpio.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h +.\objects\ens1_gpio.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h +.\objects\ens1_gpio.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_gpio.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_gpio.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h +.\objects\ens1_gpio.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_gpio.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_gpio.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_gpio.o: .\FWLIB\include\ENS1_TIMER.h +.\objects\ens1_gpio.o: .\USER\my_header.h +.\objects\ens1_gpio.o: .\FWLIB\include\ENS1_GPIO.h diff --git a/Objects/ens1_gpio.o b/Objects/ens1_gpio.o new file mode 100644 index 0000000..0df88b1 Binary files /dev/null and b/Objects/ens1_gpio.o differ diff --git a/Objects/ens1_iic.crf b/Objects/ens1_iic.crf new file mode 100644 index 0000000..f6d1aab Binary files /dev/null and b/Objects/ens1_iic.crf differ diff --git a/Objects/ens1_iic.d b/Objects/ens1_iic.d new file mode 100644 index 0000000..e16aaef --- /dev/null +++ b/Objects/ens1_iic.d @@ -0,0 +1,14 @@ +.\objects\ens1_iic.o: FWLIB\source\ENS1_IIC.c +.\objects\ens1_iic.o: .\FWLIB\include\ENS1_IIC.h +.\objects\ens1_iic.o: .\USER\my_header.h +.\objects\ens1_iic.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens1_iic.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\ens1_iic.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_iic.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_iic.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens1_iic.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_iic.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_iic.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_iic.o: .\FWLIB\include\ens1_uart.h +.\objects\ens1_iic.o: .\FWLIB\include\ENS1_CLOCK.h +.\objects\ens1_iic.o: .\FWLIB\include\ENS1_GPIO.h diff --git a/Objects/ens1_iic.o b/Objects/ens1_iic.o new file mode 100644 index 0000000..5970cdb Binary files /dev/null and b/Objects/ens1_iic.o differ diff --git a/Objects/ens1_mtp.crf b/Objects/ens1_mtp.crf new file mode 100644 index 0000000..8ce5f9d Binary files /dev/null and b/Objects/ens1_mtp.crf differ diff --git a/Objects/ens1_mtp.d b/Objects/ens1_mtp.d new file mode 100644 index 0000000..66454ad --- /dev/null +++ b/Objects/ens1_mtp.d @@ -0,0 +1,15 @@ +.\objects\ens1_mtp.o: FWLIB\source\ENS1_MTP.c +.\objects\ens1_mtp.o: .\FWLIB\include\ENS1_MTP.h +.\objects\ens1_mtp.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_mtp.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h +.\objects\ens1_mtp.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_mtp.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_mtp.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdlib.h +.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\string.h +.\objects\ens1_mtp.o: .\USER\my_header.h +.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h +.\objects\ens1_mtp.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h +.\objects\ens1_mtp.o: .\FWLIB\include\ENS1_TIMER.h +.\objects\ens1_mtp.o: .\USER\my_header.h diff --git a/Objects/ens1_mtp.o b/Objects/ens1_mtp.o new file mode 100644 index 0000000..dd88f0d Binary files /dev/null and b/Objects/ens1_mtp.o differ diff --git a/Objects/ens1_pwm.crf b/Objects/ens1_pwm.crf new file mode 100644 index 0000000..2f8d95b Binary files /dev/null and b/Objects/ens1_pwm.crf differ diff --git a/Objects/ens1_pwm.d b/Objects/ens1_pwm.d new file mode 100644 index 0000000..6793968 --- /dev/null +++ b/Objects/ens1_pwm.d @@ -0,0 +1,12 @@ +.\objects\ens1_pwm.o: FWLIB\source\ENS1_PWM.c +.\objects\ens1_pwm.o: .\FWLIB\include\ens1_pwm.h +.\objects\ens1_pwm.o: .\USER\my_header.h +.\objects\ens1_pwm.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens1_pwm.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\ens1_pwm.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_pwm.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_pwm.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens1_pwm.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_pwm.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_pwm.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_pwm.o: .\FWLIB\include\ENS1_CLOCK.h diff --git a/Objects/ens1_pwm.o b/Objects/ens1_pwm.o new file mode 100644 index 0000000..97e7a7e Binary files /dev/null and b/Objects/ens1_pwm.o differ diff --git a/Objects/ens1_spi.crf b/Objects/ens1_spi.crf new file mode 100644 index 0000000..4b860c9 Binary files /dev/null and b/Objects/ens1_spi.crf differ diff --git a/Objects/ens1_spi.d b/Objects/ens1_spi.d new file mode 100644 index 0000000..69d94f8 --- /dev/null +++ b/Objects/ens1_spi.d @@ -0,0 +1,12 @@ +.\objects\ens1_spi.o: FWLIB\source\ENS1_SPI.c +.\objects\ens1_spi.o: .\FWLIB\include\ENS1_SPI.h +.\objects\ens1_spi.o: .\USER\my_header.h +.\objects\ens1_spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens1_spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\ens1_spi.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_spi.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_spi.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens1_spi.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_spi.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_spi.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_spi.o: .\FWLIB\include\ENS1_GPIO.h diff --git a/Objects/ens1_spi.o b/Objects/ens1_spi.o new file mode 100644 index 0000000..79456db Binary files /dev/null and b/Objects/ens1_spi.o differ diff --git a/Objects/ens1_timer.crf b/Objects/ens1_timer.crf new file mode 100644 index 0000000..d5da35b Binary files /dev/null and b/Objects/ens1_timer.crf differ diff --git a/Objects/ens1_timer.d b/Objects/ens1_timer.d new file mode 100644 index 0000000..bd569e6 --- /dev/null +++ b/Objects/ens1_timer.d @@ -0,0 +1,14 @@ +.\objects\ens1_timer.o: FWLIB\source\ENS1_TIMER.c +.\objects\ens1_timer.o: .\FWLIB\include\ENS1_TIMER.h +.\objects\ens1_timer.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_timer.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_timer.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h +.\objects\ens1_timer.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_timer.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_timer.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_timer.o: .\USER\my_header.h +.\objects\ens1_timer.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h +.\objects\ens1_timer.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h +.\objects\ens1_timer.o: .\FWLIB\include\ENS1_TIMER.h +.\objects\ens1_timer.o: .\FWLIB\include\ENS_CURRENT_CALIBRATION.h +.\objects\ens1_timer.o: .\FWLIB\include\ENS1_CLOCK.h diff --git a/Objects/ens1_timer.o b/Objects/ens1_timer.o new file mode 100644 index 0000000..4139eba Binary files /dev/null and b/Objects/ens1_timer.o differ diff --git a/Objects/ens1_uart.crf b/Objects/ens1_uart.crf new file mode 100644 index 0000000..6870c1f Binary files /dev/null and b/Objects/ens1_uart.crf differ diff --git a/Objects/ens1_uart.d b/Objects/ens1_uart.d new file mode 100644 index 0000000..970edc9 --- /dev/null +++ b/Objects/ens1_uart.d @@ -0,0 +1,15 @@ +.\objects\ens1_uart.o: FWLIB\source\ENS1_UART.c +.\objects\ens1_uart.o: .\USER\my_header.h +.\objects\ens1_uart.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h +.\objects\ens1_uart.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h +.\objects\ens1_uart.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_uart.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_uart.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h +.\objects\ens1_uart.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_uart.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_uart.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_uart.o: .\FWLIB\include\ENS1_TIMER.h +.\objects\ens1_uart.o: .\USER\my_header.h +.\objects\ens1_uart.o: .\FWLIB\include\ENS1_UART.h +.\objects\ens1_uart.o: .\FWLIB\include\ENS1_CLOCK.h +.\objects\ens1_uart.o: .\FWLIB\include\ENS1_GPIO.h diff --git a/Objects/ens1_uart.o b/Objects/ens1_uart.o new file mode 100644 index 0000000..7e7d710 Binary files /dev/null and b/Objects/ens1_uart.o differ diff --git a/Objects/ens1_watchdog.crf b/Objects/ens1_watchdog.crf new file mode 100644 index 0000000..8eefd3a Binary files /dev/null and b/Objects/ens1_watchdog.crf differ diff --git a/Objects/ens1_watchdog.d b/Objects/ens1_watchdog.d new file mode 100644 index 0000000..443fdfd --- /dev/null +++ b/Objects/ens1_watchdog.d @@ -0,0 +1,12 @@ +.\objects\ens1_watchdog.o: FWLIB\source\ENS1_WATCHDOG.c +.\objects\ens1_watchdog.o: .\FWLIB\include\ENS1_WATCHDOG.h +.\objects\ens1_watchdog.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens1_watchdog.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens1_watchdog.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens1_watchdog.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens1_watchdog.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens1_watchdog.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens1_watchdog.o: .\FWLIB\include\ENS1_CLOCK.h +.\objects\ens1_watchdog.o: .\USER\my_header.h +.\objects\ens1_watchdog.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens1_watchdog.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h diff --git a/Objects/ens1_watchdog.o b/Objects/ens1_watchdog.o new file mode 100644 index 0000000..da98e4a Binary files /dev/null and b/Objects/ens1_watchdog.o differ diff --git a/Objects/ens_adc.crf b/Objects/ens_adc.crf new file mode 100644 index 0000000..9f35439 Binary files /dev/null and b/Objects/ens_adc.crf differ diff --git a/Objects/ens_adc.d b/Objects/ens_adc.d new file mode 100644 index 0000000..e81da38 --- /dev/null +++ b/Objects/ens_adc.d @@ -0,0 +1,12 @@ +.\objects\ens_adc.o: FWLIB\source\ENS_ADC.c +.\objects\ens_adc.o: .\FWLIB\include\ENS1_ADC.h +.\objects\ens_adc.o: .\USER\my_header.h +.\objects\ens_adc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens_adc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\ens_adc.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens_adc.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens_adc.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens_adc.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens_adc.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens_adc.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens_adc.o: .\FWLIB\include\ENS1_GPIO.h diff --git a/Objects/ens_adc.o b/Objects/ens_adc.o new file mode 100644 index 0000000..f4434a5 Binary files /dev/null and b/Objects/ens_adc.o differ diff --git a/Objects/ens_current_calibration.crf b/Objects/ens_current_calibration.crf new file mode 100644 index 0000000..eb6d1b7 Binary files /dev/null and b/Objects/ens_current_calibration.crf differ diff --git a/Objects/ens_current_calibration.d b/Objects/ens_current_calibration.d new file mode 100644 index 0000000..ecc36dd --- /dev/null +++ b/Objects/ens_current_calibration.d @@ -0,0 +1,17 @@ +.\objects\ens_current_calibration.o: FWLIB\source\ENS_CURRENT_CALIBRATION.c +.\objects\ens_current_calibration.o: .\FWLIB\include\ENS_CURRENT_CALIBRATION.h +.\objects\ens_current_calibration.o: .\USER\my_header.h +.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\ens_current_calibration.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\ens_current_calibration.o: .\CORE\INCLUDE\core_cm0.h +.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\ens_current_calibration.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\ens_current_calibration.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\ens_current_calibration.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\ens_current_calibration.o: .\FWLIB\include\ENS1_TIMER.h +.\objects\ens_current_calibration.o: .\FWLIB\include\ENS1_MTP.h +.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\objects\ens_current_calibration.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h +.\objects\ens_current_calibration.o: .\FWLIB\include\ENS1_UART.h +.\objects\ens_current_calibration.o: .\FWLIB\include\ENS1_CLOCK.h diff --git a/Objects/ens_current_calibration.o b/Objects/ens_current_calibration.o new file mode 100644 index 0000000..86e45fe Binary files /dev/null and b/Objects/ens_current_calibration.o differ diff --git a/Objects/haienda.crf b/Objects/haienda.crf new file mode 100644 index 0000000..66801b8 Binary files /dev/null and b/Objects/haienda.crf differ diff --git a/Objects/haienda.d b/Objects/haienda.d new file mode 100644 index 0000000..fee1234 --- /dev/null +++ b/Objects/haienda.d @@ -0,0 +1,14 @@ +.\objects\haienda.o: haienda.c +.\objects\haienda.o: .\FWLIB\include\ENS_CURRENT_CALIBRATION.h +.\objects\haienda.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\haienda.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\haienda.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\haienda.o: .\CORE\INCLUDE\core_cm0.h +.\objects\haienda.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\haienda.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\haienda.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\haienda.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\haienda.o: .\USER\my_header.h +.\objects\haienda.o: .\FWLIB\include\ENS1_UART.h +.\objects\haienda.o: .\FWLIB\include\ENS1_CLOCK.h +.\objects\haienda.o: .\FWLIB\include\ENS1_TIMER.h diff --git a/Objects/haienda.o b/Objects/haienda.o new file mode 100644 index 0000000..f860c95 Binary files /dev/null and b/Objects/haienda.o differ diff --git a/Objects/mian.crf b/Objects/mian.crf new file mode 100644 index 0000000..512ffa4 Binary files /dev/null and b/Objects/mian.crf differ diff --git a/Objects/mian.d b/Objects/mian.d new file mode 100644 index 0000000..3ec82b5 --- /dev/null +++ b/Objects/mian.d @@ -0,0 +1,18 @@ +.\objects\mian.o: USER\mian.c +.\objects\mian.o: USER\my_header.h +.\objects\mian.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h +.\objects\mian.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\math.h +.\objects\mian.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\mian.o: .\CORE\INCLUDE\core_cm0.h +.\objects\mian.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h +.\objects\mian.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\mian.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\mian.o: .\CORE\INCLUDE\system_CMSDK_CM0.h +.\objects\mian.o: .\FWLIB\include\ENS1_TIMER.h +.\objects\mian.o: .\USER\my_header.h +.\objects\mian.o: .\FWLIB\include\ENS1_MTP.h +.\objects\mian.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdlib.h +.\objects\mian.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\string.h +.\objects\mian.o: .\FWLIB\include\ENS1_CLOCK.h +.\objects\mian.o: .\FWLIB\include\ENS1_UART.h +.\objects\mian.o: .\FWLIB\include\ENS1_GPIO.h diff --git a/Objects/mian.o b/Objects/mian.o new file mode 100644 index 0000000..dad1085 Binary files /dev/null and b/Objects/mian.o differ diff --git a/Objects/retarget.crf b/Objects/retarget.crf new file mode 100644 index 0000000..3f1e27f Binary files /dev/null and b/Objects/retarget.crf differ diff --git a/Objects/retarget.d b/Objects/retarget.d new file mode 100644 index 0000000..310a05d --- /dev/null +++ b/Objects/retarget.d @@ -0,0 +1,11 @@ +.\objects\retarget.o: FWLIB\source\retarget.c +.\objects\retarget.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdio.h +.\objects\retarget.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\time.h +.\objects\retarget.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\rt_misc.h +.\objects\retarget.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stddef.h +.\objects\retarget.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h +.\objects\retarget.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\retarget.o: .\CORE\INCLUDE\core_cm0.h +.\objects\retarget.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\retarget.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\retarget.o: .\CORE\INCLUDE\system_CMSDK_CM0.h diff --git a/Objects/retarget.o b/Objects/retarget.o new file mode 100644 index 0000000..b96ba6d Binary files /dev/null and b/Objects/retarget.o differ diff --git a/Objects/startup_armcm0.d b/Objects/startup_armcm0.d new file mode 100644 index 0000000..1577e69 --- /dev/null +++ b/Objects/startup_armcm0.d @@ -0,0 +1 @@ +.\objects\startup_armcm0.o: CORE\startup_ARMCM0.s diff --git a/Objects/startup_armcm0.o b/Objects/startup_armcm0.o new file mode 100644 index 0000000..f6f5c5e Binary files /dev/null and b/Objects/startup_armcm0.o differ diff --git a/Objects/startup_cmsdk_cm0.d b/Objects/startup_cmsdk_cm0.d new file mode 100644 index 0000000..d96cbd6 --- /dev/null +++ b/Objects/startup_cmsdk_cm0.d @@ -0,0 +1 @@ +.\objects\startup_cmsdk_cm0.o: CORE\ARM\startup_CMSDK_CM0.s diff --git a/Objects/startup_cmsdk_cm0.o b/Objects/startup_cmsdk_cm0.o new file mode 100644 index 0000000..6c28317 Binary files /dev/null and b/Objects/startup_cmsdk_cm0.o differ diff --git a/Objects/system_armcm0.d b/Objects/system_armcm0.d new file mode 100644 index 0000000..66950c6 --- /dev/null +++ b/Objects/system_armcm0.d @@ -0,0 +1,7 @@ +.\objects\system_armcm0.o: CORE\system_ARMCM0.c +.\objects\system_armcm0.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.0\Device\ARM\ARMCM0\Include\ARMCM0.h +.\objects\system_armcm0.o: .\CORE\INCLUDE\core_cm0.h +.\objects\system_armcm0.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\system_armcm0.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\system_armcm0.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\system_armcm0.o: C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.0\Device\ARM\ARMCM0\Include\system_ARMCM0.h diff --git a/Objects/system_cmsdk_cm0.crf b/Objects/system_cmsdk_cm0.crf new file mode 100644 index 0000000..fb2bb76 Binary files /dev/null and b/Objects/system_cmsdk_cm0.crf differ diff --git a/Objects/system_cmsdk_cm0.d b/Objects/system_cmsdk_cm0.d new file mode 100644 index 0000000..fd47182 --- /dev/null +++ b/Objects/system_cmsdk_cm0.d @@ -0,0 +1,7 @@ +.\objects\system_cmsdk_cm0.o: CORE\system_CMSDK_CM0.c +.\objects\system_cmsdk_cm0.o: D:\Keil_v5\ARM\ARM_Compiler_5.06u7\Bin\..\include\stdint.h +.\objects\system_cmsdk_cm0.o: .\CORE\INCLUDE\CMSDK_CM0.h +.\objects\system_cmsdk_cm0.o: .\CORE\INCLUDE\core_cm0.h +.\objects\system_cmsdk_cm0.o: .\CORE\INCLUDE\core_cmInstr.h +.\objects\system_cmsdk_cm0.o: .\CORE\INCLUDE\core_cmFunc.h +.\objects\system_cmsdk_cm0.o: .\CORE\INCLUDE\system_CMSDK_CM0.h diff --git a/Objects/system_cmsdk_cm0.o b/Objects/system_cmsdk_cm0.o new file mode 100644 index 0000000..d6db4f2 Binary files /dev/null and b/Objects/system_cmsdk_cm0.o differ diff --git a/USER/ENS001_CONFIG.h b/USER/ENS001_CONFIG.h new file mode 100644 index 0000000..149f106 --- /dev/null +++ b/USER/ENS001_CONFIG.h @@ -0,0 +1,27 @@ +/*Copyright (C),2023 , NANOCHAP +*File name: +*Author: Martin +*Version: V1.0 +*Date: 2023-08-11 +*Description: +*Function List: + 1. + 2. + 3. +History: + 1.V1.0 + Date: + Author: + Modification: +*/ +#ifndef ENS001_CONFIG_H +#define ENS001_CONFIG_H + +#include "CMSDK_CM0.h" +//HSI freq +#define SYSTEM_FREQ 32 + + + + +#endif diff --git a/USER/MY_HEADER.h b/USER/MY_HEADER.h new file mode 100644 index 0000000..e714dc0 --- /dev/null +++ b/USER/MY_HEADER.h @@ -0,0 +1,81 @@ +#ifndef MY_HEADER_H +#define MY_HEADER_H + +#include +#include +#include "CMSDK_CM0.h" +#include "ENS1_TIMER.h" +#define TRUE 1 +#define FALSE 0 + +/*typedef enum +{ + true=1, false=0 +}bool;*/ +typedef enum {CHANNEL_0 = 0,CHANNEL_1,CHANNEL_2,CHANNEL_3} CHANNEL_NUM; +typedef enum {ALT_FUNC0=0,ALT_FUNC1=1,ALT_FUNC2=2,ALT_FUNC3=3 } GPIO_AltFuncSel; +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus ,IOStatus; +typedef enum {DISABLE = 0, ENABLE } FunctionalState; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; +typedef enum {LOW_LEVEL = 0, HIGH_LEVEL = !LOW_LEVEL} LEVELStatus; +typedef enum {OUTPUT = 0, INPUT = !OUTPUT} I_O_SELECT; +typedef enum {oversamp_16 = 0, oversamp_13=!oversamp_16} OverSampModeSel; +typedef enum +{ + GPIO_PU = 0x00, //上拉 + GPIO_PD = 0x01, //下拉 + GPIO_NOPULL = 0x02 //无上下拉 +}GPIO_PUPD_TypeDef; + +//输出速度选择枚举 +typedef enum +{ + OUTPUT_FAST = 0x00, //快速 + OUTPUT_SLOW = 0x01 //慢速 +}OUTPUT_SPEED_TypeDef; + +//输出模式选择枚举 +typedef enum +{ + GPIO_OType_PP = 0x00, //推挽输出 + GPIO_OType_OD = 0x01 //开漏输出 +}GPIOOType_TypeDef; + +//驱动强度选择枚举 +typedef enum +{ + PDRV_4mA = 0x00, //输出驱动强度4mA + PDRV_8mA, //输出驱动强度8mA + PDRV_14mA, //输出驱动强度14mA + PDRV_16mA //输出驱动强度16mA +}OUTPUT_PDRV_TypeDef; + + +typedef enum { + GPIO_0=0, + GPIO_1=1, + GPIO_2=2, + GPIO_3=3, + GPIO_4=4, + GPIO_5=5, + GPIO_6=6, + GPIO_7=7, + GPIO_8=8, + GPIO_9=9, + GPIO_10=10, + GPIO_11=11, + GPIO_12=12, + GPIO_13=13, + GPIO_14=14, + GPIO_15=15, + GPIO_16=16, + GPIO_17=17, + GPIO_18=18, + GPIO_19=19, + GPIO_20=20, + GPIO_21=21, + GPIO_22=22, + GPIO_23=23, +}GPIO_NUM; + +#endif diff --git a/USER/mian.c b/USER/mian.c new file mode 100644 index 0000000..eaa8d8f --- /dev/null +++ b/USER/mian.c @@ -0,0 +1,38 @@ +/* +*Copyright ,2023 , NANOCHAP +*File name: MIAN.C +*Author: +*Version: V1.0 +*Date: 2023-11- +*Description: 1S 定时器测试（TIMER0） +*Function List: + +History: +1.V1.0 +Date: +Author: +Modification: 初版 + +*/ +#include "my_header.h" +#include "ENS1_MTP.h" +#include "ENS1_CLOCK.h" +#include "ENS1_UART.h" +#include "ENS1_TIMER.h" +#include "ENS1_GPIO.h" +int main(){ + MTP_init(); + ClockInit(); + GPIO_IO_Init(GPIO_19, OUTPUT, 0x00, 0x02, 0x00, 0x00, ENABLE); + GPIO_Output(GPIO_19, LOW_LEVEL); + /*uart*/ + UART_Init(CMSDK_UART1, &UART1_Init); + UART_ITConfig(CMSDK_UART1, &UART1_ITSet); + /*TIMER*/ + TIMER0_Init(1); + while(1) + { + /*在 void TIMER0_Handler(void) 中断处理函数中打印*/ + } +} +