208 lines
7.4 KiB
C
208 lines
7.4 KiB
C
/*
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*Copyright ,2023 , NANOCHAP
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*File name: ENS1_SPI.H
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*Author:
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*Version: V1.0
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*Date: 2023-11-
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*Description:
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*Function List:
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1 uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx)
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2 uint8_t CLR_TX_FIFO(CMSDK_SPI_TypeDef* SPIx)
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3 uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx)
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4 uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
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5 uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx)
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6 SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx)
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7 uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
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8 uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
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9 uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx)
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10 uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx)
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11 uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx)
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12 uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx )
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13 uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx )
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14 uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,bool TXDMA_SET ,bool RXDMA_SET)
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15 uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS)
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16 uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , struct SPI_ModeConfig_Struct SPI_Config ,struct SPI_FIFO_Struct FIFO_Struct)
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17 uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx)
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18 uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx)
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19 uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx )
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20 void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data)
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21 uint8_t SPI_INT_SET(IRQn_Type IRQn, bool SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET)
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History:
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1.V1.0
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Date:
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Author:
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Modification: ³õ°æ
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*/
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#ifndef ENS1_SPI_H
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#define ENS1_SPI_H
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#include "my_header.h"
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/*
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Ò»¡¢Òý½Å¹Øϵ£º
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ALT Function2
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SPI1_SCK --- GPIO16
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SPI1_MOSI --- GPIO17
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SPI1_MISO --- GPIO18
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SPI1_NSS0 --- GPIO19
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SPI1_NSS1 --- GPIO2
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SPI1_NSS2 --- GPIO3
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SPI1_NSS3 --- GPIO4
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ALT Function2
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SPI0_SCK --- GPIO8
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SPI0_MOSI --- GPIO9
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SPI0_MISO --- GPIO10
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SPI0_NSS0 --- GPIO11
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SPI0_NSS1 --- GPIO13
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SPI0_NSS2 --- GPIO14
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SPI0_NSS3 --- GPIO15
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¶þ¡¢SPI¹¦ÄÜÁбí˵Ã÷£º
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ÈýÌõÏß·ÉϵÄÈ«Ë«¹¤Í¬²½´«Êä
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Ë«Ïß°ëË«¹¤Í¬²½´«Êä
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Á½Ïßµ¥¹¤Í¬²½´«Ê䣨´øµ¥ÏòÊý¾ÝÏߣ©
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16*16bits FIFO ÊÕ·¢»º³åÇø
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4-16λÊý¾Ý´óСѡÔñ
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Ö÷ģʽ²¨ÌØÂÊ·¢ÉúÆ÷¸ß´ïFpclk/2
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´Óģʽ²¨ÌØÂÊ·¢ÉúÆ÷¸ß´ïFpclk/4
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Èí¼þ»òÓ²¼þ¹ÜÀí NSS
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¿É±à³ÌʱÖÓ¼«ÐÔºÍÏàλ
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¿É±à³ÌµÄÊý¾Ý˳ÐòÓëMSB»òLSBÒÆλ
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DMAʼþÖ§³Ö
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ÖжÏÖ§³Ö
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*/
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typedef enum {MASTER = 1 ,SLAVE= 0}MASTER_SLAVE_SEL;
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typedef enum {NSS0= 8 ,NSS1 ,NSS2 ,NSS3}NSS_CHANNEL_SEL ;
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typedef enum {NOTBUSY = 0, BUSY}SPI_BUSY_STATE ;
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typedef enum {EMPTY=0,FULL}FIFO_FULL_EMPTY_STATE;
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struct SPI_ModeConfig_Struct
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{
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uint8_t BAUD_FPCLKdivx ; //²¨ÌØÂÊ·ÖƵϵÊý
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uint8_t SPI_MODE ; //SPI¹¤×÷ģʽ
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uint8_t SPI_TRANS_MODE; //´«ÊäģʽѡÔñ
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MASTER_SLAVE_SEL MS_SEL; //Ö÷´ÓģʽѡÔñ
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uint16_t CHAR_LEN ; //ÉèÖô«Ê䳤¶È £¨4 - 16 bit£©
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NSS_CHANNEL_SEL NSSx ;
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uint8_t SAMP_PHASE ;
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};
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struct SPI_FIFO_Struct //ÉèÖÃFIFO¼°DMA´«Êä
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{
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uint8_t TX_FIFO_TH; // 0 - 16 char
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uint8_t RX_FIFO_TH; // 0 - 16 char
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int FIFO_ENABLE_SET;
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int TXDMA_SET; //Ñ¡ÔñÊÇ·ñÆô¶¯DMA(fifo¿ªÆôµÄÇ°ÌáÏÂ)
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int RXDMA_SET;
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};
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/* ÖжÏÀàÐÍʹÄܽṹÌå
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1¡¢·¢ËͲ¿·ÖÓÐ ÏÂÒç Öжϣ¨·¢ËÍÊý¾ÝûÓÐÀ²£©
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2¡¢½ÓÊÕ²¿·ÖÓÐ Òç³ö Öжϣ¨½ÓÂúÀ²£©
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3¡¢ÊÕ·¢Íê³ÉÖжϣ¿
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4¡¢·¢ËÍ»º³åÇø¿Õ ÖжÏ
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5¡¢½ÓÊÕ»º³åÇø·Ç¿Õ ÖжÏ
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*/
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//ÖжÏʹÄÜ
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#define UNDERRUN_INT_EN (uint8_t)0x10
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#define OVERRUN_INT_EN (uint8_t)0x8
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#define CMPL_INT_EN (uint8_t)0x4
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#define TXE_INT_EN (uint8_t)0x2
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#define RXNE_INT_EN (uint8_t)0x1
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//ÅжÏÊÇ·ñ¼ì²âµ½¶ÔÓ¦µÄÖжÏ
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#define UNDERRUN_INT (uint8_t)0x10
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#define OVERRUN_INT (uint8_t)0x8
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#define CMPL_INT (uint8_t)0x4
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#define TXE_INT (uint8_t)0x2
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#define RXNE_INT (uint8_t)0x1
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/*ģʽ£º | ½ÓÏß·½Ê½£º Ö÷»ú ´Ó»ú
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È«Ë«¹¤ | MISO/MOSI MISO/MOSI
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°ëË«¹¤ | MOSI MISO
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Ö÷»ú½ö·¢ËÍ£¬´Ó»ú½ö½ÓÊÕģʽ | MOSI MOSI
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Ö÷»ú½ö½ÓÊÕ£¬´Ó»ú½ö·¢ËÍģʽ | MISO MISO
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SPI_TRANS_MODE ´«ÊäģʽѡÔñ£º
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2Ïßµ¥Ïò / 1ÏßË«Ïò
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ÊÕ+·¢ / ½ö·¢ /½öÊÕ/ µ¥Ïò½ö·¢ËÍ / ½ö½ÓÊÕ
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*/
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#define L2_UniDirect_TandR (uint8_t)0x0 //BIT[15:12] 0 0 00
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#define L2_UniDirect_T (uint8_t)0x1 //BIT[15:12] 0 0 01
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#define L2_UniDirect_R (uint8_t)0x2 //BIT[15:12] 0 0 10
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#define L1_BiDirect_T (uint8_t)0x8 //BIT[15:12] 1 0 00
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#define L1_BiDirect_R (uint8_t)0xc//BIT[15:12] 1 1 00
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/*NSSÏà¹ØÉèÖÃ*/
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#define NSS_PULSE 1 //ÓÐnss
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#define NO_NSS_PULSE 0 //ûÓÐnss
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#define NSS_ASSERTED 0 //
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#define NSS_DEASSERYED 1 //Èí¼þ·¢³önssÐźÅ
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#define NSS_CTRL_HW 0 //ÉèÖÃΪӲ¼þÉú³ÉNSS
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#define NSS_CTRL_SW 1 //ÉèÖÃΪÈí¼þÉú³ÉNSS
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/*²¨ÌØÂÊÉèÖÃ*/
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#define BAUD_FPCLKdiv2 (uint8_t)0x0
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#define BAUD_FPCLKdiv4 (uint8_t)0x1
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#define BAUD_FPCLKdiv8 (uint8_t)0x2
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#define BAUD_FPCLKdiv16 (uint8_t)0x3
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#define BAUD_FPCLKdiv32 (uint8_t)0x4
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#define BAUD_FPCLKdiv64 (uint8_t)0x5
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#define BAUD_FPCLKdiv128 (uint8_t)0x6
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#define BAUD_FPCLKdiv256 (uint8_t)0x7
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/*SPI_MODE ¹¤×÷ģʽѡÔñ*/
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#define SPI_MODE0 (uint8_t)0x0 //bit[3:2] 00
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#define SPI_MODE1 (uint8_t)0x1 // 01
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#define SPI_MODE2 (uint8_t)0x2 // 10
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#define SPI_MODE3 (uint8_t)0x3 // 11
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/*SAMP_PHASE Ñ¡Ïî*/
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#define PRE_1_PCLK_PERIOD (uint8_t)0X0
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#define SAMP_PHASE_NORMAL (uint8_t)0X1
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#define DELAY_1_PCLK_PERIOD (uint8_t)0X2
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#define DELAY_2_PCLK_PERIOD (uint8_t)0X3
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/*****************************ÉùÃ÷ ºÍ ¶¨Òå***************************/
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#define SPI0_CS_SET GPIO_SetOutput(GPIO_11)
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#define SPI0_CS_RESET GPIO_ResetOutput(GPIO_11)
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#define SPI1_CS_SET GPIO_SetOutput(GPIO_19)
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#define SPI1_CS_RESET GPIO_ResetOutput(GPIO_19)
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//¶ÁSPIµ±Ç°ÉèÖõÄģʽ
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extern uint8_t READ_SPI_MODE(CMSDK_SPI_TypeDef* SPIx);
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/*Çå³ýFIFOºÍ¼ÆÊýÇå0*/
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extern uint8_t CLR_TX_FIFO(CMSDK_SPI_TypeDef* SPIx);
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extern uint8_t CLR_RX_FIFO(CMSDK_SPI_TypeDef* SPIx) ;
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/*FIFO ״̬¶ÁÈ¡*/
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extern uint8_t RX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx); //¶ÁÈ¡µ±Ç°½ÓÊÕFIFOÊý¾Ý³¤¶È
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extern uint8_t TX_FIFO_LEN(CMSDK_SPI_TypeDef* SPIx) ; //¶ÁÈ¡µ±Ç°·¢ËÍFIFOÊý¾Ý³¤¶È
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extern SPI_BUSY_STATE BUSY_STATE(CMSDK_SPI_TypeDef* SPIx) ; //¶ÁÈ¡µ±Ç°SPIÊÇ·ñ·±Ã¦
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extern uint8_t RX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) ; //µ±Ç°¶ÁÈ¡FIFOÊÇ·ñΪÂú£¿
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extern uint8_t RX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) ; //µ±Ç°¶ÁÈ¡FIFOÊÇ·ñΪ¿Õ£¿
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extern uint8_t TX_FIFO_FULL(CMSDK_SPI_TypeDef* SPIx) ;//µ±Ç°·¢ËÍFIFOÊÇ·ñΪÂú£¿
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extern uint8_t TX_FIFO_EMPTY(CMSDK_SPI_TypeDef* SPIx) ; //µ±Ç°·¢ËÍFIFOÊÇ·ñΪ¿Õ£¿
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extern uint8_t SPI_FIFO_STATE(CMSDK_SPI_TypeDef* SPIx);
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extern uint8_t SPI_FIFO_ENABLE(CMSDK_SPI_TypeDef* SPIx ); //FIFO¹¦ÄÜʹÄÜ
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extern uint8_t SPI_FIFO_DISABLE(CMSDK_SPI_TypeDef* SPIx ); //FIFO¹¦ÄÜʧÄÜ
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extern uint8_t SPI_FIFODMA_SET(CMSDK_SPI_TypeDef* SPIx ,int TXDMA_SET ,int RXDMA_SET); //DMAÉèÖÃ
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extern uint8_t SPI_NSS_CHANNEL(CMSDK_SPI_TypeDef* SPIx ,NSS_CHANNEL_SEL NSSx ,FunctionalState ENorDIS); //nssͨµÀÑ¡Ôñ
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extern uint8_t SPI_Config_init(CMSDK_SPI_TypeDef* SPIx , struct SPI_ModeConfig_Struct SPI_Config ,struct SPI_FIFO_Struct FIFO_Struct); //spiµÄ³õʼÅäÖÃ
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extern uint8_t SPI_START(CMSDK_SPI_TypeDef* SPIx);
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extern uint8_t SPI_STOP(CMSDK_SPI_TypeDef* SPIx);
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//¶Á±»½ÓÊÕµÄÊý¾Ý ×î¶à16bits
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extern uint16_t READ_SPI_RCVBuff(CMSDK_SPI_TypeDef* SPIx );
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//дÊý¾Ý
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extern void WRITE_SPI_THRBuff(CMSDK_SPI_TypeDef* SPIx,uint8_t data);
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extern uint8_t SPI_INT_SET(IRQn_Type IRQn, int SPI_INT_ENABLE, uint8_t SPI_INT_BIT_SET);
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#endif
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