250 lines
8.7 KiB
C
250 lines
8.7 KiB
C
/*
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*Copyright (C),2023 , NANOCHAP
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*File name: ENS1_ADC.C
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*Author:
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*Version: V1.0
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*Date: 2023-11-
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*Description:
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*Function List:
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History:
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1.V1.0
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Date:
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Author:
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Modification: <20><><EFBFBD><EFBFBD>
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*/
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#include "ENS1_ADC.h"
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#include "ENS1_GPIO.h"
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#include "ENS1_CLOCK.h"
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#include "ENS1_ANAC.h"
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/* һ<><D2BB><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>˵<EFBFBD><CBB5><EFBFBD><EFBFBD>
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ADC<EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD>ת<EFBFBD><EFBFBD>ģʽ <20><><EFBFBD>ݸ<EFBFBD><DDB8><EFBFBD>ģʽ <20>ȴ<EFBFBD>ģʽ
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ADC<EFBFBD><EFBFBD><EFBFBD>ƣ<EFBFBD> ADCʹ<43><CAB9> <20><> ADC<44><43><EFBFBD><EFBFBD>
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ADC<EFBFBD>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD> EOC<4F>ж<EFBFBD>ʹ<EFBFBD><CAB9> <20><><EFBFBD>ݸ<EFBFBD><DDB8><EFBFBD><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
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ADC<EFBFBD>ж<EFBFBD>״̬<EFBFBD><EFBFBD> EOC<4F>жϷ<D0B6><CFB7><EFBFBD> <20><><EFBFBD>ݸ<EFBFBD><DDB8><EFBFBD><EFBFBD>жϷ<D0B6><CFB7><EFBFBD>
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ADC״̬ <20><> EOC<4F><43>־ ADC<44><43><EFBFBD>л<EFBFBD>æ״̬
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ADCʱ<EFBFBD>ӷ<EFBFBD>Ƶ <20><><EFBFBD><EFBFBD>Ƶֵ 2 4 6 8 10 12 16 32
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ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD> <20><>ADC<44><43><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> 2 3 4 5
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ADC<EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>
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ADCͨ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD> <20><>
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ADCEOC<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD> <20><> <20>Ƿ<EFBFBD><C7B7>ڽ<EFBFBD><DABD>յ<EFBFBD>EOC<4F><43>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>´<EFBFBD>ת<EFBFBD><D7AA>
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*/
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>ģʽ
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*ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ADC_START λ<><CEBB>0 <20><><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>EOC<4F><43><EFBFBD><EFBFBD>EOC_WAIT_COUNT_DONE <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>
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*<2A><><EFBFBD>ֱ<EFBFBD><D6B1>EOC_WAIT_COUNT_DONE <20><>û<EFBFBD>н<EFBFBD><D0BD>յ<EFBFBD>EOC <20><><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD>ᱻ<EFBFBD><E1B1BB><EFBFBD><EFBFBD>
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*ADC<44><43>ֹͣת<D6B9><D7AA><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD>ADC_CTRL_REG <20><> ADC_EN λ Ϊ1
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*<2A><><EFBFBD><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD>ڼ䣬ADC_EN λ<><CEBB>Ϊ0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD>е<EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD> EOC/EOC_WAIT_COUNT_DONE ֹͣת<D6B9><D7AA>
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*<2A><><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD>EOC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̣<EFBFBD>
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1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD>ģʽ<EFBFBD><EFBFBD>
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2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC_CONFIG_reg bit0 = 0 bit2 = 0
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3<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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4<EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD><EFBFBD>ADC_Data register
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5<EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD>ADC_EOC_IE<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD>
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6<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> IER<45>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD> EOC_INT_EN <20><>OVER_RUN_INT_EN λ<><CEBB><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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7<EFBFBD><EFBFBD>Ӳ<EFBFBD><EFBFBD>ֹͣADC
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*/
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/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>ģʽ
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1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC_CONFIG_reg bit0 = 1
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2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD>1 ADC_EN bit and ADC_START bits
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3<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֮<EFBFBD><EFBFBD><EFBFBD><EFBFBD>adc_eoc_config_regsiter[0] <20><><EFBFBD><EFBFBD><EFBFBD>´<EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>
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<20><><EFBFBD>Adc_eoc_config_register[0] =1 <20><> <20><><EFBFBD><EFBFBD>յ<EFBFBD>EOC<4F><43>ʼ<EFBFBD>´<EFBFBD>ת<EFBFBD><D7AA>
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<09><><EFBFBD>ݱ<EFBFBD><DDB1>浽<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>
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4<EFBFBD><EFBFBD>ADC_EOC_IE <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
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5<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD> IER<45>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD> EOC_INT_EN <20><>OVER_RUN_INT_EN λ<><CEBB><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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ע<EFBFBD>⣺ADC_eoc_config_reg<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>-<2D>ǵȴ<C7B5>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>Ч <20><><EFBFBD><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EOC<4F><43><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>ת<EFBFBD><D7AA>
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1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD>յ<EFBFBD>EOC<4F><43>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>ת<EFBFBD><D7AA>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>-<2D>ȴ<EFBFBD>ģʽ<C4A3>£<EFBFBD>ADC_eoc_config_regӦ<67>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD>Ϊ0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*/
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/*<2A>ġ<EFBFBD><C4A1>ȴ<EFBFBD>ģʽ
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1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC_CONFIG_reg bit2 = 1 <20><>ʹ<EFBFBD>ܵȴ<DCB5>ģʽ<C4A3><CABD>
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2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD>
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3<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD>
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<20><>ADC<44><43><EFBFBD>ݵ<EFBFBD><DDB5><EFBFBD>Ӧ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>
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ADC_EOC_IE <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
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<20><><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD> IER<45>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD> EOC_INT_EN <20><>OVER_RUN_INT_EN λ<><CEBB><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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4<EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>뵽ADC_WAIT <20>ȴ<EFBFBD>״ֱ̬<CCAC><D6B1>EOC<4F>жϱ<D0B6><CFB1><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> ADC<44><43><EFBFBD>ݱ<EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>
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5<EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD>EOC<EFBFBD>жϱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>һ<EFBFBD>ε<EFBFBD>ת<EFBFBD><EFBFBD>
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*/
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/*<2A>塢<EFBFBD><E5A1A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>EOC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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2<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> OVERRUNģʽ<C4A3><CABD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3>µ<EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD>ᱻ<EFBFBD><E1B1BB><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> overrun <20><><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD>
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ע<EFBFBD>⣺ <20><><EFBFBD>overrun ģʽû<CABD>б<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD> <20>µĻ<C2B5><C4BB>߾ɵ<DFBE>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD>overrun <20><><EFBFBD><EFBFBD>״̬ѡ<CCAC><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<20><><EFBFBD><EFBFBD> <20><><EFBFBD>overrun <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD>ᱻ<EFBFBD><E1B1BB><EFBFBD><EFBFBD>
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<20><><EFBFBD>û<EFBFBD><C3BB>overrun <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*/
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/*<2A><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>˵<EFBFBD><CBB5>
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1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD>EOC<EFBFBD><EFBFBD> EOC_IR <20><><EFBFBD><EFBFBD>
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2<EFBFBD><EFBFBD>OVERRUN<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>OVERRUN_IR <20><><EFBFBD><EFBFBD>
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3<EFBFBD><EFBFBD>EOC_IR <20><>overrun <20><>ΪADC<44>жϱ<D0B6> ͨ<><CDA8><EFBFBD><EFBFBD>ϵͳ
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<20><>ϵͳͨ<CDB3><CDA8> data_reg <20><>ȡ<EFBFBD><C8A1>adc<64><63><EFBFBD>ݺ<EFBFBD> EOC_IR <20><> EOC_IR_CLEAR <20><><EFBFBD>
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*/
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/*overrun <20><><EFBFBD><EFBFBD>
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<20>˴<EFBFBD><CBB4><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ǣ<EFBFBD> ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3>ȡ<EFBFBD><C8A1>ADC<44><43><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>EOC_IRǰ<52><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5>µ<EFBFBD>EOC
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*/
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volatile uint8_t ADC_READ_STATUS = ADC_READ_DATA_IS_WAITING;
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uint8_t ADC_UART_BYTE_LOW = 0;
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uint8_t ADC_UART_BYTE_HIGH = 0;
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uint8_t ENS1_ADCCLKConfig(uint8_t ADC_CLK_div)
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{
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CMSDK_ADC->ADC_CLK_DIV = ((CMSDK_ADC->ADC_CLK_DIV &~ (0x7)) | (ADC_CLK_div));
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return 0;
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}
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/*
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ENS_ADC_COV_MODE COV_MODE
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ENS_ADC_OVERRUN_MODE OVERRUN_MODE
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WAIT_MODE WAITorNOT
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*/
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uint8_t ENS1_ADC_CONFIG(ENS_ADC_SEL channelx ,
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uint8_t MODE_SEL,
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ENS_ADC_COV_INC_EOC EOC_CONFIG ,
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uint8_t SIMLING_TIME,
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uint8_t INT_MODE_SEL)
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{
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NVIC_ClearPendingIRQ(ADC_IRQn);
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NVIC_DisableIRQ(ADC_IRQn);
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if(channelx == ENS1_ADC_CHANNEL1)
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{
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CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<10))|(0x03<<10);
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CMSDK_GPIO->ANAEN |= (1 << 21);
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CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
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CMSDK_ADC->ADC_CH_SEL = 1;
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}
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else if(channelx == ENS1_ADC_CHANNEL2)
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{
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CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<12))|(0x03<<12);
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CMSDK_GPIO->ANAEN |= (1 << 22);
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CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
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CMSDK_ADC->ADC_CH_SEL = 2;
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}
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else if(channelx == ENS1_ADC_CHANNEL3)
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{
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CMSDK_GPIO->ALTFH = (CMSDK_GPIO->ALTFH &~ (0x03<<14))|(0x03<<14);
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CMSDK_GPIO->ANAEN |= (1 << 23);
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CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
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CMSDK_ADC->ADC_CH_SEL = 3;
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}
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else
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{
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CMSDK_ADC->ADC_CH_SEL &=~ (0x7);
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CMSDK_ADC->ADC_CH_SEL = 0;
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}
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CMSDK_ADC->ADC_CONFG =(CMSDK_ADC->ADC_CONFG &~ 0x7 )| MODE_SEL;
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CMSDK_ADC->ADC_SAMP_TIME = (CMSDK_ADC->ADC_SAMP_TIME &~ 0x3) | SIMLING_TIME;
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//<2F><><EFBFBD><EFBFBD>ADC_eoc_config_reg<65>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>-<2D>ǵȴ<C7B5>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>
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if( ((MODE_SEL & 0X1 )== 1 ) && (MODE_SEL & 0X4) == 0)
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{
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CMSDK_ADC->ADC_EOC_CONFG = (CMSDK_ADC->ADC_EOC_CONFG &~ (0x1)) | EOC_CONFIG;
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}
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//<2F>ж<EFBFBD>ʹ<EFBFBD><CAB9>
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CMSDK_ADC->ADC_IER = (CMSDK_ADC->ADC_IER &~ (0x3)) | ( INT_MODE_SEL );
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return CMSDK_ADC->ADC_CONFG;
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}
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uint8_t ENS1_ADC_START(ENS_ADC_SEL channelx )
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{
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CMSDK_ADC->ADC_CTRL |= (1) |(1<<8);
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if(CMSDK_ADC->ADC_IER != 0)
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{
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NVIC_EnableIRQ(ADC_IRQn);
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}
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return 0;
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}
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uint8_t ENS1_ADC_STOP(ENS_ADC_SEL channelx)
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{
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CMSDK_ADC->ADC_CTRL &=~ (1);
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NVIC_DisableIRQ(ADC_IRQn);
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return 0;
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}
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
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//ADC<44>ڲ<EFBFBD>ͬģʽ<C4A3><CABD><EFBFBD>в<EFBFBD>ͬ<EFBFBD>IJɼ<C4B2><C9BC><EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Adc_config_register<65><72><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>8<EFBFBD><38>ģʽ
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uint16_t save_data;
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uint8_t ADC_CONFIG_READ;
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//<2F>˺<EFBFBD><CBBA><EFBFBD>δ<EFBFBD><CEB4>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɼ<EFBFBD>+<2B>ж<EFBFBD>ģʽ<C4A3><CABD><EFBFBD>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
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uint16_t ADC_READ_DATA(void)
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{
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ADC_CONFIG_READ = CMSDK_ADC->ADC_CONFG;
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switch(ADC_CONFIG_READ & 0x7) {
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case single_mode_without_overrun_without_wait :
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while(ADC_READ_STATUS == ADC_READ_DATA_IS_WAITING); //<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD>EOC<4F>ĵ<EFBFBD><C4B5><EFBFBD>
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ADC_READ_STATUS = ADC_READ_DATA_IS_WAITING; //<2F>жϷ<D0B6><CFB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѿ<EFBFBD><D1BE><EFBFBD>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˣ<EFBFBD><CBA3><EFBFBD>ʱ<EFBFBD>ٽ<EFBFBD>״̬<D7B4>л<EFBFBD><D0BB><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||
|
||
break;
|
||
|
||
case continious_mode_without_overrun_without_wait :
|
||
|
||
break;
|
||
|
||
case single_mode_with_overrun_without_wait :
|
||
|
||
break;
|
||
|
||
case continious_mode_with_overrun_without_wait :
|
||
|
||
break;
|
||
|
||
case single_mode_without_overrun_with_wait :
|
||
|
||
|
||
|
||
break;
|
||
|
||
case Continious_mode_without_overun_with_wait :
|
||
|
||
break;
|
||
|
||
case single_mode_with_overrun_with_wait :
|
||
|
||
break;
|
||
|
||
case continious_mode_with_overrun_with_wait :
|
||
|
||
break;
|
||
|
||
}
|
||
return (uint16_t)save_data;
|
||
}
|
||
|
||
//ADC interrupt handler
|
||
void ADC_Handler(void) __irq
|
||
{
|
||
if((CMSDK_ADC->ADC_ISR & 0x01) == 0x01) //<2F><><EFBFBD>յ<EFBFBD>EOC
|
||
{
|
||
CMSDK_ADC->ADC_INT_CLR = (0x01<<0);
|
||
ADC_READ_STATUS = ADC_READ_DATA_IS_READY;
|
||
save_data = (CMSDK_ADC->ADC_DATA & 0x0fff); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݺ<DDBA><F3A3ACBF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>βɼ<CEB2>
|
||
ADC_UART_BYTE_LOW = save_data&0xff;
|
||
ADC_UART_BYTE_HIGH = (save_data&0x0f00)>>8;
|
||
}
|
||
if(((CMSDK_ADC->ADC_ISR & 0x02)>>1) == 0x01) //overrun error
|
||
{
|
||
CMSDK_ADC->ADC_INT_CLR = (0x01<<1);
|
||
}
|
||
}
|
||
|
||
|
||
|
||
|